Alkis Evlogimenos | 34d9bc9 | 2004-02-23 23:08:11 +0000 | [diff] [blame] | 1 | //===-- llvm/CodeGen/VirtRegMap.cpp - Virtual Register Map ----------------===// |
| 2 | // |
| 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
| 5 | // This file was developed by the LLVM research group and is distributed under |
| 6 | // the University of Illinois Open Source License. See LICENSE.TXT for details. |
| 7 | // |
| 8 | //===----------------------------------------------------------------------===// |
| 9 | // |
Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 10 | // This file implements the VirtRegMap class. |
| 11 | // |
| 12 | // It also contains implementations of the the Spiller interface, which, given a |
| 13 | // virtual register map and a machine function, eliminates all virtual |
| 14 | // references by replacing them with physical register references - adding spill |
Alkis Evlogimenos | 0d6c5b6 | 2004-02-24 08:58:30 +0000 | [diff] [blame] | 15 | // code as necessary. |
Alkis Evlogimenos | 34d9bc9 | 2004-02-23 23:08:11 +0000 | [diff] [blame] | 16 | // |
| 17 | //===----------------------------------------------------------------------===// |
| 18 | |
Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 19 | #define DEBUG_TYPE "spiller" |
Alkis Evlogimenos | 34d9bc9 | 2004-02-23 23:08:11 +0000 | [diff] [blame] | 20 | #include "VirtRegMap.h" |
Alkis Evlogimenos | 0d6c5b6 | 2004-02-24 08:58:30 +0000 | [diff] [blame] | 21 | #include "llvm/Function.h" |
Alkis Evlogimenos | 34d9bc9 | 2004-02-23 23:08:11 +0000 | [diff] [blame] | 22 | #include "llvm/CodeGen/MachineFrameInfo.h" |
Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 23 | #include "llvm/CodeGen/MachineFunction.h" |
| 24 | #include "llvm/CodeGen/SSARegMap.h" |
Alkis Evlogimenos | 34d9bc9 | 2004-02-23 23:08:11 +0000 | [diff] [blame] | 25 | #include "llvm/Target/TargetMachine.h" |
Alkis Evlogimenos | 0d6c5b6 | 2004-02-24 08:58:30 +0000 | [diff] [blame] | 26 | #include "llvm/Target/TargetInstrInfo.h" |
Reid Spencer | 551ccae | 2004-09-01 22:55:40 +0000 | [diff] [blame] | 27 | #include "llvm/Support/CommandLine.h" |
| 28 | #include "llvm/Support/Debug.h" |
Chris Lattner | a4f0b3a | 2006-08-27 12:54:02 +0000 | [diff] [blame] | 29 | #include "llvm/Support/Compiler.h" |
Evan Cheng | 957840b | 2007-02-21 02:22:03 +0000 | [diff] [blame] | 30 | #include "llvm/ADT/BitVector.h" |
Reid Spencer | 551ccae | 2004-09-01 22:55:40 +0000 | [diff] [blame] | 31 | #include "llvm/ADT/Statistic.h" |
| 32 | #include "llvm/ADT/STLExtras.h" |
Chris Lattner | 08a4d5a | 2007-01-23 00:59:48 +0000 | [diff] [blame] | 33 | #include "llvm/ADT/SmallSet.h" |
Chris Lattner | 27f2916 | 2004-10-26 15:35:58 +0000 | [diff] [blame] | 34 | #include <algorithm> |
Alkis Evlogimenos | 34d9bc9 | 2004-02-23 23:08:11 +0000 | [diff] [blame] | 35 | using namespace llvm; |
| 36 | |
Chris Lattner | cd3245a | 2006-12-19 22:41:21 +0000 | [diff] [blame] | 37 | STATISTIC(NumSpills, "Number of register spills"); |
Evan Cheng | 2638e1a | 2007-03-20 08:13:50 +0000 | [diff] [blame] | 38 | STATISTIC(NumReMats, "Number of re-materialization"); |
Evan Cheng | b6ca4b3 | 2007-08-14 23:25:37 +0000 | [diff] [blame] | 39 | STATISTIC(NumDRM , "Number of re-materializable defs elided"); |
Chris Lattner | cd3245a | 2006-12-19 22:41:21 +0000 | [diff] [blame] | 40 | STATISTIC(NumStores, "Number of stores added"); |
| 41 | STATISTIC(NumLoads , "Number of loads added"); |
| 42 | STATISTIC(NumReused, "Number of values reused"); |
| 43 | STATISTIC(NumDSE , "Number of dead stores elided"); |
| 44 | STATISTIC(NumDCE , "Number of copies elided"); |
Alkis Evlogimenos | 0d6c5b6 | 2004-02-24 08:58:30 +0000 | [diff] [blame] | 45 | |
Chris Lattner | cd3245a | 2006-12-19 22:41:21 +0000 | [diff] [blame] | 46 | namespace { |
Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 47 | enum SpillerName { simple, local }; |
Alkis Evlogimenos | dd420e0 | 2004-03-01 23:18:15 +0000 | [diff] [blame] | 48 | |
Andrew Lenharth | ed41f1b | 2006-07-20 17:28:38 +0000 | [diff] [blame] | 49 | static cl::opt<SpillerName> |
Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 50 | SpillerOpt("spiller", |
Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 51 | cl::desc("Spiller to use: (default: local)"), |
Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 52 | cl::Prefix, |
| 53 | cl::values(clEnumVal(simple, " simple spiller"), |
| 54 | clEnumVal(local, " local spiller"), |
| 55 | clEnumValEnd), |
Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 56 | cl::init(local)); |
Alkis Evlogimenos | 34d9bc9 | 2004-02-23 23:08:11 +0000 | [diff] [blame] | 57 | } |
| 58 | |
Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 59 | //===----------------------------------------------------------------------===// |
| 60 | // VirtRegMap implementation |
| 61 | //===----------------------------------------------------------------------===// |
| 62 | |
Chris Lattner | 2926869 | 2006-09-05 02:12:02 +0000 | [diff] [blame] | 63 | VirtRegMap::VirtRegMap(MachineFunction &mf) |
| 64 | : TII(*mf.getTarget().getInstrInfo()), MF(mf), |
Evan Cheng | 2638e1a | 2007-03-20 08:13:50 +0000 | [diff] [blame] | 65 | Virt2PhysMap(NO_PHYS_REG), Virt2StackSlotMap(NO_STACK_SLOT), |
Evan Cheng | 81a0382 | 2007-11-17 00:40:40 +0000 | [diff] [blame] | 66 | Virt2ReMatIdMap(NO_STACK_SLOT), Virt2SplitMap(0), |
Evan Cheng | d120ffd | 2007-12-05 10:24:35 +0000 | [diff] [blame^] | 67 | Virt2SplitKillMap(0), ReMatMap(NULL), ReMatId(MAX_STACK_SLOT+1) { |
Chris Lattner | 2926869 | 2006-09-05 02:12:02 +0000 | [diff] [blame] | 68 | grow(); |
| 69 | } |
| 70 | |
Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 71 | void VirtRegMap::grow() { |
Evan Cheng | 549f27d3 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 72 | unsigned LastVirtReg = MF.getSSARegMap()->getLastVirtReg(); |
| 73 | Virt2PhysMap.grow(LastVirtReg); |
| 74 | Virt2StackSlotMap.grow(LastVirtReg); |
| 75 | Virt2ReMatIdMap.grow(LastVirtReg); |
Evan Cheng | 81a0382 | 2007-11-17 00:40:40 +0000 | [diff] [blame] | 76 | Virt2SplitMap.grow(LastVirtReg); |
Evan Cheng | adf8590 | 2007-12-05 09:51:10 +0000 | [diff] [blame] | 77 | Virt2SplitKillMap.grow(LastVirtReg); |
Evan Cheng | 549f27d3 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 78 | ReMatMap.grow(LastVirtReg); |
Alkis Evlogimenos | 34d9bc9 | 2004-02-23 23:08:11 +0000 | [diff] [blame] | 79 | } |
| 80 | |
Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 81 | int VirtRegMap::assignVirt2StackSlot(unsigned virtReg) { |
| 82 | assert(MRegisterInfo::isVirtualRegister(virtReg)); |
Chris Lattner | 7f690e6 | 2004-09-30 02:15:18 +0000 | [diff] [blame] | 83 | assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT && |
Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 84 | "attempt to assign stack slot to already spilled register"); |
Chris Lattner | 7f690e6 | 2004-09-30 02:15:18 +0000 | [diff] [blame] | 85 | const TargetRegisterClass* RC = MF.getSSARegMap()->getRegClass(virtReg); |
| 86 | int frameIndex = MF.getFrameInfo()->CreateStackObject(RC->getSize(), |
| 87 | RC->getAlignment()); |
| 88 | Virt2StackSlotMap[virtReg] = frameIndex; |
Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 89 | ++NumSpills; |
| 90 | return frameIndex; |
| 91 | } |
| 92 | |
| 93 | void VirtRegMap::assignVirt2StackSlot(unsigned virtReg, int frameIndex) { |
| 94 | assert(MRegisterInfo::isVirtualRegister(virtReg)); |
Chris Lattner | 7f690e6 | 2004-09-30 02:15:18 +0000 | [diff] [blame] | 95 | assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT && |
Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 96 | "attempt to assign stack slot to already spilled register"); |
Evan Cheng | 9193514 | 2007-04-04 07:40:01 +0000 | [diff] [blame] | 97 | assert((frameIndex >= 0 || |
| 98 | (frameIndex >= MF.getFrameInfo()->getObjectIndexBegin())) && |
| 99 | "illegal fixed frame index"); |
Chris Lattner | 7f690e6 | 2004-09-30 02:15:18 +0000 | [diff] [blame] | 100 | Virt2StackSlotMap[virtReg] = frameIndex; |
Alkis Evlogimenos | 38af59a | 2004-05-29 20:38:05 +0000 | [diff] [blame] | 101 | } |
| 102 | |
Evan Cheng | 2638e1a | 2007-03-20 08:13:50 +0000 | [diff] [blame] | 103 | int VirtRegMap::assignVirtReMatId(unsigned virtReg) { |
| 104 | assert(MRegisterInfo::isVirtualRegister(virtReg)); |
Evan Cheng | 549f27d3 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 105 | assert(Virt2ReMatIdMap[virtReg] == NO_STACK_SLOT && |
Evan Cheng | 2638e1a | 2007-03-20 08:13:50 +0000 | [diff] [blame] | 106 | "attempt to assign re-mat id to already spilled register"); |
Evan Cheng | 549f27d3 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 107 | Virt2ReMatIdMap[virtReg] = ReMatId; |
Evan Cheng | 2638e1a | 2007-03-20 08:13:50 +0000 | [diff] [blame] | 108 | return ReMatId++; |
| 109 | } |
| 110 | |
Evan Cheng | 549f27d3 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 111 | void VirtRegMap::assignVirtReMatId(unsigned virtReg, int id) { |
| 112 | assert(MRegisterInfo::isVirtualRegister(virtReg)); |
| 113 | assert(Virt2ReMatIdMap[virtReg] == NO_STACK_SLOT && |
| 114 | "attempt to assign re-mat id to already spilled register"); |
| 115 | Virt2ReMatIdMap[virtReg] = id; |
| 116 | } |
| 117 | |
Chris Lattner | bec6a9e | 2004-10-01 23:15:36 +0000 | [diff] [blame] | 118 | void VirtRegMap::virtFolded(unsigned VirtReg, MachineInstr *OldMI, |
Evan Cheng | aee4af6 | 2007-12-02 08:30:39 +0000 | [diff] [blame] | 119 | MachineInstr *NewMI, ModRef MRInfo) { |
Chris Lattner | bec6a9e | 2004-10-01 23:15:36 +0000 | [diff] [blame] | 120 | // Move previous memory references folded to new instruction. |
| 121 | MI2VirtMapTy::iterator IP = MI2VirtMap.lower_bound(NewMI); |
Misha Brukman | edf128a | 2005-04-21 22:36:52 +0000 | [diff] [blame] | 122 | for (MI2VirtMapTy::iterator I = MI2VirtMap.lower_bound(OldMI), |
Chris Lattner | bec6a9e | 2004-10-01 23:15:36 +0000 | [diff] [blame] | 123 | E = MI2VirtMap.end(); I != E && I->first == OldMI; ) { |
| 124 | MI2VirtMap.insert(IP, std::make_pair(NewMI, I->second)); |
Chris Lattner | dbea973 | 2004-09-30 16:35:08 +0000 | [diff] [blame] | 125 | MI2VirtMap.erase(I++); |
Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 126 | } |
Chris Lattner | dbea973 | 2004-09-30 16:35:08 +0000 | [diff] [blame] | 127 | |
Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 128 | // add new memory reference |
Chris Lattner | bec6a9e | 2004-10-01 23:15:36 +0000 | [diff] [blame] | 129 | MI2VirtMap.insert(IP, std::make_pair(NewMI, std::make_pair(VirtReg, MRInfo))); |
Alkis Evlogimenos | 5f37502 | 2004-03-01 20:05:10 +0000 | [diff] [blame] | 130 | } |
| 131 | |
Evan Cheng | 7f56625 | 2007-10-13 02:50:24 +0000 | [diff] [blame] | 132 | void VirtRegMap::virtFolded(unsigned VirtReg, MachineInstr *MI, ModRef MRInfo) { |
| 133 | MI2VirtMapTy::iterator IP = MI2VirtMap.lower_bound(MI); |
| 134 | MI2VirtMap.insert(IP, std::make_pair(MI, std::make_pair(VirtReg, MRInfo))); |
| 135 | } |
| 136 | |
Chris Lattner | 7f690e6 | 2004-09-30 02:15:18 +0000 | [diff] [blame] | 137 | void VirtRegMap::print(std::ostream &OS) const { |
| 138 | const MRegisterInfo* MRI = MF.getTarget().getRegisterInfo(); |
Alkis Evlogimenos | 34d9bc9 | 2004-02-23 23:08:11 +0000 | [diff] [blame] | 139 | |
Chris Lattner | 7f690e6 | 2004-09-30 02:15:18 +0000 | [diff] [blame] | 140 | OS << "********** REGISTER MAP **********\n"; |
Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 141 | for (unsigned i = MRegisterInfo::FirstVirtualRegister, |
Chris Lattner | 7f690e6 | 2004-09-30 02:15:18 +0000 | [diff] [blame] | 142 | e = MF.getSSARegMap()->getLastVirtReg(); i <= e; ++i) { |
| 143 | if (Virt2PhysMap[i] != (unsigned)VirtRegMap::NO_PHYS_REG) |
| 144 | OS << "[reg" << i << " -> " << MRI->getName(Virt2PhysMap[i]) << "]\n"; |
Misha Brukman | edf128a | 2005-04-21 22:36:52 +0000 | [diff] [blame] | 145 | |
Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 146 | } |
| 147 | |
| 148 | for (unsigned i = MRegisterInfo::FirstVirtualRegister, |
Chris Lattner | 7f690e6 | 2004-09-30 02:15:18 +0000 | [diff] [blame] | 149 | e = MF.getSSARegMap()->getLastVirtReg(); i <= e; ++i) |
| 150 | if (Virt2StackSlotMap[i] != VirtRegMap::NO_STACK_SLOT) |
| 151 | OS << "[reg" << i << " -> fi#" << Virt2StackSlotMap[i] << "]\n"; |
| 152 | OS << '\n'; |
Alkis Evlogimenos | 34d9bc9 | 2004-02-23 23:08:11 +0000 | [diff] [blame] | 153 | } |
Alkis Evlogimenos | 0d6c5b6 | 2004-02-24 08:58:30 +0000 | [diff] [blame] | 154 | |
Bill Wendling | b2b9c20 | 2006-11-17 02:09:07 +0000 | [diff] [blame] | 155 | void VirtRegMap::dump() const { |
Bill Wendling | 5c7e326 | 2006-12-17 05:15:13 +0000 | [diff] [blame] | 156 | print(DOUT); |
Bill Wendling | b2b9c20 | 2006-11-17 02:09:07 +0000 | [diff] [blame] | 157 | } |
Alkis Evlogimenos | dd420e0 | 2004-03-01 23:18:15 +0000 | [diff] [blame] | 158 | |
Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 159 | |
| 160 | //===----------------------------------------------------------------------===// |
| 161 | // Simple Spiller Implementation |
| 162 | //===----------------------------------------------------------------------===// |
| 163 | |
| 164 | Spiller::~Spiller() {} |
Alkis Evlogimenos | dd420e0 | 2004-03-01 23:18:15 +0000 | [diff] [blame] | 165 | |
Alkis Evlogimenos | 0d6c5b6 | 2004-02-24 08:58:30 +0000 | [diff] [blame] | 166 | namespace { |
Chris Lattner | f8c68f6 | 2006-06-28 22:17:39 +0000 | [diff] [blame] | 167 | struct VISIBILITY_HIDDEN SimpleSpiller : public Spiller { |
Chris Lattner | 35f2705 | 2006-05-01 21:16:03 +0000 | [diff] [blame] | 168 | bool runOnMachineFunction(MachineFunction& mf, VirtRegMap &VRM); |
Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 169 | }; |
Alkis Evlogimenos | 0d6c5b6 | 2004-02-24 08:58:30 +0000 | [diff] [blame] | 170 | } |
| 171 | |
Chris Lattner | 35f2705 | 2006-05-01 21:16:03 +0000 | [diff] [blame] | 172 | bool SimpleSpiller::runOnMachineFunction(MachineFunction &MF, VirtRegMap &VRM) { |
Bill Wendling | b2b9c20 | 2006-11-17 02:09:07 +0000 | [diff] [blame] | 173 | DOUT << "********** REWRITE MACHINE CODE **********\n"; |
| 174 | DOUT << "********** Function: " << MF.getFunction()->getName() << '\n'; |
Chris Lattner | b0f31bf | 2005-01-23 22:45:13 +0000 | [diff] [blame] | 175 | const TargetMachine &TM = MF.getTarget(); |
| 176 | const MRegisterInfo &MRI = *TM.getRegisterInfo(); |
Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 177 | |
Chris Lattner | 4ea1b82 | 2004-09-30 02:33:48 +0000 | [diff] [blame] | 178 | // LoadedRegs - Keep track of which vregs are loaded, so that we only load |
| 179 | // each vreg once (in the case where a spilled vreg is used by multiple |
| 180 | // operands). This is always smaller than the number of operands to the |
| 181 | // current machine instr, so it should be small. |
| 182 | std::vector<unsigned> LoadedRegs; |
Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 183 | |
Chris Lattner | 0fc27cc | 2004-09-30 02:59:33 +0000 | [diff] [blame] | 184 | for (MachineFunction::iterator MBBI = MF.begin(), E = MF.end(); |
| 185 | MBBI != E; ++MBBI) { |
Bill Wendling | b2b9c20 | 2006-11-17 02:09:07 +0000 | [diff] [blame] | 186 | DOUT << MBBI->getBasicBlock()->getName() << ":\n"; |
Chris Lattner | 0fc27cc | 2004-09-30 02:59:33 +0000 | [diff] [blame] | 187 | MachineBasicBlock &MBB = *MBBI; |
| 188 | for (MachineBasicBlock::iterator MII = MBB.begin(), |
| 189 | E = MBB.end(); MII != E; ++MII) { |
| 190 | MachineInstr &MI = *MII; |
| 191 | for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) { |
Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 192 | MachineOperand &MO = MI.getOperand(i); |
Chris Lattner | 886dd91 | 2005-04-04 21:35:34 +0000 | [diff] [blame] | 193 | if (MO.isRegister() && MO.getReg()) |
| 194 | if (MRegisterInfo::isVirtualRegister(MO.getReg())) { |
| 195 | unsigned VirtReg = MO.getReg(); |
| 196 | unsigned PhysReg = VRM.getPhys(VirtReg); |
Evan Cheng | 549f27d3 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 197 | if (!VRM.isAssignedReg(VirtReg)) { |
Chris Lattner | 886dd91 | 2005-04-04 21:35:34 +0000 | [diff] [blame] | 198 | int StackSlot = VRM.getStackSlot(VirtReg); |
Chris Lattner | bf9716b | 2005-09-30 01:29:00 +0000 | [diff] [blame] | 199 | const TargetRegisterClass* RC = |
| 200 | MF.getSSARegMap()->getRegClass(VirtReg); |
Misha Brukman | edf128a | 2005-04-21 22:36:52 +0000 | [diff] [blame] | 201 | |
Chris Lattner | 886dd91 | 2005-04-04 21:35:34 +0000 | [diff] [blame] | 202 | if (MO.isUse() && |
| 203 | std::find(LoadedRegs.begin(), LoadedRegs.end(), VirtReg) |
| 204 | == LoadedRegs.end()) { |
Chris Lattner | bf9716b | 2005-09-30 01:29:00 +0000 | [diff] [blame] | 205 | MRI.loadRegFromStackSlot(MBB, &MI, PhysReg, StackSlot, RC); |
Chris Lattner | 886dd91 | 2005-04-04 21:35:34 +0000 | [diff] [blame] | 206 | LoadedRegs.push_back(VirtReg); |
| 207 | ++NumLoads; |
Bill Wendling | b2b9c20 | 2006-11-17 02:09:07 +0000 | [diff] [blame] | 208 | DOUT << '\t' << *prior(MII); |
Chris Lattner | 886dd91 | 2005-04-04 21:35:34 +0000 | [diff] [blame] | 209 | } |
Misha Brukman | edf128a | 2005-04-21 22:36:52 +0000 | [diff] [blame] | 210 | |
Chris Lattner | 886dd91 | 2005-04-04 21:35:34 +0000 | [diff] [blame] | 211 | if (MO.isDef()) { |
Evan Cheng | d64b5c8 | 2007-12-05 03:14:33 +0000 | [diff] [blame] | 212 | MRI.storeRegToStackSlot(MBB, next(MII), PhysReg, true, |
| 213 | StackSlot, RC); |
Chris Lattner | 886dd91 | 2005-04-04 21:35:34 +0000 | [diff] [blame] | 214 | ++NumStores; |
| 215 | } |
Chris Lattner | 0fc27cc | 2004-09-30 02:59:33 +0000 | [diff] [blame] | 216 | } |
Evan Cheng | 6c087e5 | 2007-04-25 22:13:27 +0000 | [diff] [blame] | 217 | MF.setPhysRegUsed(PhysReg); |
Chris Lattner | e53f4a0 | 2006-05-04 17:52:23 +0000 | [diff] [blame] | 218 | MI.getOperand(i).setReg(PhysReg); |
Chris Lattner | 886dd91 | 2005-04-04 21:35:34 +0000 | [diff] [blame] | 219 | } else { |
Evan Cheng | 6c087e5 | 2007-04-25 22:13:27 +0000 | [diff] [blame] | 220 | MF.setPhysRegUsed(MO.getReg()); |
Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 221 | } |
Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 222 | } |
Chris Lattner | 886dd91 | 2005-04-04 21:35:34 +0000 | [diff] [blame] | 223 | |
Bill Wendling | b2b9c20 | 2006-11-17 02:09:07 +0000 | [diff] [blame] | 224 | DOUT << '\t' << MI; |
Chris Lattner | 4ea1b82 | 2004-09-30 02:33:48 +0000 | [diff] [blame] | 225 | LoadedRegs.clear(); |
Alkis Evlogimenos | dd420e0 | 2004-03-01 23:18:15 +0000 | [diff] [blame] | 226 | } |
Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 227 | } |
| 228 | return true; |
| 229 | } |
| 230 | |
| 231 | //===----------------------------------------------------------------------===// |
| 232 | // Local Spiller Implementation |
| 233 | //===----------------------------------------------------------------------===// |
| 234 | |
| 235 | namespace { |
Evan Cheng | 66f7163 | 2007-10-19 21:23:22 +0000 | [diff] [blame] | 236 | class AvailableSpills; |
| 237 | |
Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 238 | /// LocalSpiller - This spiller does a simple pass over the machine basic |
| 239 | /// block to attempt to keep spills in registers as much as possible for |
| 240 | /// blocks that have low register pressure (the vreg may be spilled due to |
| 241 | /// register pressure in other blocks). |
Chris Lattner | f8c68f6 | 2006-06-28 22:17:39 +0000 | [diff] [blame] | 242 | class VISIBILITY_HIDDEN LocalSpiller : public Spiller { |
Evan Cheng | 32dfbea | 2007-10-12 08:50:34 +0000 | [diff] [blame] | 243 | SSARegMap *RegMap; |
Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 244 | const MRegisterInfo *MRI; |
Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 245 | const TargetInstrInfo *TII; |
Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 246 | public: |
Chris Lattner | 35f2705 | 2006-05-01 21:16:03 +0000 | [diff] [blame] | 247 | bool runOnMachineFunction(MachineFunction &MF, VirtRegMap &VRM) { |
Evan Cheng | 32dfbea | 2007-10-12 08:50:34 +0000 | [diff] [blame] | 248 | RegMap = MF.getSSARegMap(); |
Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 249 | MRI = MF.getTarget().getRegisterInfo(); |
| 250 | TII = MF.getTarget().getInstrInfo(); |
Bill Wendling | b2b9c20 | 2006-11-17 02:09:07 +0000 | [diff] [blame] | 251 | DOUT << "\n**** Local spiller rewriting function '" |
| 252 | << MF.getFunction()->getName() << "':\n"; |
David Greene | 04fa32f | 2007-09-06 16:36:39 +0000 | [diff] [blame] | 253 | DOUT << "**** Machine Instrs (NOTE! Does not include spills and reloads!) ****\n"; |
| 254 | DEBUG(MF.dump()); |
Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 255 | |
Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 256 | for (MachineFunction::iterator MBB = MF.begin(), E = MF.end(); |
| 257 | MBB != E; ++MBB) |
Evan Cheng | 549f27d3 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 258 | RewriteMBB(*MBB, VRM); |
David Greene | 04fa32f | 2007-09-06 16:36:39 +0000 | [diff] [blame] | 259 | |
| 260 | DOUT << "**** Post Machine Instrs ****\n"; |
| 261 | DEBUG(MF.dump()); |
| 262 | |
Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 263 | return true; |
| 264 | } |
Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 265 | private: |
Evan Cheng | 66f7163 | 2007-10-19 21:23:22 +0000 | [diff] [blame] | 266 | bool PrepForUnfoldOpti(MachineBasicBlock &MBB, |
| 267 | MachineBasicBlock::iterator &MII, |
| 268 | std::vector<MachineInstr*> &MaybeDeadStores, |
| 269 | AvailableSpills &Spills, BitVector &RegKills, |
| 270 | std::vector<MachineOperand*> &KillOps, |
| 271 | VirtRegMap &VRM); |
Evan Cheng | 81a0382 | 2007-11-17 00:40:40 +0000 | [diff] [blame] | 272 | void SpillRegToStackSlot(MachineBasicBlock &MBB, |
| 273 | MachineBasicBlock::iterator &MII, |
| 274 | int Idx, unsigned PhysReg, int StackSlot, |
| 275 | const TargetRegisterClass *RC, |
Evan Cheng | 35a3e4a | 2007-12-04 19:19:45 +0000 | [diff] [blame] | 276 | bool isAvailable, MachineInstr *&LastStore, |
Evan Cheng | 81a0382 | 2007-11-17 00:40:40 +0000 | [diff] [blame] | 277 | AvailableSpills &Spills, |
| 278 | SmallSet<MachineInstr*, 4> &ReMatDefs, |
| 279 | BitVector &RegKills, |
| 280 | std::vector<MachineOperand*> &KillOps, |
Evan Cheng | e4b3900 | 2007-12-03 21:31:55 +0000 | [diff] [blame] | 281 | VirtRegMap &VRM); |
Evan Cheng | 549f27d3 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 282 | void RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM); |
Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 283 | }; |
| 284 | } |
| 285 | |
Chris Lattner | 66cf80f | 2006-02-03 23:13:58 +0000 | [diff] [blame] | 286 | /// AvailableSpills - As the local spiller is scanning and rewriting an MBB from |
Evan Cheng | 549f27d3 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 287 | /// top down, keep track of which spills slots or remat are available in each |
| 288 | /// register. |
Chris Lattner | 593c958 | 2006-02-03 23:28:46 +0000 | [diff] [blame] | 289 | /// |
| 290 | /// Note that not all physregs are created equal here. In particular, some |
| 291 | /// physregs are reloads that we are allowed to clobber or ignore at any time. |
| 292 | /// Other physregs are values that the register allocated program is using that |
| 293 | /// we cannot CHANGE, but we can read if we like. We keep track of this on a |
Evan Cheng | 549f27d3 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 294 | /// per-stack-slot / remat id basis as the low bit in the value of the |
| 295 | /// SpillSlotsAvailable entries. The predicate 'canClobberPhysReg()' checks |
| 296 | /// this bit and addAvailable sets it if. |
Chris Lattner | f8c68f6 | 2006-06-28 22:17:39 +0000 | [diff] [blame] | 297 | namespace { |
| 298 | class VISIBILITY_HIDDEN AvailableSpills { |
Chris Lattner | 66cf80f | 2006-02-03 23:13:58 +0000 | [diff] [blame] | 299 | const MRegisterInfo *MRI; |
| 300 | const TargetInstrInfo *TII; |
| 301 | |
Evan Cheng | 549f27d3 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 302 | // SpillSlotsOrReMatsAvailable - This map keeps track of all of the spilled |
| 303 | // or remat'ed virtual register values that are still available, due to being |
| 304 | // loaded or stored to, but not invalidated yet. |
| 305 | std::map<int, unsigned> SpillSlotsOrReMatsAvailable; |
Chris Lattner | 66cf80f | 2006-02-03 23:13:58 +0000 | [diff] [blame] | 306 | |
Evan Cheng | 549f27d3 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 307 | // PhysRegsAvailable - This is the inverse of SpillSlotsOrReMatsAvailable, |
| 308 | // indicating which stack slot values are currently held by a physreg. This |
| 309 | // is used to invalidate entries in SpillSlotsOrReMatsAvailable when a |
| 310 | // physreg is modified. |
Chris Lattner | 66cf80f | 2006-02-03 23:13:58 +0000 | [diff] [blame] | 311 | std::multimap<unsigned, int> PhysRegsAvailable; |
| 312 | |
Evan Cheng | 7a0d51c | 2006-12-14 07:54:05 +0000 | [diff] [blame] | 313 | void disallowClobberPhysRegOnly(unsigned PhysReg); |
| 314 | |
Chris Lattner | 66cf80f | 2006-02-03 23:13:58 +0000 | [diff] [blame] | 315 | void ClobberPhysRegOnly(unsigned PhysReg); |
| 316 | public: |
| 317 | AvailableSpills(const MRegisterInfo *mri, const TargetInstrInfo *tii) |
| 318 | : MRI(mri), TII(tii) { |
| 319 | } |
| 320 | |
Evan Cheng | 91e2390 | 2007-02-23 01:13:26 +0000 | [diff] [blame] | 321 | const MRegisterInfo *getRegInfo() const { return MRI; } |
| 322 | |
Evan Cheng | 549f27d3 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 323 | /// getSpillSlotOrReMatPhysReg - If the specified stack slot or remat is |
| 324 | /// available in a physical register, return that PhysReg, otherwise |
| 325 | /// return 0. |
| 326 | unsigned getSpillSlotOrReMatPhysReg(int Slot) const { |
| 327 | std::map<int, unsigned>::const_iterator I = |
| 328 | SpillSlotsOrReMatsAvailable.find(Slot); |
| 329 | if (I != SpillSlotsOrReMatsAvailable.end()) { |
Evan Cheng | b9591c6 | 2007-07-11 08:47:44 +0000 | [diff] [blame] | 330 | return I->second >> 1; // Remove the CanClobber bit. |
Evan Cheng | 91e2390 | 2007-02-23 01:13:26 +0000 | [diff] [blame] | 331 | } |
Chris Lattner | 66cf80f | 2006-02-03 23:13:58 +0000 | [diff] [blame] | 332 | return 0; |
| 333 | } |
Evan Cheng | de4e942 | 2007-02-25 09:51:27 +0000 | [diff] [blame] | 334 | |
Evan Cheng | 549f27d3 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 335 | /// addAvailable - Mark that the specified stack slot / remat is available in |
| 336 | /// the specified physreg. If CanClobber is true, the physreg can be modified |
| 337 | /// at any time without changing the semantics of the program. |
| 338 | void addAvailable(int SlotOrReMat, MachineInstr *MI, unsigned Reg, |
Evan Cheng | 91e2390 | 2007-02-23 01:13:26 +0000 | [diff] [blame] | 339 | bool CanClobber = true) { |
Chris Lattner | 8666249 | 2006-02-03 23:50:46 +0000 | [diff] [blame] | 340 | // If this stack slot is thought to be available in some other physreg, |
| 341 | // remove its record. |
Evan Cheng | 549f27d3 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 342 | ModifyStackSlotOrReMat(SlotOrReMat); |
Chris Lattner | 8666249 | 2006-02-03 23:50:46 +0000 | [diff] [blame] | 343 | |
Evan Cheng | 549f27d3 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 344 | PhysRegsAvailable.insert(std::make_pair(Reg, SlotOrReMat)); |
Evan Cheng | 90a43c3 | 2007-08-15 20:20:34 +0000 | [diff] [blame] | 345 | SpillSlotsOrReMatsAvailable[SlotOrReMat]= (Reg << 1) | (unsigned)CanClobber; |
Chris Lattner | 66cf80f | 2006-02-03 23:13:58 +0000 | [diff] [blame] | 346 | |
Evan Cheng | 549f27d3 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 347 | if (SlotOrReMat > VirtRegMap::MAX_STACK_SLOT) |
| 348 | DOUT << "Remembering RM#" << SlotOrReMat-VirtRegMap::MAX_STACK_SLOT-1; |
Evan Cheng | 2638e1a | 2007-03-20 08:13:50 +0000 | [diff] [blame] | 349 | else |
Evan Cheng | 549f27d3 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 350 | DOUT << "Remembering SS#" << SlotOrReMat; |
Evan Cheng | 2638e1a | 2007-03-20 08:13:50 +0000 | [diff] [blame] | 351 | DOUT << " in physreg " << MRI->getName(Reg) << "\n"; |
Chris Lattner | 66cf80f | 2006-02-03 23:13:58 +0000 | [diff] [blame] | 352 | } |
Evan Cheng | 7a0d51c | 2006-12-14 07:54:05 +0000 | [diff] [blame] | 353 | |
Chris Lattner | 593c958 | 2006-02-03 23:28:46 +0000 | [diff] [blame] | 354 | /// canClobberPhysReg - Return true if the spiller is allowed to change the |
| 355 | /// value of the specified stackslot register if it desires. The specified |
| 356 | /// stack slot must be available in a physreg for this query to make sense. |
Evan Cheng | 549f27d3 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 357 | bool canClobberPhysReg(int SlotOrReMat) const { |
Evan Cheng | 90a43c3 | 2007-08-15 20:20:34 +0000 | [diff] [blame] | 358 | assert(SpillSlotsOrReMatsAvailable.count(SlotOrReMat) && |
| 359 | "Value not available!"); |
Evan Cheng | 549f27d3 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 360 | return SpillSlotsOrReMatsAvailable.find(SlotOrReMat)->second & 1; |
Chris Lattner | 593c958 | 2006-02-03 23:28:46 +0000 | [diff] [blame] | 361 | } |
Evan Cheng | 35a3e4a | 2007-12-04 19:19:45 +0000 | [diff] [blame] | 362 | |
Evan Cheng | 7a0d51c | 2006-12-14 07:54:05 +0000 | [diff] [blame] | 363 | /// disallowClobberPhysReg - Unset the CanClobber bit of the specified |
| 364 | /// stackslot register. The register is still available but is no longer |
| 365 | /// allowed to be modifed. |
| 366 | void disallowClobberPhysReg(unsigned PhysReg); |
| 367 | |
Chris Lattner | 66cf80f | 2006-02-03 23:13:58 +0000 | [diff] [blame] | 368 | /// ClobberPhysReg - This is called when the specified physreg changes |
Evan Cheng | 66f7163 | 2007-10-19 21:23:22 +0000 | [diff] [blame] | 369 | /// value. We use this to invalidate any info about stuff that lives in |
Chris Lattner | 66cf80f | 2006-02-03 23:13:58 +0000 | [diff] [blame] | 370 | /// it and any of its aliases. |
| 371 | void ClobberPhysReg(unsigned PhysReg); |
| 372 | |
Evan Cheng | 90a43c3 | 2007-08-15 20:20:34 +0000 | [diff] [blame] | 373 | /// ModifyStackSlotOrReMat - This method is called when the value in a stack |
| 374 | /// slot changes. This removes information about which register the previous |
| 375 | /// value for this slot lives in (as the previous value is dead now). |
Evan Cheng | 549f27d3 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 376 | void ModifyStackSlotOrReMat(int SlotOrReMat); |
Chris Lattner | 66cf80f | 2006-02-03 23:13:58 +0000 | [diff] [blame] | 377 | }; |
Chris Lattner | f8c68f6 | 2006-06-28 22:17:39 +0000 | [diff] [blame] | 378 | } |
Chris Lattner | 66cf80f | 2006-02-03 23:13:58 +0000 | [diff] [blame] | 379 | |
Evan Cheng | 7a0d51c | 2006-12-14 07:54:05 +0000 | [diff] [blame] | 380 | /// disallowClobberPhysRegOnly - Unset the CanClobber bit of the specified |
| 381 | /// stackslot register. The register is still available but is no longer |
| 382 | /// allowed to be modifed. |
| 383 | void AvailableSpills::disallowClobberPhysRegOnly(unsigned PhysReg) { |
| 384 | std::multimap<unsigned, int>::iterator I = |
| 385 | PhysRegsAvailable.lower_bound(PhysReg); |
| 386 | while (I != PhysRegsAvailable.end() && I->first == PhysReg) { |
Evan Cheng | 549f27d3 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 387 | int SlotOrReMat = I->second; |
Evan Cheng | 7a0d51c | 2006-12-14 07:54:05 +0000 | [diff] [blame] | 388 | I++; |
Evan Cheng | 549f27d3 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 389 | assert((SpillSlotsOrReMatsAvailable[SlotOrReMat] >> 1) == PhysReg && |
Evan Cheng | 7a0d51c | 2006-12-14 07:54:05 +0000 | [diff] [blame] | 390 | "Bidirectional map mismatch!"); |
Evan Cheng | 549f27d3 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 391 | SpillSlotsOrReMatsAvailable[SlotOrReMat] &= ~1; |
Evan Cheng | 7a0d51c | 2006-12-14 07:54:05 +0000 | [diff] [blame] | 392 | DOUT << "PhysReg " << MRI->getName(PhysReg) |
| 393 | << " copied, it is available for use but can no longer be modified\n"; |
| 394 | } |
| 395 | } |
| 396 | |
| 397 | /// disallowClobberPhysReg - Unset the CanClobber bit of the specified |
| 398 | /// stackslot register and its aliases. The register and its aliases may |
| 399 | /// still available but is no longer allowed to be modifed. |
| 400 | void AvailableSpills::disallowClobberPhysReg(unsigned PhysReg) { |
| 401 | for (const unsigned *AS = MRI->getAliasSet(PhysReg); *AS; ++AS) |
| 402 | disallowClobberPhysRegOnly(*AS); |
| 403 | disallowClobberPhysRegOnly(PhysReg); |
| 404 | } |
| 405 | |
Chris Lattner | 66cf80f | 2006-02-03 23:13:58 +0000 | [diff] [blame] | 406 | /// ClobberPhysRegOnly - This is called when the specified physreg changes |
| 407 | /// value. We use this to invalidate any info about stuff we thing lives in it. |
| 408 | void AvailableSpills::ClobberPhysRegOnly(unsigned PhysReg) { |
| 409 | std::multimap<unsigned, int>::iterator I = |
| 410 | PhysRegsAvailable.lower_bound(PhysReg); |
Chris Lattner | 07cf141 | 2006-02-03 00:36:31 +0000 | [diff] [blame] | 411 | while (I != PhysRegsAvailable.end() && I->first == PhysReg) { |
Evan Cheng | 549f27d3 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 412 | int SlotOrReMat = I->second; |
Chris Lattner | 07cf141 | 2006-02-03 00:36:31 +0000 | [diff] [blame] | 413 | PhysRegsAvailable.erase(I++); |
Evan Cheng | 549f27d3 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 414 | assert((SpillSlotsOrReMatsAvailable[SlotOrReMat] >> 1) == PhysReg && |
Chris Lattner | 66cf80f | 2006-02-03 23:13:58 +0000 | [diff] [blame] | 415 | "Bidirectional map mismatch!"); |
Evan Cheng | 549f27d3 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 416 | SpillSlotsOrReMatsAvailable.erase(SlotOrReMat); |
Bill Wendling | b2b9c20 | 2006-11-17 02:09:07 +0000 | [diff] [blame] | 417 | DOUT << "PhysReg " << MRI->getName(PhysReg) |
Evan Cheng | 2638e1a | 2007-03-20 08:13:50 +0000 | [diff] [blame] | 418 | << " clobbered, invalidating "; |
Evan Cheng | 549f27d3 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 419 | if (SlotOrReMat > VirtRegMap::MAX_STACK_SLOT) |
| 420 | DOUT << "RM#" << SlotOrReMat-VirtRegMap::MAX_STACK_SLOT-1 << "\n"; |
Evan Cheng | 2638e1a | 2007-03-20 08:13:50 +0000 | [diff] [blame] | 421 | else |
Evan Cheng | 549f27d3 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 422 | DOUT << "SS#" << SlotOrReMat << "\n"; |
Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 423 | } |
Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 424 | } |
| 425 | |
Chris Lattner | 66cf80f | 2006-02-03 23:13:58 +0000 | [diff] [blame] | 426 | /// ClobberPhysReg - This is called when the specified physreg changes |
| 427 | /// value. We use this to invalidate any info about stuff we thing lives in |
| 428 | /// it and any of its aliases. |
| 429 | void AvailableSpills::ClobberPhysReg(unsigned PhysReg) { |
Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 430 | for (const unsigned *AS = MRI->getAliasSet(PhysReg); *AS; ++AS) |
Chris Lattner | 66cf80f | 2006-02-03 23:13:58 +0000 | [diff] [blame] | 431 | ClobberPhysRegOnly(*AS); |
| 432 | ClobberPhysRegOnly(PhysReg); |
Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 433 | } |
| 434 | |
Evan Cheng | 90a43c3 | 2007-08-15 20:20:34 +0000 | [diff] [blame] | 435 | /// ModifyStackSlotOrReMat - This method is called when the value in a stack |
| 436 | /// slot changes. This removes information about which register the previous |
| 437 | /// value for this slot lives in (as the previous value is dead now). |
Evan Cheng | 549f27d3 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 438 | void AvailableSpills::ModifyStackSlotOrReMat(int SlotOrReMat) { |
Evan Cheng | 90a43c3 | 2007-08-15 20:20:34 +0000 | [diff] [blame] | 439 | std::map<int, unsigned>::iterator It = |
| 440 | SpillSlotsOrReMatsAvailable.find(SlotOrReMat); |
Evan Cheng | 549f27d3 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 441 | if (It == SpillSlotsOrReMatsAvailable.end()) return; |
Evan Cheng | b9591c6 | 2007-07-11 08:47:44 +0000 | [diff] [blame] | 442 | unsigned Reg = It->second >> 1; |
Evan Cheng | 549f27d3 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 443 | SpillSlotsOrReMatsAvailable.erase(It); |
Chris Lattner | 07cf141 | 2006-02-03 00:36:31 +0000 | [diff] [blame] | 444 | |
| 445 | // This register may hold the value of multiple stack slots, only remove this |
| 446 | // stack slot from the set of values the register contains. |
| 447 | std::multimap<unsigned, int>::iterator I = PhysRegsAvailable.lower_bound(Reg); |
| 448 | for (; ; ++I) { |
| 449 | assert(I != PhysRegsAvailable.end() && I->first == Reg && |
| 450 | "Map inverse broken!"); |
Evan Cheng | 549f27d3 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 451 | if (I->second == SlotOrReMat) break; |
Chris Lattner | 07cf141 | 2006-02-03 00:36:31 +0000 | [diff] [blame] | 452 | } |
| 453 | PhysRegsAvailable.erase(I); |
| 454 | } |
| 455 | |
| 456 | |
Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 457 | |
Evan Cheng | 28bb462 | 2007-07-11 19:17:18 +0000 | [diff] [blame] | 458 | /// InvalidateKills - MI is going to be deleted. If any of its operands are |
| 459 | /// marked kill, then invalidate the information. |
| 460 | static void InvalidateKills(MachineInstr &MI, BitVector &RegKills, |
Evan Cheng | c91f0b8 | 2007-08-14 20:23:13 +0000 | [diff] [blame] | 461 | std::vector<MachineOperand*> &KillOps, |
Evan Cheng | 66f7163 | 2007-10-19 21:23:22 +0000 | [diff] [blame] | 462 | SmallVector<unsigned, 2> *KillRegs = NULL) { |
Evan Cheng | 28bb462 | 2007-07-11 19:17:18 +0000 | [diff] [blame] | 463 | for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) { |
| 464 | MachineOperand &MO = MI.getOperand(i); |
Dan Gohman | 92dfe20 | 2007-09-14 20:33:02 +0000 | [diff] [blame] | 465 | if (!MO.isRegister() || !MO.isUse() || !MO.isKill()) |
Evan Cheng | 28bb462 | 2007-07-11 19:17:18 +0000 | [diff] [blame] | 466 | continue; |
| 467 | unsigned Reg = MO.getReg(); |
Evan Cheng | b6ca4b3 | 2007-08-14 23:25:37 +0000 | [diff] [blame] | 468 | if (KillRegs) |
| 469 | KillRegs->push_back(Reg); |
Evan Cheng | 28bb462 | 2007-07-11 19:17:18 +0000 | [diff] [blame] | 470 | if (KillOps[Reg] == &MO) { |
| 471 | RegKills.reset(Reg); |
| 472 | KillOps[Reg] = NULL; |
| 473 | } |
| 474 | } |
| 475 | } |
| 476 | |
Evan Cheng | b6ca4b3 | 2007-08-14 23:25:37 +0000 | [diff] [blame] | 477 | /// InvalidateRegDef - If the def operand of the specified def MI is now dead |
| 478 | /// (since it's spill instruction is removed), mark it isDead. Also checks if |
| 479 | /// the def MI has other definition operands that are not dead. Returns it by |
| 480 | /// reference. |
| 481 | static bool InvalidateRegDef(MachineBasicBlock::iterator I, |
| 482 | MachineInstr &NewDef, unsigned Reg, |
| 483 | bool &HasLiveDef) { |
| 484 | // Due to remat, it's possible this reg isn't being reused. That is, |
| 485 | // the def of this reg (by prev MI) is now dead. |
| 486 | MachineInstr *DefMI = I; |
| 487 | MachineOperand *DefOp = NULL; |
| 488 | for (unsigned i = 0, e = DefMI->getNumOperands(); i != e; ++i) { |
| 489 | MachineOperand &MO = DefMI->getOperand(i); |
Dan Gohman | 92dfe20 | 2007-09-14 20:33:02 +0000 | [diff] [blame] | 490 | if (MO.isRegister() && MO.isDef()) { |
Evan Cheng | b6ca4b3 | 2007-08-14 23:25:37 +0000 | [diff] [blame] | 491 | if (MO.getReg() == Reg) |
| 492 | DefOp = &MO; |
| 493 | else if (!MO.isDead()) |
| 494 | HasLiveDef = true; |
| 495 | } |
| 496 | } |
| 497 | if (!DefOp) |
| 498 | return false; |
| 499 | |
| 500 | bool FoundUse = false, Done = false; |
| 501 | MachineBasicBlock::iterator E = NewDef; |
| 502 | ++I; ++E; |
| 503 | for (; !Done && I != E; ++I) { |
| 504 | MachineInstr *NMI = I; |
| 505 | for (unsigned j = 0, ee = NMI->getNumOperands(); j != ee; ++j) { |
| 506 | MachineOperand &MO = NMI->getOperand(j); |
Dan Gohman | 92dfe20 | 2007-09-14 20:33:02 +0000 | [diff] [blame] | 507 | if (!MO.isRegister() || MO.getReg() != Reg) |
Evan Cheng | b6ca4b3 | 2007-08-14 23:25:37 +0000 | [diff] [blame] | 508 | continue; |
| 509 | if (MO.isUse()) |
| 510 | FoundUse = true; |
| 511 | Done = true; // Stop after scanning all the operands of this MI. |
| 512 | } |
| 513 | } |
| 514 | if (!FoundUse) { |
| 515 | // Def is dead! |
| 516 | DefOp->setIsDead(); |
| 517 | return true; |
| 518 | } |
| 519 | return false; |
| 520 | } |
| 521 | |
Evan Cheng | 28bb462 | 2007-07-11 19:17:18 +0000 | [diff] [blame] | 522 | /// UpdateKills - Track and update kill info. If a MI reads a register that is |
| 523 | /// marked kill, then it must be due to register reuse. Transfer the kill info |
| 524 | /// over. |
| 525 | static void UpdateKills(MachineInstr &MI, BitVector &RegKills, |
| 526 | std::vector<MachineOperand*> &KillOps) { |
| 527 | const TargetInstrDescriptor *TID = MI.getInstrDescriptor(); |
| 528 | for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) { |
| 529 | MachineOperand &MO = MI.getOperand(i); |
Dan Gohman | 92dfe20 | 2007-09-14 20:33:02 +0000 | [diff] [blame] | 530 | if (!MO.isRegister() || !MO.isUse()) |
Evan Cheng | 28bb462 | 2007-07-11 19:17:18 +0000 | [diff] [blame] | 531 | continue; |
| 532 | unsigned Reg = MO.getReg(); |
| 533 | if (Reg == 0) |
| 534 | continue; |
| 535 | |
| 536 | if (RegKills[Reg]) { |
| 537 | // That can't be right. Register is killed but not re-defined and it's |
| 538 | // being reused. Let's fix that. |
| 539 | KillOps[Reg]->unsetIsKill(); |
| 540 | if (i < TID->numOperands && |
| 541 | TID->getOperandConstraint(i, TOI::TIED_TO) == -1) |
| 542 | // Unless it's a two-address operand, this is the new kill. |
| 543 | MO.setIsKill(); |
| 544 | } |
| 545 | |
| 546 | if (MO.isKill()) { |
| 547 | RegKills.set(Reg); |
| 548 | KillOps[Reg] = &MO; |
| 549 | } |
| 550 | } |
| 551 | |
| 552 | for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) { |
| 553 | const MachineOperand &MO = MI.getOperand(i); |
Dan Gohman | 92dfe20 | 2007-09-14 20:33:02 +0000 | [diff] [blame] | 554 | if (!MO.isRegister() || !MO.isDef()) |
Evan Cheng | 28bb462 | 2007-07-11 19:17:18 +0000 | [diff] [blame] | 555 | continue; |
| 556 | unsigned Reg = MO.getReg(); |
| 557 | RegKills.reset(Reg); |
| 558 | KillOps[Reg] = NULL; |
| 559 | } |
| 560 | } |
| 561 | |
| 562 | |
Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 563 | // ReusedOp - For each reused operand, we keep track of a bit of information, in |
| 564 | // case we need to rollback upon processing a new operand. See comments below. |
| 565 | namespace { |
| 566 | struct ReusedOp { |
| 567 | // The MachineInstr operand that reused an available value. |
| 568 | unsigned Operand; |
Misha Brukman | edf128a | 2005-04-21 22:36:52 +0000 | [diff] [blame] | 569 | |
Evan Cheng | 549f27d3 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 570 | // StackSlotOrReMat - The spill slot or remat id of the value being reused. |
| 571 | unsigned StackSlotOrReMat; |
Misha Brukman | edf128a | 2005-04-21 22:36:52 +0000 | [diff] [blame] | 572 | |
Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 573 | // PhysRegReused - The physical register the value was available in. |
| 574 | unsigned PhysRegReused; |
Misha Brukman | edf128a | 2005-04-21 22:36:52 +0000 | [diff] [blame] | 575 | |
Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 576 | // AssignedPhysReg - The physreg that was assigned for use by the reload. |
| 577 | unsigned AssignedPhysReg; |
Chris Lattner | 8a61a75 | 2005-10-06 17:19:06 +0000 | [diff] [blame] | 578 | |
| 579 | // VirtReg - The virtual register itself. |
| 580 | unsigned VirtReg; |
Misha Brukman | edf128a | 2005-04-21 22:36:52 +0000 | [diff] [blame] | 581 | |
Chris Lattner | 8a61a75 | 2005-10-06 17:19:06 +0000 | [diff] [blame] | 582 | ReusedOp(unsigned o, unsigned ss, unsigned prr, unsigned apr, |
| 583 | unsigned vreg) |
Evan Cheng | 90a43c3 | 2007-08-15 20:20:34 +0000 | [diff] [blame] | 584 | : Operand(o), StackSlotOrReMat(ss), PhysRegReused(prr), |
| 585 | AssignedPhysReg(apr), VirtReg(vreg) {} |
Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 586 | }; |
Chris Lattner | 540fec6 | 2006-02-25 01:51:33 +0000 | [diff] [blame] | 587 | |
| 588 | /// ReuseInfo - This maintains a collection of ReuseOp's for each operand that |
| 589 | /// is reused instead of reloaded. |
Chris Lattner | f8c68f6 | 2006-06-28 22:17:39 +0000 | [diff] [blame] | 590 | class VISIBILITY_HIDDEN ReuseInfo { |
Chris Lattner | 540fec6 | 2006-02-25 01:51:33 +0000 | [diff] [blame] | 591 | MachineInstr &MI; |
| 592 | std::vector<ReusedOp> Reuses; |
Evan Cheng | 957840b | 2007-02-21 02:22:03 +0000 | [diff] [blame] | 593 | BitVector PhysRegsClobbered; |
Chris Lattner | 540fec6 | 2006-02-25 01:51:33 +0000 | [diff] [blame] | 594 | public: |
Evan Cheng | e077ef6 | 2006-11-04 00:21:55 +0000 | [diff] [blame] | 595 | ReuseInfo(MachineInstr &mi, const MRegisterInfo *mri) : MI(mi) { |
Evan Cheng | 957840b | 2007-02-21 02:22:03 +0000 | [diff] [blame] | 596 | PhysRegsClobbered.resize(mri->getNumRegs()); |
Evan Cheng | e077ef6 | 2006-11-04 00:21:55 +0000 | [diff] [blame] | 597 | } |
Chris Lattner | 540fec6 | 2006-02-25 01:51:33 +0000 | [diff] [blame] | 598 | |
| 599 | bool hasReuses() const { |
| 600 | return !Reuses.empty(); |
| 601 | } |
| 602 | |
| 603 | /// addReuse - If we choose to reuse a virtual register that is already |
| 604 | /// available instead of reloading it, remember that we did so. |
Evan Cheng | 549f27d3 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 605 | void addReuse(unsigned OpNo, unsigned StackSlotOrReMat, |
Chris Lattner | 540fec6 | 2006-02-25 01:51:33 +0000 | [diff] [blame] | 606 | unsigned PhysRegReused, unsigned AssignedPhysReg, |
| 607 | unsigned VirtReg) { |
| 608 | // If the reload is to the assigned register anyway, no undo will be |
| 609 | // required. |
| 610 | if (PhysRegReused == AssignedPhysReg) return; |
| 611 | |
| 612 | // Otherwise, remember this. |
Evan Cheng | 549f27d3 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 613 | Reuses.push_back(ReusedOp(OpNo, StackSlotOrReMat, PhysRegReused, |
Chris Lattner | 540fec6 | 2006-02-25 01:51:33 +0000 | [diff] [blame] | 614 | AssignedPhysReg, VirtReg)); |
| 615 | } |
Evan Cheng | e077ef6 | 2006-11-04 00:21:55 +0000 | [diff] [blame] | 616 | |
| 617 | void markClobbered(unsigned PhysReg) { |
Evan Cheng | 957840b | 2007-02-21 02:22:03 +0000 | [diff] [blame] | 618 | PhysRegsClobbered.set(PhysReg); |
Evan Cheng | e077ef6 | 2006-11-04 00:21:55 +0000 | [diff] [blame] | 619 | } |
| 620 | |
| 621 | bool isClobbered(unsigned PhysReg) const { |
Evan Cheng | 957840b | 2007-02-21 02:22:03 +0000 | [diff] [blame] | 622 | return PhysRegsClobbered.test(PhysReg); |
Evan Cheng | e077ef6 | 2006-11-04 00:21:55 +0000 | [diff] [blame] | 623 | } |
Chris Lattner | 540fec6 | 2006-02-25 01:51:33 +0000 | [diff] [blame] | 624 | |
| 625 | /// GetRegForReload - We are about to emit a reload into PhysReg. If there |
| 626 | /// is some other operand that is using the specified register, either pick |
| 627 | /// a new register to use, or evict the previous reload and use this reg. |
| 628 | unsigned GetRegForReload(unsigned PhysReg, MachineInstr *MI, |
| 629 | AvailableSpills &Spills, |
Evan Cheng | fff3e19 | 2007-08-14 09:11:18 +0000 | [diff] [blame] | 630 | std::vector<MachineInstr*> &MaybeDeadStores, |
Evan Cheng | 28bb462 | 2007-07-11 19:17:18 +0000 | [diff] [blame] | 631 | SmallSet<unsigned, 8> &Rejected, |
| 632 | BitVector &RegKills, |
Evan Cheng | 549f27d3 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 633 | std::vector<MachineOperand*> &KillOps, |
| 634 | VirtRegMap &VRM) { |
Chris Lattner | 540fec6 | 2006-02-25 01:51:33 +0000 | [diff] [blame] | 635 | if (Reuses.empty()) return PhysReg; // This is most often empty. |
| 636 | |
| 637 | for (unsigned ro = 0, e = Reuses.size(); ro != e; ++ro) { |
| 638 | ReusedOp &Op = Reuses[ro]; |
| 639 | // If we find some other reuse that was supposed to use this register |
| 640 | // exactly for its reload, we can change this reload to use ITS reload |
Evan Cheng | 3c82cab | 2007-01-19 22:40:14 +0000 | [diff] [blame] | 641 | // register. That is, unless its reload register has already been |
| 642 | // considered and subsequently rejected because it has also been reused |
| 643 | // by another operand. |
| 644 | if (Op.PhysRegReused == PhysReg && |
| 645 | Rejected.count(Op.AssignedPhysReg) == 0) { |
Chris Lattner | 540fec6 | 2006-02-25 01:51:33 +0000 | [diff] [blame] | 646 | // Yup, use the reload register that we didn't use before. |
Evan Cheng | 3c82cab | 2007-01-19 22:40:14 +0000 | [diff] [blame] | 647 | unsigned NewReg = Op.AssignedPhysReg; |
| 648 | Rejected.insert(PhysReg); |
Evan Cheng | 28bb462 | 2007-07-11 19:17:18 +0000 | [diff] [blame] | 649 | return GetRegForReload(NewReg, MI, Spills, MaybeDeadStores, Rejected, |
Evan Cheng | 549f27d3 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 650 | RegKills, KillOps, VRM); |
Chris Lattner | 540fec6 | 2006-02-25 01:51:33 +0000 | [diff] [blame] | 651 | } else { |
| 652 | // Otherwise, we might also have a problem if a previously reused |
| 653 | // value aliases the new register. If so, codegen the previous reload |
| 654 | // and use this one. |
| 655 | unsigned PRRU = Op.PhysRegReused; |
| 656 | const MRegisterInfo *MRI = Spills.getRegInfo(); |
| 657 | if (MRI->areAliases(PRRU, PhysReg)) { |
| 658 | // Okay, we found out that an alias of a reused register |
| 659 | // was used. This isn't good because it means we have |
| 660 | // to undo a previous reuse. |
| 661 | MachineBasicBlock *MBB = MI->getParent(); |
| 662 | const TargetRegisterClass *AliasRC = |
Chris Lattner | 28bad08 | 2006-02-25 02:17:31 +0000 | [diff] [blame] | 663 | MBB->getParent()->getSSARegMap()->getRegClass(Op.VirtReg); |
| 664 | |
| 665 | // Copy Op out of the vector and remove it, we're going to insert an |
| 666 | // explicit load for it. |
| 667 | ReusedOp NewOp = Op; |
| 668 | Reuses.erase(Reuses.begin()+ro); |
| 669 | |
| 670 | // Ok, we're going to try to reload the assigned physreg into the |
| 671 | // slot that we were supposed to in the first place. However, that |
| 672 | // register could hold a reuse. Check to see if it conflicts or |
| 673 | // would prefer us to use a different register. |
| 674 | unsigned NewPhysReg = GetRegForReload(NewOp.AssignedPhysReg, |
Evan Cheng | 28bb462 | 2007-07-11 19:17:18 +0000 | [diff] [blame] | 675 | MI, Spills, MaybeDeadStores, |
Evan Cheng | 549f27d3 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 676 | Rejected, RegKills, KillOps, VRM); |
Chris Lattner | 28bad08 | 2006-02-25 02:17:31 +0000 | [diff] [blame] | 677 | |
Evan Cheng | 549f27d3 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 678 | if (NewOp.StackSlotOrReMat > VirtRegMap::MAX_STACK_SLOT) { |
| 679 | MRI->reMaterialize(*MBB, MI, NewPhysReg, |
| 680 | VRM.getReMaterializedMI(NewOp.VirtReg)); |
| 681 | ++NumReMats; |
| 682 | } else { |
| 683 | MRI->loadRegFromStackSlot(*MBB, MI, NewPhysReg, |
| 684 | NewOp.StackSlotOrReMat, AliasRC); |
Evan Cheng | fff3e19 | 2007-08-14 09:11:18 +0000 | [diff] [blame] | 685 | // Any stores to this stack slot are not dead anymore. |
| 686 | MaybeDeadStores[NewOp.StackSlotOrReMat] = NULL; |
Evan Cheng | 549f27d3 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 687 | ++NumLoads; |
| 688 | } |
Chris Lattner | 28bad08 | 2006-02-25 02:17:31 +0000 | [diff] [blame] | 689 | Spills.ClobberPhysReg(NewPhysReg); |
| 690 | Spills.ClobberPhysReg(NewOp.PhysRegReused); |
Chris Lattner | 540fec6 | 2006-02-25 01:51:33 +0000 | [diff] [blame] | 691 | |
Chris Lattner | e53f4a0 | 2006-05-04 17:52:23 +0000 | [diff] [blame] | 692 | MI->getOperand(NewOp.Operand).setReg(NewPhysReg); |
Chris Lattner | 540fec6 | 2006-02-25 01:51:33 +0000 | [diff] [blame] | 693 | |
Evan Cheng | 549f27d3 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 694 | Spills.addAvailable(NewOp.StackSlotOrReMat, MI, NewPhysReg); |
Evan Cheng | 28bb462 | 2007-07-11 19:17:18 +0000 | [diff] [blame] | 695 | MachineBasicBlock::iterator MII = MI; |
| 696 | --MII; |
| 697 | UpdateKills(*MII, RegKills, KillOps); |
| 698 | DOUT << '\t' << *MII; |
Chris Lattner | 540fec6 | 2006-02-25 01:51:33 +0000 | [diff] [blame] | 699 | |
Bill Wendling | b2b9c20 | 2006-11-17 02:09:07 +0000 | [diff] [blame] | 700 | DOUT << "Reuse undone!\n"; |
Chris Lattner | 540fec6 | 2006-02-25 01:51:33 +0000 | [diff] [blame] | 701 | --NumReused; |
Chris Lattner | 28bad08 | 2006-02-25 02:17:31 +0000 | [diff] [blame] | 702 | |
| 703 | // Finally, PhysReg is now available, go ahead and use it. |
Chris Lattner | 540fec6 | 2006-02-25 01:51:33 +0000 | [diff] [blame] | 704 | return PhysReg; |
| 705 | } |
| 706 | } |
| 707 | } |
| 708 | return PhysReg; |
| 709 | } |
Evan Cheng | 3c82cab | 2007-01-19 22:40:14 +0000 | [diff] [blame] | 710 | |
| 711 | /// GetRegForReload - Helper for the above GetRegForReload(). Add a |
| 712 | /// 'Rejected' set to remember which registers have been considered and |
| 713 | /// rejected for the reload. This avoids infinite looping in case like |
| 714 | /// this: |
| 715 | /// t1 := op t2, t3 |
| 716 | /// t2 <- assigned r0 for use by the reload but ended up reuse r1 |
| 717 | /// t3 <- assigned r1 for use by the reload but ended up reuse r0 |
| 718 | /// t1 <- desires r1 |
| 719 | /// sees r1 is taken by t2, tries t2's reload register r0 |
| 720 | /// sees r0 is taken by t3, tries t3's reload register r1 |
| 721 | /// sees r1 is taken by t2, tries t2's reload register r0 ... |
| 722 | unsigned GetRegForReload(unsigned PhysReg, MachineInstr *MI, |
| 723 | AvailableSpills &Spills, |
Evan Cheng | fff3e19 | 2007-08-14 09:11:18 +0000 | [diff] [blame] | 724 | std::vector<MachineInstr*> &MaybeDeadStores, |
Evan Cheng | 28bb462 | 2007-07-11 19:17:18 +0000 | [diff] [blame] | 725 | BitVector &RegKills, |
Evan Cheng | 549f27d3 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 726 | std::vector<MachineOperand*> &KillOps, |
| 727 | VirtRegMap &VRM) { |
Chris Lattner | 08a4d5a | 2007-01-23 00:59:48 +0000 | [diff] [blame] | 728 | SmallSet<unsigned, 8> Rejected; |
Evan Cheng | 28bb462 | 2007-07-11 19:17:18 +0000 | [diff] [blame] | 729 | return GetRegForReload(PhysReg, MI, Spills, MaybeDeadStores, Rejected, |
Evan Cheng | 549f27d3 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 730 | RegKills, KillOps, VRM); |
Evan Cheng | 3c82cab | 2007-01-19 22:40:14 +0000 | [diff] [blame] | 731 | } |
Chris Lattner | 540fec6 | 2006-02-25 01:51:33 +0000 | [diff] [blame] | 732 | }; |
Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 733 | } |
Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 734 | |
Evan Cheng | 66f7163 | 2007-10-19 21:23:22 +0000 | [diff] [blame] | 735 | /// PrepForUnfoldOpti - Turn a store folding instruction into a load folding |
| 736 | /// instruction. e.g. |
| 737 | /// xorl %edi, %eax |
| 738 | /// movl %eax, -32(%ebp) |
| 739 | /// movl -36(%ebp), %eax |
| 740 | /// orl %eax, -32(%ebp) |
| 741 | /// ==> |
| 742 | /// xorl %edi, %eax |
| 743 | /// orl -36(%ebp), %eax |
| 744 | /// mov %eax, -32(%ebp) |
| 745 | /// This enables unfolding optimization for a subsequent instruction which will |
| 746 | /// also eliminate the newly introduced store instruction. |
| 747 | bool LocalSpiller::PrepForUnfoldOpti(MachineBasicBlock &MBB, |
| 748 | MachineBasicBlock::iterator &MII, |
| 749 | std::vector<MachineInstr*> &MaybeDeadStores, |
| 750 | AvailableSpills &Spills, |
| 751 | BitVector &RegKills, |
| 752 | std::vector<MachineOperand*> &KillOps, |
| 753 | VirtRegMap &VRM) { |
| 754 | MachineFunction &MF = *MBB.getParent(); |
| 755 | MachineInstr &MI = *MII; |
| 756 | unsigned UnfoldedOpc = 0; |
| 757 | unsigned UnfoldPR = 0; |
| 758 | unsigned UnfoldVR = 0; |
| 759 | int FoldedSS = VirtRegMap::NO_STACK_SLOT; |
| 760 | VirtRegMap::MI2VirtMapTy::const_iterator I, End; |
| 761 | for (tie(I, End) = VRM.getFoldedVirts(&MI); I != End; ++I) { |
| 762 | // Only transform a MI that folds a single register. |
| 763 | if (UnfoldedOpc) |
| 764 | return false; |
| 765 | UnfoldVR = I->second.first; |
| 766 | VirtRegMap::ModRef MR = I->second.second; |
| 767 | if (VRM.isAssignedReg(UnfoldVR)) |
| 768 | continue; |
| 769 | // If this reference is not a use, any previous store is now dead. |
| 770 | // Otherwise, the store to this stack slot is not dead anymore. |
| 771 | FoldedSS = VRM.getStackSlot(UnfoldVR); |
| 772 | MachineInstr* DeadStore = MaybeDeadStores[FoldedSS]; |
| 773 | if (DeadStore && (MR & VirtRegMap::isModRef)) { |
| 774 | unsigned PhysReg = Spills.getSpillSlotOrReMatPhysReg(FoldedSS); |
| 775 | if (!PhysReg || |
| 776 | DeadStore->findRegisterUseOperandIdx(PhysReg, true) == -1) |
| 777 | continue; |
| 778 | UnfoldPR = PhysReg; |
| 779 | UnfoldedOpc = MRI->getOpcodeAfterMemoryUnfold(MI.getOpcode(), |
| 780 | false, true); |
| 781 | } |
| 782 | } |
| 783 | |
| 784 | if (!UnfoldedOpc) |
| 785 | return false; |
| 786 | |
| 787 | for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) { |
| 788 | MachineOperand &MO = MI.getOperand(i); |
| 789 | if (!MO.isRegister() || MO.getReg() == 0 || !MO.isUse()) |
| 790 | continue; |
| 791 | unsigned VirtReg = MO.getReg(); |
Evan Cheng | c498b02 | 2007-11-14 07:59:08 +0000 | [diff] [blame] | 792 | if (MRegisterInfo::isPhysicalRegister(VirtReg) || MO.getSubReg()) |
Evan Cheng | 66f7163 | 2007-10-19 21:23:22 +0000 | [diff] [blame] | 793 | continue; |
| 794 | if (VRM.isAssignedReg(VirtReg)) { |
| 795 | unsigned PhysReg = VRM.getPhys(VirtReg); |
| 796 | if (PhysReg && MRI->regsOverlap(PhysReg, UnfoldPR)) |
| 797 | return false; |
| 798 | } else if (VRM.isReMaterialized(VirtReg)) |
| 799 | continue; |
| 800 | int SS = VRM.getStackSlot(VirtReg); |
| 801 | unsigned PhysReg = Spills.getSpillSlotOrReMatPhysReg(SS); |
| 802 | if (PhysReg) { |
| 803 | if (MRI->regsOverlap(PhysReg, UnfoldPR)) |
| 804 | return false; |
| 805 | continue; |
| 806 | } |
| 807 | PhysReg = VRM.getPhys(VirtReg); |
| 808 | if (!MRI->regsOverlap(PhysReg, UnfoldPR)) |
| 809 | continue; |
| 810 | |
| 811 | // Ok, we'll need to reload the value into a register which makes |
| 812 | // it impossible to perform the store unfolding optimization later. |
| 813 | // Let's see if it is possible to fold the load if the store is |
| 814 | // unfolded. This allows us to perform the store unfolding |
| 815 | // optimization. |
| 816 | SmallVector<MachineInstr*, 4> NewMIs; |
| 817 | if (MRI->unfoldMemoryOperand(MF, &MI, UnfoldVR, false, false, NewMIs)) { |
| 818 | assert(NewMIs.size() == 1); |
| 819 | MachineInstr *NewMI = NewMIs.back(); |
| 820 | NewMIs.clear(); |
Evan Cheng | 81a0382 | 2007-11-17 00:40:40 +0000 | [diff] [blame] | 821 | int Idx = NewMI->findRegisterUseOperandIdx(VirtReg); |
| 822 | assert(Idx != -1); |
Evan Cheng | aee4af6 | 2007-12-02 08:30:39 +0000 | [diff] [blame] | 823 | SmallVector<unsigned, 2> Ops; |
| 824 | Ops.push_back(Idx); |
| 825 | MachineInstr *FoldedMI = MRI->foldMemoryOperand(NewMI, Ops, SS); |
Evan Cheng | 66f7163 | 2007-10-19 21:23:22 +0000 | [diff] [blame] | 826 | if (FoldedMI) { |
Evan Cheng | cbfb9b2 | 2007-10-22 03:01:44 +0000 | [diff] [blame] | 827 | if (!VRM.hasPhys(UnfoldVR)) |
Evan Cheng | 66f7163 | 2007-10-19 21:23:22 +0000 | [diff] [blame] | 828 | VRM.assignVirt2Phys(UnfoldVR, UnfoldPR); |
Evan Cheng | 66f7163 | 2007-10-19 21:23:22 +0000 | [diff] [blame] | 829 | VRM.virtFolded(VirtReg, FoldedMI, VirtRegMap::isRef); |
| 830 | MII = MBB.insert(MII, FoldedMI); |
Evan Cheng | cada245 | 2007-11-28 01:28:46 +0000 | [diff] [blame] | 831 | VRM.RemoveMachineInstrFromMaps(&MI); |
Evan Cheng | 66f7163 | 2007-10-19 21:23:22 +0000 | [diff] [blame] | 832 | MBB.erase(&MI); |
| 833 | return true; |
| 834 | } |
| 835 | delete NewMI; |
| 836 | } |
| 837 | } |
| 838 | return false; |
| 839 | } |
Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 840 | |
Evan Cheng | 7277a7d | 2007-11-02 17:35:08 +0000 | [diff] [blame] | 841 | /// findSuperReg - Find the SubReg's super-register of given register class |
| 842 | /// where its SubIdx sub-register is SubReg. |
| 843 | static unsigned findSuperReg(const TargetRegisterClass *RC, unsigned SubReg, |
| 844 | unsigned SubIdx, const MRegisterInfo *MRI) { |
| 845 | for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end(); |
| 846 | I != E; ++I) { |
| 847 | unsigned Reg = *I; |
| 848 | if (MRI->getSubReg(Reg, SubIdx) == SubReg) |
| 849 | return Reg; |
| 850 | } |
| 851 | return 0; |
| 852 | } |
| 853 | |
Evan Cheng | 81a0382 | 2007-11-17 00:40:40 +0000 | [diff] [blame] | 854 | /// SpillRegToStackSlot - Spill a register to a specified stack slot. Check if |
| 855 | /// the last store to the same slot is now dead. If so, remove the last store. |
| 856 | void LocalSpiller::SpillRegToStackSlot(MachineBasicBlock &MBB, |
| 857 | MachineBasicBlock::iterator &MII, |
| 858 | int Idx, unsigned PhysReg, int StackSlot, |
| 859 | const TargetRegisterClass *RC, |
Evan Cheng | 35a3e4a | 2007-12-04 19:19:45 +0000 | [diff] [blame] | 860 | bool isAvailable, MachineInstr *&LastStore, |
Evan Cheng | 81a0382 | 2007-11-17 00:40:40 +0000 | [diff] [blame] | 861 | AvailableSpills &Spills, |
| 862 | SmallSet<MachineInstr*, 4> &ReMatDefs, |
| 863 | BitVector &RegKills, |
| 864 | std::vector<MachineOperand*> &KillOps, |
Evan Cheng | e4b3900 | 2007-12-03 21:31:55 +0000 | [diff] [blame] | 865 | VirtRegMap &VRM) { |
Evan Cheng | d64b5c8 | 2007-12-05 03:14:33 +0000 | [diff] [blame] | 866 | MRI->storeRegToStackSlot(MBB, next(MII), PhysReg, true, StackSlot, RC); |
Evan Cheng | 81a0382 | 2007-11-17 00:40:40 +0000 | [diff] [blame] | 867 | DOUT << "Store:\t" << *next(MII); |
| 868 | |
| 869 | // If there is a dead store to this stack slot, nuke it now. |
| 870 | if (LastStore) { |
| 871 | DOUT << "Removed dead store:\t" << *LastStore; |
| 872 | ++NumDSE; |
| 873 | SmallVector<unsigned, 2> KillRegs; |
| 874 | InvalidateKills(*LastStore, RegKills, KillOps, &KillRegs); |
| 875 | MachineBasicBlock::iterator PrevMII = LastStore; |
| 876 | bool CheckDef = PrevMII != MBB.begin(); |
| 877 | if (CheckDef) |
| 878 | --PrevMII; |
| 879 | MBB.erase(LastStore); |
Evan Cheng | cada245 | 2007-11-28 01:28:46 +0000 | [diff] [blame] | 880 | VRM.RemoveMachineInstrFromMaps(LastStore); |
Evan Cheng | 81a0382 | 2007-11-17 00:40:40 +0000 | [diff] [blame] | 881 | if (CheckDef) { |
| 882 | // Look at defs of killed registers on the store. Mark the defs |
| 883 | // as dead since the store has been deleted and they aren't |
| 884 | // being reused. |
| 885 | for (unsigned j = 0, ee = KillRegs.size(); j != ee; ++j) { |
| 886 | bool HasOtherDef = false; |
| 887 | if (InvalidateRegDef(PrevMII, *MII, KillRegs[j], HasOtherDef)) { |
| 888 | MachineInstr *DeadDef = PrevMII; |
| 889 | if (ReMatDefs.count(DeadDef) && !HasOtherDef) { |
| 890 | // FIXME: This assumes a remat def does not have side |
| 891 | // effects. |
| 892 | MBB.erase(DeadDef); |
Evan Cheng | cada245 | 2007-11-28 01:28:46 +0000 | [diff] [blame] | 893 | VRM.RemoveMachineInstrFromMaps(DeadDef); |
Evan Cheng | 81a0382 | 2007-11-17 00:40:40 +0000 | [diff] [blame] | 894 | ++NumDRM; |
| 895 | } |
| 896 | } |
| 897 | } |
| 898 | } |
| 899 | } |
| 900 | |
Evan Cheng | e4b3900 | 2007-12-03 21:31:55 +0000 | [diff] [blame] | 901 | LastStore = next(MII); |
Evan Cheng | 81a0382 | 2007-11-17 00:40:40 +0000 | [diff] [blame] | 902 | |
| 903 | // If the stack slot value was previously available in some other |
| 904 | // register, change it now. Otherwise, make the register available, |
| 905 | // in PhysReg. |
| 906 | Spills.ModifyStackSlotOrReMat(StackSlot); |
| 907 | Spills.ClobberPhysReg(PhysReg); |
Evan Cheng | 35a3e4a | 2007-12-04 19:19:45 +0000 | [diff] [blame] | 908 | Spills.addAvailable(StackSlot, LastStore, PhysReg, isAvailable); |
Evan Cheng | 81a0382 | 2007-11-17 00:40:40 +0000 | [diff] [blame] | 909 | ++NumStores; |
| 910 | } |
| 911 | |
Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 912 | /// rewriteMBB - Keep track of which spills are available even after the |
Evan Cheng | 81a0382 | 2007-11-17 00:40:40 +0000 | [diff] [blame] | 913 | /// register allocator is done with them. If possible, avid reloading vregs. |
Evan Cheng | 549f27d3 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 914 | void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) { |
Bill Wendling | b2b9c20 | 2006-11-17 02:09:07 +0000 | [diff] [blame] | 915 | DOUT << MBB.getBasicBlock()->getName() << ":\n"; |
Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 916 | |
Evan Cheng | fff3e19 | 2007-08-14 09:11:18 +0000 | [diff] [blame] | 917 | MachineFunction &MF = *MBB.getParent(); |
| 918 | |
Chris Lattner | 66cf80f | 2006-02-03 23:13:58 +0000 | [diff] [blame] | 919 | // Spills - Keep track of which spilled values are available in physregs so |
| 920 | // that we can choose to reuse the physregs instead of emitting reloads. |
| 921 | AvailableSpills Spills(MRI, TII); |
| 922 | |
Chris Lattner | 52b25db | 2004-10-01 19:47:12 +0000 | [diff] [blame] | 923 | // MaybeDeadStores - When we need to write a value back into a stack slot, |
| 924 | // keep track of the inserted store. If the stack slot value is never read |
| 925 | // (because the value was used from some available register, for example), and |
| 926 | // subsequently stored to, the original store is dead. This map keeps track |
| 927 | // of inserted stores that are not used. If we see a subsequent store to the |
| 928 | // same stack slot, the original store is deleted. |
Evan Cheng | fff3e19 | 2007-08-14 09:11:18 +0000 | [diff] [blame] | 929 | std::vector<MachineInstr*> MaybeDeadStores; |
| 930 | MaybeDeadStores.resize(MF.getFrameInfo()->getObjectIndexEnd(), NULL); |
Chris Lattner | 52b25db | 2004-10-01 19:47:12 +0000 | [diff] [blame] | 931 | |
Evan Cheng | b6ca4b3 | 2007-08-14 23:25:37 +0000 | [diff] [blame] | 932 | // ReMatDefs - These are rematerializable def MIs which are not deleted. |
| 933 | SmallSet<MachineInstr*, 4> ReMatDefs; |
| 934 | |
Evan Cheng | 0c40d72 | 2007-07-11 05:28:39 +0000 | [diff] [blame] | 935 | // Keep track of kill information. |
| 936 | BitVector RegKills(MRI->getNumRegs()); |
| 937 | std::vector<MachineOperand*> KillOps; |
| 938 | KillOps.resize(MRI->getNumRegs(), NULL); |
| 939 | |
Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 940 | for (MachineBasicBlock::iterator MII = MBB.begin(), E = MBB.end(); |
| 941 | MII != E; ) { |
Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 942 | MachineBasicBlock::iterator NextMII = MII; ++NextMII; |
Evan Cheng | 0c40d72 | 2007-07-11 05:28:39 +0000 | [diff] [blame] | 943 | |
Evan Cheng | 66f7163 | 2007-10-19 21:23:22 +0000 | [diff] [blame] | 944 | VirtRegMap::MI2VirtMapTy::const_iterator I, End; |
Evan Cheng | 0c40d72 | 2007-07-11 05:28:39 +0000 | [diff] [blame] | 945 | bool Erased = false; |
| 946 | bool BackTracked = false; |
Evan Cheng | 66f7163 | 2007-10-19 21:23:22 +0000 | [diff] [blame] | 947 | if (PrepForUnfoldOpti(MBB, MII, |
| 948 | MaybeDeadStores, Spills, RegKills, KillOps, VRM)) |
| 949 | NextMII = next(MII); |
Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 950 | |
Evan Cheng | 66f7163 | 2007-10-19 21:23:22 +0000 | [diff] [blame] | 951 | MachineInstr &MI = *MII; |
Evan Cheng | 86facc2 | 2006-12-15 06:41:01 +0000 | [diff] [blame] | 952 | const TargetInstrDescriptor *TID = MI.getInstrDescriptor(); |
Evan Cheng | e077ef6 | 2006-11-04 00:21:55 +0000 | [diff] [blame] | 953 | |
Evan Cheng | 0cbb116 | 2007-11-29 01:06:25 +0000 | [diff] [blame] | 954 | // Insert restores here if asked to. |
| 955 | if (VRM.isRestorePt(&MI)) { |
| 956 | std::vector<unsigned> &RestoreRegs = VRM.getRestorePtRestores(&MI); |
| 957 | for (unsigned i = 0, e = RestoreRegs.size(); i != e; ++i) { |
| 958 | unsigned VirtReg = RestoreRegs[i]; |
| 959 | if (!VRM.getPreSplitReg(VirtReg)) |
| 960 | continue; // Split interval spilled again. |
| 961 | unsigned Phys = VRM.getPhys(VirtReg); |
| 962 | MF.setPhysRegUsed(Phys); |
| 963 | if (VRM.isReMaterialized(VirtReg)) { |
| 964 | MRI->reMaterialize(MBB, &MI, Phys, |
| 965 | VRM.getReMaterializedMI(VirtReg)); |
| 966 | ++NumReMats; |
| 967 | } else { |
| 968 | const TargetRegisterClass* RC = RegMap->getRegClass(VirtReg); |
| 969 | MRI->loadRegFromStackSlot(MBB, &MI, Phys, VRM.getStackSlot(VirtReg), RC); |
| 970 | ++NumLoads; |
| 971 | } |
| 972 | // This invalidates Phys. |
| 973 | Spills.ClobberPhysReg(Phys); |
| 974 | UpdateKills(*prior(MII), RegKills, KillOps); |
| 975 | DOUT << '\t' << *prior(MII); |
| 976 | } |
| 977 | } |
| 978 | |
Evan Cheng | 81a0382 | 2007-11-17 00:40:40 +0000 | [diff] [blame] | 979 | // Insert spills here if asked to. |
Evan Cheng | cada245 | 2007-11-28 01:28:46 +0000 | [diff] [blame] | 980 | if (VRM.isSpillPt(&MI)) { |
Evan Cheng | b50bb8c | 2007-12-05 08:16:32 +0000 | [diff] [blame] | 981 | std::vector<std::pair<unsigned,bool> > &SpillRegs = |
| 982 | VRM.getSpillPtSpills(&MI); |
Evan Cheng | cada245 | 2007-11-28 01:28:46 +0000 | [diff] [blame] | 983 | for (unsigned i = 0, e = SpillRegs.size(); i != e; ++i) { |
Evan Cheng | b50bb8c | 2007-12-05 08:16:32 +0000 | [diff] [blame] | 984 | unsigned VirtReg = SpillRegs[i].first; |
| 985 | bool isKill = SpillRegs[i].second; |
Evan Cheng | cada245 | 2007-11-28 01:28:46 +0000 | [diff] [blame] | 986 | if (!VRM.getPreSplitReg(VirtReg)) |
| 987 | continue; // Split interval spilled again. |
| 988 | const TargetRegisterClass *RC = RegMap->getRegClass(VirtReg); |
| 989 | unsigned Phys = VRM.getPhys(VirtReg); |
| 990 | int StackSlot = VRM.getStackSlot(VirtReg); |
Evan Cheng | b50bb8c | 2007-12-05 08:16:32 +0000 | [diff] [blame] | 991 | MRI->storeRegToStackSlot(MBB, next(MII), Phys, isKill, StackSlot, RC); |
Evan Cheng | d64b5c8 | 2007-12-05 03:14:33 +0000 | [diff] [blame] | 992 | MachineInstr *StoreMI = next(MII); |
| 993 | DOUT << "Store:\t" << StoreMI; |
| 994 | VRM.virtFolded(VirtReg, StoreMI, VirtRegMap::isMod); |
Evan Cheng | cada245 | 2007-11-28 01:28:46 +0000 | [diff] [blame] | 995 | } |
Evan Cheng | e4b3900 | 2007-12-03 21:31:55 +0000 | [diff] [blame] | 996 | NextMII = next(MII); |
Evan Cheng | 81a0382 | 2007-11-17 00:40:40 +0000 | [diff] [blame] | 997 | } |
| 998 | |
| 999 | /// ReusedOperands - Keep track of operand reuse in case we need to undo |
| 1000 | /// reuse. |
| 1001 | ReuseInfo ReusedOperands(MI, MRI); |
Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 1002 | // Process all of the spilled uses and all non spilled reg references. |
| 1003 | for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) { |
| 1004 | MachineOperand &MO = MI.getOperand(i); |
Chris Lattner | 50ea01e | 2005-09-09 20:29:51 +0000 | [diff] [blame] | 1005 | if (!MO.isRegister() || MO.getReg() == 0) |
| 1006 | continue; // Ignore non-register operands. |
| 1007 | |
Evan Cheng | 32dfbea | 2007-10-12 08:50:34 +0000 | [diff] [blame] | 1008 | unsigned VirtReg = MO.getReg(); |
| 1009 | if (MRegisterInfo::isPhysicalRegister(VirtReg)) { |
Chris Lattner | 50ea01e | 2005-09-09 20:29:51 +0000 | [diff] [blame] | 1010 | // Ignore physregs for spilling, but remember that it is used by this |
| 1011 | // function. |
Evan Cheng | 32dfbea | 2007-10-12 08:50:34 +0000 | [diff] [blame] | 1012 | MF.setPhysRegUsed(VirtReg); |
Chris Lattner | 50ea01e | 2005-09-09 20:29:51 +0000 | [diff] [blame] | 1013 | continue; |
| 1014 | } |
| 1015 | |
Evan Cheng | 32dfbea | 2007-10-12 08:50:34 +0000 | [diff] [blame] | 1016 | assert(MRegisterInfo::isVirtualRegister(VirtReg) && |
Chris Lattner | 50ea01e | 2005-09-09 20:29:51 +0000 | [diff] [blame] | 1017 | "Not a virtual or a physical register?"); |
Evan Cheng | 70306f8 | 2007-12-03 09:58:48 +0000 | [diff] [blame] | 1018 | |
Evan Cheng | c498b02 | 2007-11-14 07:59:08 +0000 | [diff] [blame] | 1019 | unsigned SubIdx = MO.getSubReg(); |
Evan Cheng | 549f27d3 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 1020 | if (VRM.isAssignedReg(VirtReg)) { |
Chris Lattner | 50ea01e | 2005-09-09 20:29:51 +0000 | [diff] [blame] | 1021 | // This virtual register was assigned a physreg! |
| 1022 | unsigned Phys = VRM.getPhys(VirtReg); |
Evan Cheng | 6c087e5 | 2007-04-25 22:13:27 +0000 | [diff] [blame] | 1023 | MF.setPhysRegUsed(Phys); |
Evan Cheng | e077ef6 | 2006-11-04 00:21:55 +0000 | [diff] [blame] | 1024 | if (MO.isDef()) |
| 1025 | ReusedOperands.markClobbered(Phys); |
Evan Cheng | c498b02 | 2007-11-14 07:59:08 +0000 | [diff] [blame] | 1026 | unsigned RReg = SubIdx ? MRI->getSubReg(Phys, SubIdx) : Phys; |
Evan Cheng | 32dfbea | 2007-10-12 08:50:34 +0000 | [diff] [blame] | 1027 | MI.getOperand(i).setReg(RReg); |
Chris Lattner | 50ea01e | 2005-09-09 20:29:51 +0000 | [diff] [blame] | 1028 | continue; |
| 1029 | } |
| 1030 | |
| 1031 | // This virtual register is now known to be a spilled value. |
| 1032 | if (!MO.isUse()) |
| 1033 | continue; // Handle defs in the loop below (handle use&def here though) |
Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 1034 | |
Evan Cheng | 549f27d3 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 1035 | bool DoReMat = VRM.isReMaterialized(VirtReg); |
| 1036 | int SSorRMId = DoReMat |
| 1037 | ? VRM.getReMatId(VirtReg) : VRM.getStackSlot(VirtReg); |
Evan Cheng | dc6be19 | 2007-08-14 05:42:54 +0000 | [diff] [blame] | 1038 | int ReuseSlot = SSorRMId; |
Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 1039 | |
Chris Lattner | 50ea01e | 2005-09-09 20:29:51 +0000 | [diff] [blame] | 1040 | // Check to see if this stack slot is available. |
Evan Cheng | dc6be19 | 2007-08-14 05:42:54 +0000 | [diff] [blame] | 1041 | unsigned PhysReg = Spills.getSpillSlotOrReMatPhysReg(SSorRMId); |
Evan Cheng | 32dfbea | 2007-10-12 08:50:34 +0000 | [diff] [blame] | 1042 | |
| 1043 | // If this is a sub-register use, make sure the reuse register is in the |
| 1044 | // right register class. For example, for x86 not all of the 32-bit |
| 1045 | // registers have accessible sub-registers. |
| 1046 | // Similarly so for EXTRACT_SUBREG. Consider this: |
| 1047 | // EDI = op |
| 1048 | // MOV32_mr fi#1, EDI |
| 1049 | // ... |
| 1050 | // = EXTRACT_SUBREG fi#1 |
| 1051 | // fi#1 is available in EDI, but it cannot be reused because it's not in |
| 1052 | // the right register file. |
| 1053 | if (PhysReg && |
Evan Cheng | c498b02 | 2007-11-14 07:59:08 +0000 | [diff] [blame] | 1054 | (SubIdx || MI.getOpcode() == TargetInstrInfo::EXTRACT_SUBREG)) { |
Evan Cheng | 32dfbea | 2007-10-12 08:50:34 +0000 | [diff] [blame] | 1055 | const TargetRegisterClass* RC = RegMap->getRegClass(VirtReg); |
| 1056 | if (!RC->contains(PhysReg)) |
| 1057 | PhysReg = 0; |
| 1058 | } |
| 1059 | |
Evan Cheng | dc6be19 | 2007-08-14 05:42:54 +0000 | [diff] [blame] | 1060 | if (PhysReg) { |
Chris Lattner | 2926869 | 2006-09-05 02:12:02 +0000 | [diff] [blame] | 1061 | // This spilled operand might be part of a two-address operand. If this |
| 1062 | // is the case, then changing it will necessarily require changing the |
| 1063 | // def part of the instruction as well. However, in some cases, we |
| 1064 | // aren't allowed to modify the reused register. If none of these cases |
| 1065 | // apply, reuse it. |
| 1066 | bool CanReuse = true; |
Evan Cheng | 86facc2 | 2006-12-15 06:41:01 +0000 | [diff] [blame] | 1067 | int ti = TID->getOperandConstraint(i, TOI::TIED_TO); |
Evan Cheng | 360c2dd | 2006-11-01 23:06:55 +0000 | [diff] [blame] | 1068 | if (ti != -1 && |
Dan Gohman | 92dfe20 | 2007-09-14 20:33:02 +0000 | [diff] [blame] | 1069 | MI.getOperand(ti).isRegister() && |
Evan Cheng | 360c2dd | 2006-11-01 23:06:55 +0000 | [diff] [blame] | 1070 | MI.getOperand(ti).getReg() == VirtReg) { |
Chris Lattner | 2926869 | 2006-09-05 02:12:02 +0000 | [diff] [blame] | 1071 | // Okay, we have a two address operand. We can reuse this physreg as |
Evan Cheng | 3c82cab | 2007-01-19 22:40:14 +0000 | [diff] [blame] | 1072 | // long as we are allowed to clobber the value and there isn't an |
| 1073 | // earlier def that has already clobbered the physreg. |
Evan Cheng | dc6be19 | 2007-08-14 05:42:54 +0000 | [diff] [blame] | 1074 | CanReuse = Spills.canClobberPhysReg(ReuseSlot) && |
Evan Cheng | e077ef6 | 2006-11-04 00:21:55 +0000 | [diff] [blame] | 1075 | !ReusedOperands.isClobbered(PhysReg); |
Chris Lattner | 2926869 | 2006-09-05 02:12:02 +0000 | [diff] [blame] | 1076 | } |
| 1077 | |
| 1078 | if (CanReuse) { |
Chris Lattner | addc55a | 2006-04-28 01:46:50 +0000 | [diff] [blame] | 1079 | // If this stack slot value is already available, reuse it! |
Evan Cheng | dc6be19 | 2007-08-14 05:42:54 +0000 | [diff] [blame] | 1080 | if (ReuseSlot > VirtRegMap::MAX_STACK_SLOT) |
| 1081 | DOUT << "Reusing RM#" << ReuseSlot-VirtRegMap::MAX_STACK_SLOT-1; |
Evan Cheng | 2638e1a | 2007-03-20 08:13:50 +0000 | [diff] [blame] | 1082 | else |
Evan Cheng | dc6be19 | 2007-08-14 05:42:54 +0000 | [diff] [blame] | 1083 | DOUT << "Reusing SS#" << ReuseSlot; |
Evan Cheng | 2638e1a | 2007-03-20 08:13:50 +0000 | [diff] [blame] | 1084 | DOUT << " from physreg " |
Bill Wendling | b2b9c20 | 2006-11-17 02:09:07 +0000 | [diff] [blame] | 1085 | << MRI->getName(PhysReg) << " for vreg" |
| 1086 | << VirtReg <<" instead of reloading into physreg " |
| 1087 | << MRI->getName(VRM.getPhys(VirtReg)) << "\n"; |
Evan Cheng | c498b02 | 2007-11-14 07:59:08 +0000 | [diff] [blame] | 1088 | unsigned RReg = SubIdx ? MRI->getSubReg(PhysReg, SubIdx) : PhysReg; |
Evan Cheng | 32dfbea | 2007-10-12 08:50:34 +0000 | [diff] [blame] | 1089 | MI.getOperand(i).setReg(RReg); |
Chris Lattner | addc55a | 2006-04-28 01:46:50 +0000 | [diff] [blame] | 1090 | |
| 1091 | // The only technical detail we have is that we don't know that |
| 1092 | // PhysReg won't be clobbered by a reloaded stack slot that occurs |
| 1093 | // later in the instruction. In particular, consider 'op V1, V2'. |
| 1094 | // If V1 is available in physreg R0, we would choose to reuse it |
| 1095 | // here, instead of reloading it into the register the allocator |
| 1096 | // indicated (say R1). However, V2 might have to be reloaded |
| 1097 | // later, and it might indicate that it needs to live in R0. When |
| 1098 | // this occurs, we need to have information available that |
| 1099 | // indicates it is safe to use R1 for the reload instead of R0. |
| 1100 | // |
| 1101 | // To further complicate matters, we might conflict with an alias, |
| 1102 | // or R0 and R1 might not be compatible with each other. In this |
| 1103 | // case, we actually insert a reload for V1 in R1, ensuring that |
| 1104 | // we can get at R0 or its alias. |
Evan Cheng | dc6be19 | 2007-08-14 05:42:54 +0000 | [diff] [blame] | 1105 | ReusedOperands.addReuse(i, ReuseSlot, PhysReg, |
Chris Lattner | addc55a | 2006-04-28 01:46:50 +0000 | [diff] [blame] | 1106 | VRM.getPhys(VirtReg), VirtReg); |
Evan Cheng | e077ef6 | 2006-11-04 00:21:55 +0000 | [diff] [blame] | 1107 | if (ti != -1) |
| 1108 | // Only mark it clobbered if this is a use&def operand. |
| 1109 | ReusedOperands.markClobbered(PhysReg); |
Chris Lattner | addc55a | 2006-04-28 01:46:50 +0000 | [diff] [blame] | 1110 | ++NumReused; |
Evan Cheng | fff3e19 | 2007-08-14 09:11:18 +0000 | [diff] [blame] | 1111 | |
| 1112 | if (MI.getOperand(i).isKill() && |
| 1113 | ReuseSlot <= VirtRegMap::MAX_STACK_SLOT) { |
| 1114 | // This was the last use and the spilled value is still available |
| 1115 | // for reuse. That means the spill was unnecessary! |
| 1116 | MachineInstr* DeadStore = MaybeDeadStores[ReuseSlot]; |
| 1117 | if (DeadStore) { |
| 1118 | DOUT << "Removed dead store:\t" << *DeadStore; |
| 1119 | InvalidateKills(*DeadStore, RegKills, KillOps); |
Evan Cheng | cada245 | 2007-11-28 01:28:46 +0000 | [diff] [blame] | 1120 | VRM.RemoveMachineInstrFromMaps(DeadStore); |
Evan Cheng | 66f7163 | 2007-10-19 21:23:22 +0000 | [diff] [blame] | 1121 | MBB.erase(DeadStore); |
Evan Cheng | fff3e19 | 2007-08-14 09:11:18 +0000 | [diff] [blame] | 1122 | MaybeDeadStores[ReuseSlot] = NULL; |
| 1123 | ++NumDSE; |
| 1124 | } |
| 1125 | } |
Chris Lattner | addc55a | 2006-04-28 01:46:50 +0000 | [diff] [blame] | 1126 | continue; |
Evan Cheng | 32dfbea | 2007-10-12 08:50:34 +0000 | [diff] [blame] | 1127 | } // CanReuse |
Chris Lattner | addc55a | 2006-04-28 01:46:50 +0000 | [diff] [blame] | 1128 | |
| 1129 | // Otherwise we have a situation where we have a two-address instruction |
| 1130 | // whose mod/ref operand needs to be reloaded. This reload is already |
| 1131 | // available in some register "PhysReg", but if we used PhysReg as the |
| 1132 | // operand to our 2-addr instruction, the instruction would modify |
| 1133 | // PhysReg. This isn't cool if something later uses PhysReg and expects |
| 1134 | // to get its initial value. |
Chris Lattner | 50ea01e | 2005-09-09 20:29:51 +0000 | [diff] [blame] | 1135 | // |
Chris Lattner | addc55a | 2006-04-28 01:46:50 +0000 | [diff] [blame] | 1136 | // To avoid this problem, and to avoid doing a load right after a store, |
| 1137 | // we emit a copy from PhysReg into the designated register for this |
| 1138 | // operand. |
| 1139 | unsigned DesignatedReg = VRM.getPhys(VirtReg); |
| 1140 | assert(DesignatedReg && "Must map virtreg to physreg!"); |
| 1141 | |
| 1142 | // Note that, if we reused a register for a previous operand, the |
| 1143 | // register we want to reload into might not actually be |
| 1144 | // available. If this occurs, use the register indicated by the |
| 1145 | // reuser. |
| 1146 | if (ReusedOperands.hasReuses()) |
| 1147 | DesignatedReg = ReusedOperands.GetRegForReload(DesignatedReg, &MI, |
Evan Cheng | 549f27d3 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 1148 | Spills, MaybeDeadStores, RegKills, KillOps, VRM); |
Chris Lattner | addc55a | 2006-04-28 01:46:50 +0000 | [diff] [blame] | 1149 | |
Chris Lattner | ba1fc3d | 2006-04-28 04:43:18 +0000 | [diff] [blame] | 1150 | // If the mapped designated register is actually the physreg we have |
| 1151 | // incoming, we don't need to inserted a dead copy. |
| 1152 | if (DesignatedReg == PhysReg) { |
| 1153 | // If this stack slot value is already available, reuse it! |
Evan Cheng | dc6be19 | 2007-08-14 05:42:54 +0000 | [diff] [blame] | 1154 | if (ReuseSlot > VirtRegMap::MAX_STACK_SLOT) |
| 1155 | DOUT << "Reusing RM#" << ReuseSlot-VirtRegMap::MAX_STACK_SLOT-1; |
Evan Cheng | 2638e1a | 2007-03-20 08:13:50 +0000 | [diff] [blame] | 1156 | else |
Evan Cheng | dc6be19 | 2007-08-14 05:42:54 +0000 | [diff] [blame] | 1157 | DOUT << "Reusing SS#" << ReuseSlot; |
Evan Cheng | 2638e1a | 2007-03-20 08:13:50 +0000 | [diff] [blame] | 1158 | DOUT << " from physreg " << MRI->getName(PhysReg) << " for vreg" |
Bill Wendling | b2b9c20 | 2006-11-17 02:09:07 +0000 | [diff] [blame] | 1159 | << VirtReg |
| 1160 | << " instead of reloading into same physreg.\n"; |
Evan Cheng | c498b02 | 2007-11-14 07:59:08 +0000 | [diff] [blame] | 1161 | unsigned RReg = SubIdx ? MRI->getSubReg(PhysReg, SubIdx) : PhysReg; |
Evan Cheng | 32dfbea | 2007-10-12 08:50:34 +0000 | [diff] [blame] | 1162 | MI.getOperand(i).setReg(RReg); |
Evan Cheng | 7277a7d | 2007-11-02 17:35:08 +0000 | [diff] [blame] | 1163 | ReusedOperands.markClobbered(RReg); |
Chris Lattner | ba1fc3d | 2006-04-28 04:43:18 +0000 | [diff] [blame] | 1164 | ++NumReused; |
| 1165 | continue; |
| 1166 | } |
| 1167 | |
Evan Cheng | 32dfbea | 2007-10-12 08:50:34 +0000 | [diff] [blame] | 1168 | const TargetRegisterClass* RC = RegMap->getRegClass(VirtReg); |
Evan Cheng | 6c087e5 | 2007-04-25 22:13:27 +0000 | [diff] [blame] | 1169 | MF.setPhysRegUsed(DesignatedReg); |
Evan Cheng | e077ef6 | 2006-11-04 00:21:55 +0000 | [diff] [blame] | 1170 | ReusedOperands.markClobbered(DesignatedReg); |
Evan Cheng | 9efce63 | 2007-09-26 06:25:56 +0000 | [diff] [blame] | 1171 | MRI->copyRegToReg(MBB, &MI, DesignatedReg, PhysReg, RC, RC); |
Evan Cheng | de4e942 | 2007-02-25 09:51:27 +0000 | [diff] [blame] | 1172 | |
Evan Cheng | 6b44809 | 2007-03-02 08:52:00 +0000 | [diff] [blame] | 1173 | MachineInstr *CopyMI = prior(MII); |
Evan Cheng | 0c40d72 | 2007-07-11 05:28:39 +0000 | [diff] [blame] | 1174 | UpdateKills(*CopyMI, RegKills, KillOps); |
Evan Cheng | de4e942 | 2007-02-25 09:51:27 +0000 | [diff] [blame] | 1175 | |
Chris Lattner | addc55a | 2006-04-28 01:46:50 +0000 | [diff] [blame] | 1176 | // This invalidates DesignatedReg. |
| 1177 | Spills.ClobberPhysReg(DesignatedReg); |
| 1178 | |
Evan Cheng | dc6be19 | 2007-08-14 05:42:54 +0000 | [diff] [blame] | 1179 | Spills.addAvailable(ReuseSlot, &MI, DesignatedReg); |
Evan Cheng | 32dfbea | 2007-10-12 08:50:34 +0000 | [diff] [blame] | 1180 | unsigned RReg = |
Evan Cheng | c498b02 | 2007-11-14 07:59:08 +0000 | [diff] [blame] | 1181 | SubIdx ? MRI->getSubReg(DesignatedReg, SubIdx) : DesignatedReg; |
Evan Cheng | 32dfbea | 2007-10-12 08:50:34 +0000 | [diff] [blame] | 1182 | MI.getOperand(i).setReg(RReg); |
Bill Wendling | b2b9c20 | 2006-11-17 02:09:07 +0000 | [diff] [blame] | 1183 | DOUT << '\t' << *prior(MII); |
Chris Lattner | 50ea01e | 2005-09-09 20:29:51 +0000 | [diff] [blame] | 1184 | ++NumReused; |
| 1185 | continue; |
Evan Cheng | 66f7163 | 2007-10-19 21:23:22 +0000 | [diff] [blame] | 1186 | } // if (PhysReg) |
Chris Lattner | 50ea01e | 2005-09-09 20:29:51 +0000 | [diff] [blame] | 1187 | |
| 1188 | // Otherwise, reload it and remember that we have it. |
| 1189 | PhysReg = VRM.getPhys(VirtReg); |
Chris Lattner | 172c362 | 2006-01-04 06:47:48 +0000 | [diff] [blame] | 1190 | assert(PhysReg && "Must map virtreg to physreg!"); |
Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 1191 | |
Chris Lattner | 50ea01e | 2005-09-09 20:29:51 +0000 | [diff] [blame] | 1192 | // Note that, if we reused a register for a previous operand, the |
| 1193 | // register we want to reload into might not actually be |
| 1194 | // available. If this occurs, use the register indicated by the |
| 1195 | // reuser. |
Chris Lattner | 540fec6 | 2006-02-25 01:51:33 +0000 | [diff] [blame] | 1196 | if (ReusedOperands.hasReuses()) |
| 1197 | PhysReg = ReusedOperands.GetRegForReload(PhysReg, &MI, |
Evan Cheng | 549f27d3 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 1198 | Spills, MaybeDeadStores, RegKills, KillOps, VRM); |
Chris Lattner | 540fec6 | 2006-02-25 01:51:33 +0000 | [diff] [blame] | 1199 | |
Evan Cheng | 6c087e5 | 2007-04-25 22:13:27 +0000 | [diff] [blame] | 1200 | MF.setPhysRegUsed(PhysReg); |
Evan Cheng | e077ef6 | 2006-11-04 00:21:55 +0000 | [diff] [blame] | 1201 | ReusedOperands.markClobbered(PhysReg); |
Evan Cheng | 549f27d3 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 1202 | if (DoReMat) { |
Evan Cheng | 2638e1a | 2007-03-20 08:13:50 +0000 | [diff] [blame] | 1203 | MRI->reMaterialize(MBB, &MI, PhysReg, VRM.getReMaterializedMI(VirtReg)); |
Evan Cheng | 9193514 | 2007-04-04 07:40:01 +0000 | [diff] [blame] | 1204 | ++NumReMats; |
| 1205 | } else { |
Evan Cheng | 32dfbea | 2007-10-12 08:50:34 +0000 | [diff] [blame] | 1206 | const TargetRegisterClass* RC = RegMap->getRegClass(VirtReg); |
Evan Cheng | 549f27d3 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 1207 | MRI->loadRegFromStackSlot(MBB, &MI, PhysReg, SSorRMId, RC); |
Evan Cheng | 9193514 | 2007-04-04 07:40:01 +0000 | [diff] [blame] | 1208 | ++NumLoads; |
| 1209 | } |
Chris Lattner | 50ea01e | 2005-09-09 20:29:51 +0000 | [diff] [blame] | 1210 | // This invalidates PhysReg. |
Chris Lattner | 66cf80f | 2006-02-03 23:13:58 +0000 | [diff] [blame] | 1211 | Spills.ClobberPhysReg(PhysReg); |
Chris Lattner | 50ea01e | 2005-09-09 20:29:51 +0000 | [diff] [blame] | 1212 | |
| 1213 | // Any stores to this stack slot are not dead anymore. |
Evan Cheng | 549f27d3 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 1214 | if (!DoReMat) |
Evan Cheng | fff3e19 | 2007-08-14 09:11:18 +0000 | [diff] [blame] | 1215 | MaybeDeadStores[SSorRMId] = NULL; |
Evan Cheng | 549f27d3 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 1216 | Spills.addAvailable(SSorRMId, &MI, PhysReg); |
Evan Cheng | de4e942 | 2007-02-25 09:51:27 +0000 | [diff] [blame] | 1217 | // Assumes this is the last use. IsKill will be unset if reg is reused |
| 1218 | // unless it's a two-address operand. |
| 1219 | if (TID->getOperandConstraint(i, TOI::TIED_TO) == -1) |
| 1220 | MI.getOperand(i).setIsKill(); |
Evan Cheng | c498b02 | 2007-11-14 07:59:08 +0000 | [diff] [blame] | 1221 | unsigned RReg = SubIdx ? MRI->getSubReg(PhysReg, SubIdx) : PhysReg; |
Evan Cheng | 32dfbea | 2007-10-12 08:50:34 +0000 | [diff] [blame] | 1222 | MI.getOperand(i).setReg(RReg); |
Evan Cheng | 0c40d72 | 2007-07-11 05:28:39 +0000 | [diff] [blame] | 1223 | UpdateKills(*prior(MII), RegKills, KillOps); |
Bill Wendling | b2b9c20 | 2006-11-17 02:09:07 +0000 | [diff] [blame] | 1224 | DOUT << '\t' << *prior(MII); |
Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 1225 | } |
| 1226 | |
Bill Wendling | b2b9c20 | 2006-11-17 02:09:07 +0000 | [diff] [blame] | 1227 | DOUT << '\t' << MI; |
Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 1228 | |
Evan Cheng | 81a0382 | 2007-11-17 00:40:40 +0000 | [diff] [blame] | 1229 | |
Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 1230 | // If we have folded references to memory operands, make sure we clear all |
| 1231 | // physical registers that may contain the value of the spilled virtual |
| 1232 | // register |
Evan Cheng | 66f7163 | 2007-10-19 21:23:22 +0000 | [diff] [blame] | 1233 | SmallSet<int, 2> FoldedSS; |
Chris Lattner | 8f1d640 | 2005-01-14 15:54:24 +0000 | [diff] [blame] | 1234 | for (tie(I, End) = VRM.getFoldedVirts(&MI); I != End; ++I) { |
Chris Lattner | bec6a9e | 2004-10-01 23:15:36 +0000 | [diff] [blame] | 1235 | unsigned VirtReg = I->second.first; |
| 1236 | VirtRegMap::ModRef MR = I->second.second; |
Evan Cheng | 66f7163 | 2007-10-19 21:23:22 +0000 | [diff] [blame] | 1237 | DOUT << "Folded vreg: " << VirtReg << " MR: " << MR; |
Evan Cheng | 81a0382 | 2007-11-17 00:40:40 +0000 | [diff] [blame] | 1238 | |
Chris Lattner | cea8688 | 2005-09-19 06:56:21 +0000 | [diff] [blame] | 1239 | int SS = VRM.getStackSlot(VirtReg); |
Evan Cheng | 81a0382 | 2007-11-17 00:40:40 +0000 | [diff] [blame] | 1240 | if (SS == VirtRegMap::NO_STACK_SLOT) |
| 1241 | continue; |
Evan Cheng | 90a43c3 | 2007-08-15 20:20:34 +0000 | [diff] [blame] | 1242 | FoldedSS.insert(SS); |
Bill Wendling | b2b9c20 | 2006-11-17 02:09:07 +0000 | [diff] [blame] | 1243 | DOUT << " - StackSlot: " << SS << "\n"; |
Chris Lattner | cea8688 | 2005-09-19 06:56:21 +0000 | [diff] [blame] | 1244 | |
| 1245 | // If this folded instruction is just a use, check to see if it's a |
| 1246 | // straight load from the virt reg slot. |
| 1247 | if ((MR & VirtRegMap::isRef) && !(MR & VirtRegMap::isMod)) { |
| 1248 | int FrameIdx; |
Evan Cheng | 32dfbea | 2007-10-12 08:50:34 +0000 | [diff] [blame] | 1249 | unsigned DestReg = TII->isLoadFromStackSlot(&MI, FrameIdx); |
| 1250 | if (DestReg && FrameIdx == SS) { |
| 1251 | // If this spill slot is available, turn it into a copy (or nothing) |
| 1252 | // instead of leaving it as a load! |
| 1253 | if (unsigned InReg = Spills.getSpillSlotOrReMatPhysReg(SS)) { |
| 1254 | DOUT << "Promoted Load To Copy: " << MI; |
| 1255 | if (DestReg != InReg) { |
| 1256 | const TargetRegisterClass *RC = RegMap->getRegClass(VirtReg); |
| 1257 | MRI->copyRegToReg(MBB, &MI, DestReg, InReg, RC, RC); |
| 1258 | // Revisit the copy so we make sure to notice the effects of the |
| 1259 | // operation on the destreg (either needing to RA it if it's |
| 1260 | // virtual or needing to clobber any values if it's physical). |
| 1261 | NextMII = &MI; |
| 1262 | --NextMII; // backtrack to the copy. |
| 1263 | BackTracked = true; |
| 1264 | } else |
| 1265 | DOUT << "Removing now-noop copy: " << MI; |
Evan Cheng | de4e942 | 2007-02-25 09:51:27 +0000 | [diff] [blame] | 1266 | |
Evan Cheng | cada245 | 2007-11-28 01:28:46 +0000 | [diff] [blame] | 1267 | VRM.RemoveMachineInstrFromMaps(&MI); |
Evan Cheng | 32dfbea | 2007-10-12 08:50:34 +0000 | [diff] [blame] | 1268 | MBB.erase(&MI); |
| 1269 | Erased = true; |
| 1270 | goto ProcessNextInst; |
Chris Lattner | cea8688 | 2005-09-19 06:56:21 +0000 | [diff] [blame] | 1271 | } |
Evan Cheng | 7f56625 | 2007-10-13 02:50:24 +0000 | [diff] [blame] | 1272 | } else { |
| 1273 | unsigned PhysReg = Spills.getSpillSlotOrReMatPhysReg(SS); |
| 1274 | SmallVector<MachineInstr*, 4> NewMIs; |
| 1275 | if (PhysReg && |
| 1276 | MRI->unfoldMemoryOperand(MF, &MI, PhysReg, false, false, NewMIs)) { |
| 1277 | MBB.insert(MII, NewMIs[0]); |
Evan Cheng | cada245 | 2007-11-28 01:28:46 +0000 | [diff] [blame] | 1278 | VRM.RemoveMachineInstrFromMaps(&MI); |
Evan Cheng | 7f56625 | 2007-10-13 02:50:24 +0000 | [diff] [blame] | 1279 | MBB.erase(&MI); |
| 1280 | Erased = true; |
| 1281 | --NextMII; // backtrack to the unfolded instruction. |
| 1282 | BackTracked = true; |
| 1283 | goto ProcessNextInst; |
| 1284 | } |
Chris Lattner | cea8688 | 2005-09-19 06:56:21 +0000 | [diff] [blame] | 1285 | } |
| 1286 | } |
| 1287 | |
| 1288 | // If this reference is not a use, any previous store is now dead. |
| 1289 | // Otherwise, the store to this stack slot is not dead anymore. |
Evan Cheng | fff3e19 | 2007-08-14 09:11:18 +0000 | [diff] [blame] | 1290 | MachineInstr* DeadStore = MaybeDeadStores[SS]; |
| 1291 | if (DeadStore) { |
Evan Cheng | 66f7163 | 2007-10-19 21:23:22 +0000 | [diff] [blame] | 1292 | bool isDead = !(MR & VirtRegMap::isRef); |
Evan Cheng | 7f56625 | 2007-10-13 02:50:24 +0000 | [diff] [blame] | 1293 | MachineInstr *NewStore = NULL; |
Evan Cheng | cbfb9b2 | 2007-10-22 03:01:44 +0000 | [diff] [blame] | 1294 | if (MR & VirtRegMap::isModRef) { |
Evan Cheng | 7f56625 | 2007-10-13 02:50:24 +0000 | [diff] [blame] | 1295 | unsigned PhysReg = Spills.getSpillSlotOrReMatPhysReg(SS); |
| 1296 | SmallVector<MachineInstr*, 4> NewMIs; |
Evan Cheng | 35a3e4a | 2007-12-04 19:19:45 +0000 | [diff] [blame] | 1297 | // We can reuse this physreg as long as we are allowed to clobber |
| 1298 | // the value and there isn't an earlier def that has already clobbered the |
| 1299 | // physreg. |
Evan Cheng | 7f56625 | 2007-10-13 02:50:24 +0000 | [diff] [blame] | 1300 | if (PhysReg && |
| 1301 | DeadStore->findRegisterUseOperandIdx(PhysReg, true) != -1 && |
| 1302 | MRI->unfoldMemoryOperand(MF, &MI, PhysReg, false, true, NewMIs)) { |
| 1303 | MBB.insert(MII, NewMIs[0]); |
| 1304 | NewStore = NewMIs[1]; |
| 1305 | MBB.insert(MII, NewStore); |
Evan Cheng | cada245 | 2007-11-28 01:28:46 +0000 | [diff] [blame] | 1306 | VRM.RemoveMachineInstrFromMaps(&MI); |
Evan Cheng | 7f56625 | 2007-10-13 02:50:24 +0000 | [diff] [blame] | 1307 | MBB.erase(&MI); |
| 1308 | Erased = true; |
| 1309 | --NextMII; |
| 1310 | --NextMII; // backtrack to the unfolded instruction. |
| 1311 | BackTracked = true; |
Evan Cheng | 66f7163 | 2007-10-19 21:23:22 +0000 | [diff] [blame] | 1312 | isDead = true; |
| 1313 | } |
Evan Cheng | 7f56625 | 2007-10-13 02:50:24 +0000 | [diff] [blame] | 1314 | } |
| 1315 | |
| 1316 | if (isDead) { // Previous store is dead. |
Chris Lattner | cea8688 | 2005-09-19 06:56:21 +0000 | [diff] [blame] | 1317 | // If we get here, the store is dead, nuke it now. |
Evan Cheng | fff3e19 | 2007-08-14 09:11:18 +0000 | [diff] [blame] | 1318 | DOUT << "Removed dead store:\t" << *DeadStore; |
| 1319 | InvalidateKills(*DeadStore, RegKills, KillOps); |
Evan Cheng | cada245 | 2007-11-28 01:28:46 +0000 | [diff] [blame] | 1320 | VRM.RemoveMachineInstrFromMaps(DeadStore); |
Evan Cheng | 7f56625 | 2007-10-13 02:50:24 +0000 | [diff] [blame] | 1321 | MBB.erase(DeadStore); |
| 1322 | if (!NewStore) |
| 1323 | ++NumDSE; |
Chris Lattner | cea8688 | 2005-09-19 06:56:21 +0000 | [diff] [blame] | 1324 | } |
Evan Cheng | 7f56625 | 2007-10-13 02:50:24 +0000 | [diff] [blame] | 1325 | |
Evan Cheng | fff3e19 | 2007-08-14 09:11:18 +0000 | [diff] [blame] | 1326 | MaybeDeadStores[SS] = NULL; |
Evan Cheng | 7f56625 | 2007-10-13 02:50:24 +0000 | [diff] [blame] | 1327 | if (NewStore) { |
| 1328 | // Treat this store as a spill merged into a copy. That makes the |
| 1329 | // stack slot value available. |
| 1330 | VRM.virtFolded(VirtReg, NewStore, VirtRegMap::isMod); |
| 1331 | goto ProcessNextInst; |
| 1332 | } |
Chris Lattner | cea8688 | 2005-09-19 06:56:21 +0000 | [diff] [blame] | 1333 | } |
| 1334 | |
| 1335 | // If the spill slot value is available, and this is a new definition of |
| 1336 | // the value, the value is not available anymore. |
| 1337 | if (MR & VirtRegMap::isMod) { |
Chris Lattner | 07cf141 | 2006-02-03 00:36:31 +0000 | [diff] [blame] | 1338 | // Notice that the value in this stack slot has been modified. |
Evan Cheng | 549f27d3 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 1339 | Spills.ModifyStackSlotOrReMat(SS); |
Chris Lattner | cd81639 | 2006-02-02 23:29:36 +0000 | [diff] [blame] | 1340 | |
| 1341 | // If this is *just* a mod of the value, check to see if this is just a |
| 1342 | // store to the spill slot (i.e. the spill got merged into the copy). If |
| 1343 | // so, realize that the vreg is available now, and add the store to the |
| 1344 | // MaybeDeadStore info. |
| 1345 | int StackSlot; |
| 1346 | if (!(MR & VirtRegMap::isRef)) { |
| 1347 | if (unsigned SrcReg = TII->isStoreToStackSlot(&MI, StackSlot)) { |
| 1348 | assert(MRegisterInfo::isPhysicalRegister(SrcReg) && |
| 1349 | "Src hasn't been allocated yet?"); |
Chris Lattner | 07cf141 | 2006-02-03 00:36:31 +0000 | [diff] [blame] | 1350 | // Okay, this is certainly a store of SrcReg to [StackSlot]. Mark |
Chris Lattner | cd81639 | 2006-02-02 23:29:36 +0000 | [diff] [blame] | 1351 | // this as a potentially dead store in case there is a subsequent |
| 1352 | // store into the stack slot without a read from it. |
| 1353 | MaybeDeadStores[StackSlot] = &MI; |
| 1354 | |
Chris Lattner | cd81639 | 2006-02-02 23:29:36 +0000 | [diff] [blame] | 1355 | // If the stack slot value was previously available in some other |
| 1356 | // register, change it now. Otherwise, make the register available, |
| 1357 | // in PhysReg. |
Evan Cheng | 91e2390 | 2007-02-23 01:13:26 +0000 | [diff] [blame] | 1358 | Spills.addAvailable(StackSlot, &MI, SrcReg, false/*don't clobber*/); |
Chris Lattner | cd81639 | 2006-02-02 23:29:36 +0000 | [diff] [blame] | 1359 | } |
| 1360 | } |
Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 1361 | } |
Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 1362 | } |
| 1363 | |
Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 1364 | // Process all of the spilled defs. |
| 1365 | for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) { |
| 1366 | MachineOperand &MO = MI.getOperand(i); |
Evan Cheng | 66f7163 | 2007-10-19 21:23:22 +0000 | [diff] [blame] | 1367 | if (!(MO.isRegister() && MO.getReg() && MO.isDef())) |
| 1368 | continue; |
Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 1369 | |
Evan Cheng | 66f7163 | 2007-10-19 21:23:22 +0000 | [diff] [blame] | 1370 | unsigned VirtReg = MO.getReg(); |
| 1371 | if (!MRegisterInfo::isVirtualRegister(VirtReg)) { |
| 1372 | // Check to see if this is a noop copy. If so, eliminate the |
| 1373 | // instruction before considering the dest reg to be changed. |
| 1374 | unsigned Src, Dst; |
| 1375 | if (TII->isMoveInstr(MI, Src, Dst) && Src == Dst) { |
| 1376 | ++NumDCE; |
| 1377 | DOUT << "Removing now-noop copy: " << MI; |
| 1378 | MBB.erase(&MI); |
| 1379 | Erased = true; |
Evan Cheng | cada245 | 2007-11-28 01:28:46 +0000 | [diff] [blame] | 1380 | VRM.RemoveMachineInstrFromMaps(&MI); |
Evan Cheng | 66f7163 | 2007-10-19 21:23:22 +0000 | [diff] [blame] | 1381 | Spills.disallowClobberPhysReg(VirtReg); |
| 1382 | goto ProcessNextInst; |
| 1383 | } |
| 1384 | |
| 1385 | // If it's not a no-op copy, it clobbers the value in the destreg. |
| 1386 | Spills.ClobberPhysReg(VirtReg); |
| 1387 | ReusedOperands.markClobbered(VirtReg); |
| 1388 | |
| 1389 | // Check to see if this instruction is a load from a stack slot into |
| 1390 | // a register. If so, this provides the stack slot value in the reg. |
| 1391 | int FrameIdx; |
| 1392 | if (unsigned DestReg = TII->isLoadFromStackSlot(&MI, FrameIdx)) { |
| 1393 | assert(DestReg == VirtReg && "Unknown load situation!"); |
| 1394 | |
| 1395 | // If it is a folded reference, then it's not safe to clobber. |
| 1396 | bool Folded = FoldedSS.count(FrameIdx); |
| 1397 | // Otherwise, if it wasn't available, remember that it is now! |
| 1398 | Spills.addAvailable(FrameIdx, &MI, DestReg, !Folded); |
| 1399 | goto ProcessNextInst; |
| 1400 | } |
| 1401 | |
| 1402 | continue; |
| 1403 | } |
| 1404 | |
Evan Cheng | c498b02 | 2007-11-14 07:59:08 +0000 | [diff] [blame] | 1405 | unsigned SubIdx = MO.getSubReg(); |
Evan Cheng | 66f7163 | 2007-10-19 21:23:22 +0000 | [diff] [blame] | 1406 | bool DoReMat = VRM.isReMaterialized(VirtReg); |
| 1407 | if (DoReMat) |
| 1408 | ReMatDefs.insert(&MI); |
| 1409 | |
| 1410 | // The only vregs left are stack slot definitions. |
| 1411 | int StackSlot = VRM.getStackSlot(VirtReg); |
| 1412 | const TargetRegisterClass *RC = RegMap->getRegClass(VirtReg); |
| 1413 | |
| 1414 | // If this def is part of a two-address operand, make sure to execute |
| 1415 | // the store from the correct physical register. |
| 1416 | unsigned PhysReg; |
| 1417 | int TiedOp = MI.getInstrDescriptor()->findTiedToSrcOperand(i); |
Evan Cheng | 7277a7d | 2007-11-02 17:35:08 +0000 | [diff] [blame] | 1418 | if (TiedOp != -1) { |
Evan Cheng | 66f7163 | 2007-10-19 21:23:22 +0000 | [diff] [blame] | 1419 | PhysReg = MI.getOperand(TiedOp).getReg(); |
Evan Cheng | c498b02 | 2007-11-14 07:59:08 +0000 | [diff] [blame] | 1420 | if (SubIdx) { |
Evan Cheng | 7277a7d | 2007-11-02 17:35:08 +0000 | [diff] [blame] | 1421 | unsigned SuperReg = findSuperReg(RC, PhysReg, SubIdx, MRI); |
| 1422 | assert(SuperReg && MRI->getSubReg(SuperReg, SubIdx) == PhysReg && |
| 1423 | "Can't find corresponding super-register!"); |
| 1424 | PhysReg = SuperReg; |
| 1425 | } |
| 1426 | } else { |
Evan Cheng | 66f7163 | 2007-10-19 21:23:22 +0000 | [diff] [blame] | 1427 | PhysReg = VRM.getPhys(VirtReg); |
| 1428 | if (ReusedOperands.isClobbered(PhysReg)) { |
| 1429 | // Another def has taken the assigned physreg. It must have been a |
| 1430 | // use&def which got it due to reuse. Undo the reuse! |
| 1431 | PhysReg = ReusedOperands.GetRegForReload(PhysReg, &MI, |
| 1432 | Spills, MaybeDeadStores, RegKills, KillOps, VRM); |
| 1433 | } |
| 1434 | } |
| 1435 | |
| 1436 | MF.setPhysRegUsed(PhysReg); |
Evan Cheng | c498b02 | 2007-11-14 07:59:08 +0000 | [diff] [blame] | 1437 | unsigned RReg = SubIdx ? MRI->getSubReg(PhysReg, SubIdx) : PhysReg; |
Evan Cheng | 7277a7d | 2007-11-02 17:35:08 +0000 | [diff] [blame] | 1438 | ReusedOperands.markClobbered(RReg); |
| 1439 | MI.getOperand(i).setReg(RReg); |
| 1440 | |
Evan Cheng | 66f7163 | 2007-10-19 21:23:22 +0000 | [diff] [blame] | 1441 | if (!MO.isDead()) { |
Evan Cheng | 66f7163 | 2007-10-19 21:23:22 +0000 | [diff] [blame] | 1442 | MachineInstr *&LastStore = MaybeDeadStores[StackSlot]; |
Evan Cheng | 35a3e4a | 2007-12-04 19:19:45 +0000 | [diff] [blame] | 1443 | SpillRegToStackSlot(MBB, MII, -1, PhysReg, StackSlot, RC, true, |
| 1444 | LastStore, Spills, ReMatDefs, RegKills, KillOps, VRM); |
Evan Cheng | e4b3900 | 2007-12-03 21:31:55 +0000 | [diff] [blame] | 1445 | NextMII = next(MII); |
Evan Cheng | 66f7163 | 2007-10-19 21:23:22 +0000 | [diff] [blame] | 1446 | |
| 1447 | // Check to see if this is a noop copy. If so, eliminate the |
| 1448 | // instruction before considering the dest reg to be changed. |
| 1449 | { |
Chris Lattner | 2926869 | 2006-09-05 02:12:02 +0000 | [diff] [blame] | 1450 | unsigned Src, Dst; |
| 1451 | if (TII->isMoveInstr(MI, Src, Dst) && Src == Dst) { |
| 1452 | ++NumDCE; |
Bill Wendling | b2b9c20 | 2006-11-17 02:09:07 +0000 | [diff] [blame] | 1453 | DOUT << "Removing now-noop copy: " << MI; |
Chris Lattner | 2926869 | 2006-09-05 02:12:02 +0000 | [diff] [blame] | 1454 | MBB.erase(&MI); |
Evan Cheng | 0c40d72 | 2007-07-11 05:28:39 +0000 | [diff] [blame] | 1455 | Erased = true; |
Evan Cheng | cada245 | 2007-11-28 01:28:46 +0000 | [diff] [blame] | 1456 | VRM.RemoveMachineInstrFromMaps(&MI); |
Evan Cheng | 66f7163 | 2007-10-19 21:23:22 +0000 | [diff] [blame] | 1457 | UpdateKills(*LastStore, RegKills, KillOps); |
Chris Lattner | 2926869 | 2006-09-05 02:12:02 +0000 | [diff] [blame] | 1458 | goto ProcessNextInst; |
Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 1459 | } |
Misha Brukman | edf128a | 2005-04-21 22:36:52 +0000 | [diff] [blame] | 1460 | } |
Evan Cheng | 66f7163 | 2007-10-19 21:23:22 +0000 | [diff] [blame] | 1461 | } |
Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 1462 | } |
Chris Lattner | cea8688 | 2005-09-19 06:56:21 +0000 | [diff] [blame] | 1463 | ProcessNextInst: |
Evan Cheng | 35a3e4a | 2007-12-04 19:19:45 +0000 | [diff] [blame] | 1464 | if (!Erased && !BackTracked) { |
Evan Cheng | 0c40d72 | 2007-07-11 05:28:39 +0000 | [diff] [blame] | 1465 | for (MachineBasicBlock::iterator II = MI; II != NextMII; ++II) |
| 1466 | UpdateKills(*II, RegKills, KillOps); |
Evan Cheng | 35a3e4a | 2007-12-04 19:19:45 +0000 | [diff] [blame] | 1467 | } |
Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 1468 | MII = NextMII; |
| 1469 | } |
Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 1470 | } |
| 1471 | |
Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 1472 | llvm::Spiller* llvm::createSpiller() { |
| 1473 | switch (SpillerOpt) { |
| 1474 | default: assert(0 && "Unreachable!"); |
| 1475 | case local: |
| 1476 | return new LocalSpiller(); |
| 1477 | case simple: |
| 1478 | return new SimpleSpiller(); |
| 1479 | } |
Alkis Evlogimenos | 0d6c5b6 | 2004-02-24 08:58:30 +0000 | [diff] [blame] | 1480 | } |