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Evan Cheng3f32d652008-06-04 09:18:41 +00001//===-- LiveStackAnalysis.cpp - Live Stack Slot Analysis ------------------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file implements the live stack slot analysis pass. It is analogous to
11// live interval analysis except it's analyzing liveness of stack slots rather
12// than registers.
13//
14//===----------------------------------------------------------------------===//
15
Evan Cheng3f32d652008-06-04 09:18:41 +000016#include "llvm/CodeGen/LiveStackAnalysis.h"
Chandler Carruthd04a8d42012-12-03 16:50:05 +000017#include "llvm/ADT/Statistic.h"
Lang Hamesf41538d2009-06-02 16:53:25 +000018#include "llvm/CodeGen/LiveIntervalAnalysis.h"
Evan Cheng3f32d652008-06-04 09:18:41 +000019#include "llvm/CodeGen/Passes.h"
Evan Cheng3f32d652008-06-04 09:18:41 +000020#include "llvm/Support/Debug.h"
Chris Lattnerc02497f2009-08-23 03:47:42 +000021#include "llvm/Support/raw_ostream.h"
Chandler Carruthd04a8d42012-12-03 16:50:05 +000022#include "llvm/Target/TargetRegisterInfo.h"
Lang Hamesf41538d2009-06-02 16:53:25 +000023#include <limits>
Evan Cheng3f32d652008-06-04 09:18:41 +000024using namespace llvm;
25
Stephen Hinesdce4a402014-05-29 02:49:00 -070026#define DEBUG_TYPE "livestacks"
27
Evan Cheng3f32d652008-06-04 09:18:41 +000028char LiveStacks::ID = 0;
Evan Chengbb36a432012-09-21 20:04:28 +000029INITIALIZE_PASS_BEGIN(LiveStacks, "livestacks",
30 "Live Stack Slot Analysis", false, false)
31INITIALIZE_PASS_DEPENDENCY(SlotIndexes)
32INITIALIZE_PASS_END(LiveStacks, "livestacks",
Owen Andersonce665bd2010-10-07 22:25:06 +000033 "Live Stack Slot Analysis", false, false)
Evan Cheng3f32d652008-06-04 09:18:41 +000034
Jakob Stoklund Olesen2d172932010-10-26 00:11:33 +000035char &llvm::LiveStacksID = LiveStacks::ID;
36
Evan Cheng3f32d652008-06-04 09:18:41 +000037void LiveStacks::getAnalysisUsage(AnalysisUsage &AU) const {
Evan Chengef901c52008-09-22 22:26:15 +000038 AU.setPreservesAll();
Lang Hames233a60e2009-11-03 23:52:08 +000039 AU.addPreserved<SlotIndexes>();
40 AU.addRequiredTransitive<SlotIndexes>();
Evan Chengbbeeb2a2008-09-22 20:58:04 +000041 MachineFunctionPass::getAnalysisUsage(AU);
Evan Cheng3f32d652008-06-04 09:18:41 +000042}
43
44void LiveStacks::releaseMemory() {
Benjamin Kramerce9a20b2010-06-26 11:30:59 +000045 // Release VNInfo memory regions, VNInfo objects don't need to be dtor'd.
46 VNInfoAllocator.Reset();
Evan Chengc781a242009-05-03 18:32:42 +000047 S2IMap.clear();
48 S2RCMap.clear();
Evan Cheng3f32d652008-06-04 09:18:41 +000049}
50
Jakob Stoklund Olesene27e1ca2011-09-30 22:18:51 +000051bool LiveStacks::runOnMachineFunction(MachineFunction &MF) {
52 TRI = MF.getTarget().getRegisterInfo();
Evan Cheng3f32d652008-06-04 09:18:41 +000053 // FIXME: No analysis is being done right now. We are relying on the
54 // register allocators to provide the information.
55 return false;
56}
57
Jakob Stoklund Olesenbe97e902011-01-09 21:17:37 +000058LiveInterval &
59LiveStacks::getOrCreateInterval(int Slot, const TargetRegisterClass *RC) {
60 assert(Slot >= 0 && "Spill slot indice must be >= 0");
61 SS2IntervalMap::iterator I = S2IMap.find(Slot);
62 if (I == S2IMap.end()) {
63 I = S2IMap.insert(I, std::make_pair(Slot,
64 LiveInterval(TargetRegisterInfo::index2StackSlot(Slot), 0.0F)));
65 S2RCMap.insert(std::make_pair(Slot, RC));
66 } else {
67 // Use the largest common subclass register class.
68 const TargetRegisterClass *OldRC = S2RCMap[Slot];
Jakob Stoklund Olesene27e1ca2011-09-30 22:18:51 +000069 S2RCMap[Slot] = TRI->getCommonSubClass(OldRC, RC);
Jakob Stoklund Olesenbe97e902011-01-09 21:17:37 +000070 }
71 return I->second;
72}
73
Evan Cheng3f32d652008-06-04 09:18:41 +000074/// print - Implement the dump method.
Chris Lattner45cfe542009-08-23 06:03:38 +000075void LiveStacks::print(raw_ostream &OS, const Module*) const {
Chris Lattnerc02497f2009-08-23 03:47:42 +000076
77 OS << "********** INTERVALS **********\n";
Evan Cheng3f32d652008-06-04 09:18:41 +000078 for (const_iterator I = begin(), E = end(); I != E; ++I) {
Chris Lattnerc02497f2009-08-23 03:47:42 +000079 I->second.print(OS);
Evan Chengc781a242009-05-03 18:32:42 +000080 int Slot = I->first;
81 const TargetRegisterClass *RC = getIntervalRegClass(Slot);
82 if (RC)
Chris Lattnerc02497f2009-08-23 03:47:42 +000083 OS << " [" << RC->getName() << "]\n";
Evan Chengc781a242009-05-03 18:32:42 +000084 else
Chris Lattnerc02497f2009-08-23 03:47:42 +000085 OS << " [Unknown]\n";
Evan Cheng3f32d652008-06-04 09:18:41 +000086 }
87}