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Chris Lattner97f06932009-10-19 20:20:46 +00001//===-- ARMAsmPrinter.cpp - Print machine code to an ARM .s file ----------===//
2//
Rafael Espindola7bc59bc2006-05-14 22:18:28 +00003// The LLVM Compiler Infrastructure
4//
Chris Lattner4ee451d2007-12-29 20:36:04 +00005// This file is distributed under the University of Illinois Open Source
Rafael Espindola7bc59bc2006-05-14 22:18:28 +00006// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains a printer that converts from our internal representation
11// of machine-dependent LLVM code to GAS-format ARM assembly language.
12//
13//===----------------------------------------------------------------------===//
14
Chris Lattner95b2c7d2006-12-19 22:59:26 +000015#define DEBUG_TYPE "asm-printer"
Rafael Espindola7bc59bc2006-05-14 22:18:28 +000016#include "ARM.h"
Jim Grosbachbaf120f2010-12-01 03:45:07 +000017#include "ARMAsmPrinter.h"
Evan Chengb72d2a92011-01-11 21:46:47 +000018#include "ARMAddressingModes.h"
19#include "ARMBuildAttrs.h"
20#include "ARMBaseRegisterInfo.h"
21#include "ARMConstantPoolValue.h"
Chris Lattner97f06932009-10-19 20:20:46 +000022#include "ARMMachineFunctionInfo.h"
Evan Cheng5de5d4b2011-01-17 08:03:18 +000023#include "ARMMCExpr.h"
Chris Lattner97f06932009-10-19 20:20:46 +000024#include "ARMTargetMachine.h"
Jason W Kim17b443d2010-10-11 23:01:44 +000025#include "ARMTargetObjectFile.h"
Evan Chengb72d2a92011-01-11 21:46:47 +000026#include "InstPrinter/ARMInstPrinter.h"
Dale Johannesen3f282aa2010-04-26 20:07:31 +000027#include "llvm/Analysis/DebugInfo.h"
Rafael Espindola7bc59bc2006-05-14 22:18:28 +000028#include "llvm/Constants.h"
Rafael Espindola7bc59bc2006-05-14 22:18:28 +000029#include "llvm/Module.h"
Benjamin Kramere55b15f2009-12-28 12:27:56 +000030#include "llvm/Type.h"
Dan Gohmancf20ac42009-08-13 01:36:44 +000031#include "llvm/Assembly/Writer.h"
Chris Lattnerb0f294c2009-10-19 18:38:33 +000032#include "llvm/CodeGen/MachineModuleInfoImpls.h"
Rafael Espindola7bc59bc2006-05-14 22:18:28 +000033#include "llvm/CodeGen/MachineFunctionPass.h"
Evan Chenga8e29892007-01-19 07:51:42 +000034#include "llvm/CodeGen/MachineJumpTableInfo.h"
Chris Lattnerb0f294c2009-10-19 18:38:33 +000035#include "llvm/MC/MCAsmInfo.h"
Rafael Espindolacecbc3d2010-10-25 17:50:35 +000036#include "llvm/MC/MCAssembler.h"
Chris Lattnerb0f294c2009-10-19 18:38:33 +000037#include "llvm/MC/MCContext.h"
Bill Wendlingbecd83e2010-03-09 00:40:17 +000038#include "llvm/MC/MCExpr.h"
Chris Lattner97f06932009-10-19 20:20:46 +000039#include "llvm/MC/MCInst.h"
Chris Lattnerf9bdedd2009-08-10 18:15:01 +000040#include "llvm/MC/MCSectionMachO.h"
Rafael Espindolacecbc3d2010-10-25 17:50:35 +000041#include "llvm/MC/MCObjectStreamer.h"
Chris Lattner6c2f9e12009-08-19 05:49:37 +000042#include "llvm/MC/MCStreamer.h"
Chris Lattner325d3dc2009-09-13 17:14:04 +000043#include "llvm/MC/MCSymbol.h"
Chris Lattnerd62f1b42010-03-12 21:19:23 +000044#include "llvm/Target/Mangler.h"
Rafael Espindolab01c4bb2006-07-27 11:38:51 +000045#include "llvm/Target/TargetData.h"
Rafael Espindola7bc59bc2006-05-14 22:18:28 +000046#include "llvm/Target/TargetMachine.h"
Evan Cheng5be54b02007-01-19 19:25:36 +000047#include "llvm/Target/TargetOptions.h"
Daniel Dunbar51b198a2009-07-15 20:24:03 +000048#include "llvm/Target/TargetRegistry.h"
Evan Chengc324ecb2009-07-24 18:19:46 +000049#include "llvm/ADT/SmallPtrSet.h"
Jim Grosbachc40d9f92009-09-01 18:49:12 +000050#include "llvm/ADT/SmallString.h"
Bob Wilson54c78ef2009-11-06 23:33:28 +000051#include "llvm/ADT/StringExtras.h"
Chris Lattner97f06932009-10-19 20:20:46 +000052#include "llvm/Support/CommandLine.h"
Devang Patel59135f42010-08-04 22:39:39 +000053#include "llvm/Support/Debug.h"
Torok Edwin30464702009-07-08 20:55:50 +000054#include "llvm/Support/ErrorHandling.h"
Chris Lattnerb23569a2010-04-04 08:18:47 +000055#include "llvm/Support/raw_ostream.h"
Rafael Espindola7bc59bc2006-05-14 22:18:28 +000056#include <cctype>
Rafael Espindola7bc59bc2006-05-14 22:18:28 +000057using namespace llvm;
58
Chris Lattner95b2c7d2006-12-19 22:59:26 +000059namespace {
Rafael Espindolacecbc3d2010-10-25 17:50:35 +000060
61 // Per section and per symbol attributes are not supported.
62 // To implement them we would need the ability to delay this emission
63 // until the assembly file is fully parsed/generated as only then do we
64 // know the symbol and section numbers.
65 class AttributeEmitter {
66 public:
67 virtual void MaybeSwitchVendor(StringRef Vendor) = 0;
68 virtual void EmitAttribute(unsigned Attribute, unsigned Value) = 0;
Jason W Kimf009a962011-02-07 00:49:53 +000069 virtual void EmitTextAttribute(unsigned Attribute, StringRef String) = 0;
Rafael Espindolacecbc3d2010-10-25 17:50:35 +000070 virtual void Finish() = 0;
Rafael Espindola4921e232010-10-25 18:38:32 +000071 virtual ~AttributeEmitter() {}
Rafael Espindolacecbc3d2010-10-25 17:50:35 +000072 };
73
74 class AsmAttributeEmitter : public AttributeEmitter {
75 MCStreamer &Streamer;
76
77 public:
78 AsmAttributeEmitter(MCStreamer &Streamer_) : Streamer(Streamer_) {}
79 void MaybeSwitchVendor(StringRef Vendor) { }
80
81 void EmitAttribute(unsigned Attribute, unsigned Value) {
82 Streamer.EmitRawText("\t.eabi_attribute " +
83 Twine(Attribute) + ", " + Twine(Value));
84 }
85
Jason W Kimf009a962011-02-07 00:49:53 +000086 void EmitTextAttribute(unsigned Attribute, StringRef String) {
87 switch (Attribute) {
88 case ARMBuildAttrs::CPU_name:
Jason W Kimc046d642011-02-07 19:07:11 +000089 Streamer.EmitRawText(StringRef("\t.cpu ") + LowercaseString(String));
Jason W Kimf009a962011-02-07 00:49:53 +000090 break;
Renato Golin728ff0d2011-02-28 22:04:27 +000091 /* GAS requires .fpu to be emitted regardless of EABI attribute */
92 case ARMBuildAttrs::Advanced_SIMD_arch:
93 case ARMBuildAttrs::VFP_arch:
94 Streamer.EmitRawText(StringRef("\t.fpu ") + LowercaseString(String));
95 break;
Jason W Kimf009a962011-02-07 00:49:53 +000096 default: assert(0 && "Unsupported Text attribute in ASM Mode"); break;
97 }
98 }
Rafael Espindolacecbc3d2010-10-25 17:50:35 +000099 void Finish() { }
100 };
101
102 class ObjectAttributeEmitter : public AttributeEmitter {
103 MCObjectStreamer &Streamer;
Rafael Espindolacecbc3d2010-10-25 17:50:35 +0000104 StringRef CurrentVendor;
105 SmallString<64> Contents;
106
107 public:
108 ObjectAttributeEmitter(MCObjectStreamer &Streamer_) :
109 Streamer(Streamer_), CurrentVendor("") { }
110
111 void MaybeSwitchVendor(StringRef Vendor) {
112 assert(!Vendor.empty() && "Vendor cannot be empty.");
113
114 if (CurrentVendor.empty())
115 CurrentVendor = Vendor;
116 else if (CurrentVendor == Vendor)
117 return;
118 else
119 Finish();
120
121 CurrentVendor = Vendor;
122
Rafael Espindola33363842010-10-25 22:26:55 +0000123 assert(Contents.size() == 0);
Rafael Espindolacecbc3d2010-10-25 17:50:35 +0000124 }
125
126 void EmitAttribute(unsigned Attribute, unsigned Value) {
127 // FIXME: should be ULEB
128 Contents += Attribute;
129 Contents += Value;
130 }
131
Jason W Kimf009a962011-02-07 00:49:53 +0000132 void EmitTextAttribute(unsigned Attribute, StringRef String) {
133 Contents += Attribute;
Jason W Kimc046d642011-02-07 19:07:11 +0000134 Contents += UppercaseString(String);
Jason W Kimf009a962011-02-07 00:49:53 +0000135 Contents += 0;
136 }
137
Rafael Espindolacecbc3d2010-10-25 17:50:35 +0000138 void Finish() {
Rafael Espindola33363842010-10-25 22:26:55 +0000139 const size_t ContentsSize = Contents.size();
Rafael Espindolacecbc3d2010-10-25 17:50:35 +0000140
Rafael Espindola33363842010-10-25 22:26:55 +0000141 // Vendor size + Vendor name + '\0'
142 const size_t VendorHeaderSize = 4 + CurrentVendor.size() + 1;
Rafael Espindolacecbc3d2010-10-25 17:50:35 +0000143
Rafael Espindola33363842010-10-25 22:26:55 +0000144 // Tag + Tag Size
145 const size_t TagHeaderSize = 1 + 4;
146
147 Streamer.EmitIntValue(VendorHeaderSize + TagHeaderSize + ContentsSize, 4);
148 Streamer.EmitBytes(CurrentVendor, 0);
149 Streamer.EmitIntValue(0, 1); // '\0'
150
151 Streamer.EmitIntValue(ARMBuildAttrs::File, 1);
152 Streamer.EmitIntValue(TagHeaderSize + ContentsSize, 4);
Rafael Espindolacecbc3d2010-10-25 17:50:35 +0000153
154 Streamer.EmitBytes(Contents, 0);
Rafael Espindola33363842010-10-25 22:26:55 +0000155
156 Contents.clear();
Rafael Espindolacecbc3d2010-10-25 17:50:35 +0000157 }
158 };
159
Rafael Espindola7bc59bc2006-05-14 22:18:28 +0000160} // end of anonymous namespace
161
Jim Grosbachbaf120f2010-12-01 03:45:07 +0000162MachineLocation ARMAsmPrinter::
163getDebugValueLocation(const MachineInstr *MI) const {
164 MachineLocation Location;
165 assert(MI->getNumOperands() == 4 && "Invalid no. of machine operands!");
166 // Frame address. Currently handles register +- offset only.
167 if (MI->getOperand(0).isReg() && MI->getOperand(1).isImm())
168 Location.set(MI->getOperand(0).getReg(), MI->getOperand(1).getImm());
169 else {
170 DEBUG(dbgs() << "DBG_VALUE instruction ignored! " << *MI << "\n");
171 }
172 return Location;
173}
174
Devang Patelc26f5442011-04-28 02:22:40 +0000175/// getDwarfRegOpSize - get size required to emit given machine location using
176/// dwarf encoding.
177unsigned ARMAsmPrinter::getDwarfRegOpSize(const MachineLocation &MLoc) const {
178 const TargetRegisterInfo *RI = TM.getRegisterInfo();
179 if (RI->getDwarfRegNum(MLoc.getReg(), false) != -1)
180 return AsmPrinter::getDwarfRegOpSize(MLoc);
181 else {
182 unsigned Reg = MLoc.getReg();
183 if (Reg >= ARM::S0 && Reg <= ARM::S31) {
184 assert(ARM::S0 + 31 == ARM::S31 && "Unexpected ARM S register numbering");
185 // S registers are described as bit-pieces of a register
186 // S[2x] = DW_OP_regx(256 + (x>>1)) DW_OP_bit_piece(32, 0)
187 // S[2x+1] = DW_OP_regx(256 + (x>>1)) DW_OP_bit_piece(32, 32)
188
189 unsigned SReg = Reg - ARM::S0;
190 unsigned Rx = 256 + (SReg >> 1);
Devang Patelc26f5442011-04-28 02:22:40 +0000191 // DW_OP_regx + ULEB + DW_OP_bit_piece + ULEB + ULEB
192 // 1 + ULEB(Rx) + 1 + 1 + 1
193 return 4 + MCAsmInfo::getULEB128Size(Rx);
194 }
195
196 if (Reg >= ARM::Q0 && Reg <= ARM::Q15) {
197 assert(ARM::Q0 + 15 == ARM::Q15 && "Unexpected ARM Q register numbering");
198 // Q registers Q0-Q15 are described by composing two D registers together.
199 // Qx = DW_OP_regx(256+2x) DW_OP_piece(8) DW_OP_regx(256+2x+1) DW_OP_piece(8)
200
201 unsigned QReg = Reg - ARM::Q0;
202 unsigned D1 = 256 + 2 * QReg;
203 unsigned D2 = D1 + 1;
204
Devang Patelc26f5442011-04-28 02:22:40 +0000205 // DW_OP_regx + ULEB + DW_OP_piece + ULEB(8) +
206 // DW_OP_regx + ULEB + DW_OP_piece + ULEB(8);
207 // 6 + ULEB(D1) + ULEB(D2)
208 return 6 + MCAsmInfo::getULEB128Size(D1) + MCAsmInfo::getULEB128Size(D2);
209 }
210 }
211 return 0;
212}
213
Devang Patel27f5acb2011-04-21 22:48:26 +0000214/// EmitDwarfRegOp - Emit dwarf register operation.
Devang Patel0be77df2011-04-27 20:29:27 +0000215void ARMAsmPrinter::EmitDwarfRegOp(const MachineLocation &MLoc) const {
Devang Patel27f5acb2011-04-21 22:48:26 +0000216 const TargetRegisterInfo *RI = TM.getRegisterInfo();
217 if (RI->getDwarfRegNum(MLoc.getReg(), false) != -1)
Devang Patel0be77df2011-04-27 20:29:27 +0000218 AsmPrinter::EmitDwarfRegOp(MLoc);
Devang Patel27f5acb2011-04-21 22:48:26 +0000219 else {
220 unsigned Reg = MLoc.getReg();
221 if (Reg >= ARM::S0 && Reg <= ARM::S31) {
Devang Patel0a6ea832011-04-22 16:44:29 +0000222 assert(ARM::S0 + 31 == ARM::S31 && "Unexpected ARM S register numbering");
Devang Patel27f5acb2011-04-21 22:48:26 +0000223 // S registers are described as bit-pieces of a register
224 // S[2x] = DW_OP_regx(256 + (x>>1)) DW_OP_bit_piece(32, 0)
225 // S[2x+1] = DW_OP_regx(256 + (x>>1)) DW_OP_bit_piece(32, 32)
226
227 unsigned SReg = Reg - ARM::S0;
228 bool odd = SReg & 0x1;
229 unsigned Rx = 256 + (SReg >> 1);
Devang Patel27f5acb2011-04-21 22:48:26 +0000230
231 OutStreamer.AddComment("DW_OP_regx for S register");
232 EmitInt8(dwarf::DW_OP_regx);
233
234 OutStreamer.AddComment(Twine(SReg));
235 EmitULEB128(Rx);
236
237 if (odd) {
238 OutStreamer.AddComment("DW_OP_bit_piece 32 32");
239 EmitInt8(dwarf::DW_OP_bit_piece);
240 EmitULEB128(32);
241 EmitULEB128(32);
242 } else {
243 OutStreamer.AddComment("DW_OP_bit_piece 32 0");
244 EmitInt8(dwarf::DW_OP_bit_piece);
245 EmitULEB128(32);
246 EmitULEB128(0);
247 }
Devang Patel71f3f112011-04-21 23:22:35 +0000248 } else if (Reg >= ARM::Q0 && Reg <= ARM::Q15) {
Devang Patel0a6ea832011-04-22 16:44:29 +0000249 assert(ARM::Q0 + 15 == ARM::Q15 && "Unexpected ARM Q register numbering");
Devang Patel71f3f112011-04-21 23:22:35 +0000250 // Q registers Q0-Q15 are described by composing two D registers together.
251 // Qx = DW_OP_regx(256+2x) DW_OP_piece(8) DW_OP_regx(256+2x+1) DW_OP_piece(8)
252
253 unsigned QReg = Reg - ARM::Q0;
254 unsigned D1 = 256 + 2 * QReg;
255 unsigned D2 = D1 + 1;
256
Devang Patel71f3f112011-04-21 23:22:35 +0000257 OutStreamer.AddComment("DW_OP_regx for Q register: D1");
258 EmitInt8(dwarf::DW_OP_regx);
259 EmitULEB128(D1);
260 OutStreamer.AddComment("DW_OP_piece 8");
261 EmitInt8(dwarf::DW_OP_piece);
262 EmitULEB128(8);
263
264 OutStreamer.AddComment("DW_OP_regx for Q register: D2");
265 EmitInt8(dwarf::DW_OP_regx);
266 EmitULEB128(D2);
267 OutStreamer.AddComment("DW_OP_piece 8");
268 EmitInt8(dwarf::DW_OP_piece);
269 EmitULEB128(8);
Devang Patel27f5acb2011-04-21 22:48:26 +0000270 }
271 }
272}
273
Chris Lattner953ebb72010-01-27 23:58:11 +0000274void ARMAsmPrinter::EmitFunctionEntryLabel() {
275 if (AFI->isThumbFunction()) {
Jim Grosbachce792992010-11-05 22:08:08 +0000276 OutStreamer.EmitAssemblerFlag(MCAF_Code16);
Rafael Espindola64695402011-05-16 16:17:21 +0000277 OutStreamer.EmitThumbFunc(CurrentFnSym);
Chris Lattner953ebb72010-01-27 23:58:11 +0000278 }
Jim Grosbachb0739b72010-09-02 01:02:06 +0000279
Chris Lattner953ebb72010-01-27 23:58:11 +0000280 OutStreamer.EmitLabel(CurrentFnSym);
281}
282
Jim Grosbach2317e402010-09-30 01:57:53 +0000283/// runOnMachineFunction - This uses the EmitInstruction()
Rafael Espindola7bc59bc2006-05-14 22:18:28 +0000284/// method to print assembly for each instruction.
285///
286bool ARMAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
Evan Chenga8e29892007-01-19 07:51:42 +0000287 AFI = MF.getInfo<ARMFunctionInfo>();
Evan Cheng6d63a722008-09-18 07:27:23 +0000288 MCP = MF.getConstantPool();
Rafael Espindola4b442b52006-05-23 02:48:20 +0000289
Chris Lattnerd49fe1b2010-01-28 01:28:58 +0000290 return AsmPrinter::runOnMachineFunction(MF);
Rafael Espindola7bc59bc2006-05-14 22:18:28 +0000291}
292
Evan Cheng055b0312009-06-29 07:51:04 +0000293void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
Chris Lattner35c33bd2010-04-04 04:47:45 +0000294 raw_ostream &O, const char *Modifier) {
Evan Cheng055b0312009-06-29 07:51:04 +0000295 const MachineOperand &MO = MI->getOperand(OpNum);
Anton Korobeynikov5cdc3a92009-11-24 00:44:37 +0000296 unsigned TF = MO.getTargetFlags();
297
Rafael Espindola2f99b6b2006-05-25 12:57:06 +0000298 switch (MO.getType()) {
Chris Lattner8bc86cb2009-10-19 20:59:55 +0000299 default:
300 assert(0 && "<unknown operand type>");
Bob Wilson5bafff32009-06-22 23:27:02 +0000301 case MachineOperand::MO_Register: {
302 unsigned Reg = MO.getReg();
Chris Lattner8bc86cb2009-10-19 20:59:55 +0000303 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
Jim Grosbach35636282010-10-06 21:22:32 +0000304 assert(!MO.getSubReg() && "Subregs should be eliminated!");
305 O << ARMInstPrinter::getRegisterName(Reg);
Rafael Espindola2f99b6b2006-05-25 12:57:06 +0000306 break;
Bob Wilson5bafff32009-06-22 23:27:02 +0000307 }
Evan Chenga8e29892007-01-19 07:51:42 +0000308 case MachineOperand::MO_Immediate: {
Evan Cheng5adb66a2009-09-28 09:14:39 +0000309 int64_t Imm = MO.getImm();
Anton Korobeynikov632606c2009-10-08 20:43:22 +0000310 O << '#';
Anton Korobeynikov5cdc3a92009-11-24 00:44:37 +0000311 if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
Jason W Kim650b7d72011-01-12 23:21:49 +0000312 (TF == ARMII::MO_LO16))
Anton Korobeynikov5cdc3a92009-11-24 00:44:37 +0000313 O << ":lower16:";
314 else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
Jason W Kim650b7d72011-01-12 23:21:49 +0000315 (TF == ARMII::MO_HI16))
Anton Korobeynikov5cdc3a92009-11-24 00:44:37 +0000316 O << ":upper16:";
Anton Korobeynikov632606c2009-10-08 20:43:22 +0000317 O << Imm;
Rafael Espindola2f99b6b2006-05-25 12:57:06 +0000318 break;
Evan Chenga8e29892007-01-19 07:51:42 +0000319 }
Rafael Espindola2f99b6b2006-05-25 12:57:06 +0000320 case MachineOperand::MO_MachineBasicBlock:
Chris Lattner1b2eb0e2010-03-13 21:04:28 +0000321 O << *MO.getMBB()->getSymbol();
Rafael Espindola2f99b6b2006-05-25 12:57:06 +0000322 return;
Rafael Espindola84b19be2006-07-16 01:02:57 +0000323 case MachineOperand::MO_GlobalAddress: {
Dan Gohman46510a72010-04-15 01:51:59 +0000324 const GlobalValue *GV = MO.getGlobal();
Anton Korobeynikov5cdc3a92009-11-24 00:44:37 +0000325 if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
326 (TF & ARMII::MO_LO16))
327 O << ":lower16:";
328 else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
329 (TF & ARMII::MO_HI16))
330 O << ":upper16:";
Chris Lattnerd62f1b42010-03-12 21:19:23 +0000331 O << *Mang->getSymbol(GV);
Anton Korobeynikov7751ad92008-11-22 16:15:34 +0000332
Chris Lattner0c08d092010-04-03 22:28:33 +0000333 printOffset(MO.getOffset(), O);
Jim Grosbach1d6111c2010-10-06 21:36:43 +0000334 if (TF == ARMII::MO_PLT)
Lauro Ramos Venancio0ae4a332007-04-22 00:04:12 +0000335 O << "(PLT)";
Evan Chenga8e29892007-01-19 07:51:42 +0000336 break;
Rafael Espindola84b19be2006-07-16 01:02:57 +0000337 }
Evan Chenga8e29892007-01-19 07:51:42 +0000338 case MachineOperand::MO_ExternalSymbol: {
Chris Lattner10b318b2010-01-17 21:43:43 +0000339 O << *GetExternalSymbolSymbol(MO.getSymbolName());
Jim Grosbach1d6111c2010-10-06 21:36:43 +0000340 if (TF == ARMII::MO_PLT)
Lauro Ramos Venancio0ae4a332007-04-22 00:04:12 +0000341 O << "(PLT)";
Rafael Espindola2f99b6b2006-05-25 12:57:06 +0000342 break;
Evan Chenga8e29892007-01-19 07:51:42 +0000343 }
Rafael Espindola2f99b6b2006-05-25 12:57:06 +0000344 case MachineOperand::MO_ConstantPoolIndex:
Chris Lattner1b46f432010-01-23 07:00:21 +0000345 O << *GetCPISymbol(MO.getIndex());
Rafael Espindola2f99b6b2006-05-25 12:57:06 +0000346 break;
Evan Chenga8e29892007-01-19 07:51:42 +0000347 case MachineOperand::MO_JumpTableIndex:
Chris Lattner1b46f432010-01-23 07:00:21 +0000348 O << *GetJTISymbol(MO.getIndex());
Evan Chenga8e29892007-01-19 07:51:42 +0000349 break;
Rafael Espindola2f99b6b2006-05-25 12:57:06 +0000350 }
Rafael Espindola7bc59bc2006-05-14 22:18:28 +0000351}
352
Evan Cheng055b0312009-06-29 07:51:04 +0000353//===--------------------------------------------------------------------===//
354
Chris Lattner0890cf12010-01-25 19:51:38 +0000355MCSymbol *ARMAsmPrinter::
356GetARMSetPICJumpTableLabel2(unsigned uid, unsigned uid2,
357 const MachineBasicBlock *MBB) const {
358 SmallString<60> Name;
359 raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix()
Chris Lattnerbfcb0962010-01-25 19:39:52 +0000360 << getFunctionNumber() << '_' << uid << '_' << uid2
Chris Lattner0890cf12010-01-25 19:51:38 +0000361 << "_set_" << MBB->getNumber();
Chris Lattner9b97a732010-03-30 18:10:53 +0000362 return OutContext.GetOrCreateSymbol(Name.str());
Chris Lattner0890cf12010-01-25 19:51:38 +0000363}
364
365MCSymbol *ARMAsmPrinter::
366GetARMJTIPICJumpTableLabel2(unsigned uid, unsigned uid2) const {
367 SmallString<60> Name;
368 raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix() << "JTI"
Chris Lattner281e7762010-01-25 23:28:03 +0000369 << getFunctionNumber() << '_' << uid << '_' << uid2;
Chris Lattner9b97a732010-03-30 18:10:53 +0000370 return OutContext.GetOrCreateSymbol(Name.str());
Chris Lattnerbfcb0962010-01-25 19:39:52 +0000371}
372
Jim Grosbach433a5782010-09-24 20:47:58 +0000373
374MCSymbol *ARMAsmPrinter::GetARMSJLJEHLabel(void) const {
375 SmallString<60> Name;
376 raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix() << "SJLJEH"
377 << getFunctionNumber();
378 return OutContext.GetOrCreateSymbol(Name.str());
379}
380
Evan Cheng055b0312009-06-29 07:51:04 +0000381bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
Chris Lattnerc75c0282010-04-04 05:29:35 +0000382 unsigned AsmVariant, const char *ExtraCode,
383 raw_ostream &O) {
Evan Chenga8e29892007-01-19 07:51:42 +0000384 // Does this asm operand have a single letter operand modifier?
385 if (ExtraCode && ExtraCode[0]) {
386 if (ExtraCode[1] != 0) return true; // Unknown modifier.
Anton Korobeynikov8e9ece72009-08-08 23:10:41 +0000387
Evan Chenga8e29892007-01-19 07:51:42 +0000388 switch (ExtraCode[0]) {
389 default: return true; // Unknown modifier.
Bob Wilson9b4b00a2009-07-09 23:54:51 +0000390 case 'a': // Print as a memory address.
391 if (MI->getOperand(OpNum).isReg()) {
Jim Grosbach2f24c4e2010-09-30 15:25:22 +0000392 O << "["
393 << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg())
394 << "]";
Bob Wilson9b4b00a2009-07-09 23:54:51 +0000395 return false;
396 }
397 // Fallthrough
398 case 'c': // Don't print "#" before an immediate operand.
Bob Wilson4f38b382009-08-21 21:58:55 +0000399 if (!MI->getOperand(OpNum).isImm())
400 return true;
Jim Grosbach2317e402010-09-30 01:57:53 +0000401 O << MI->getOperand(OpNum).getImm();
Bob Wilson8f343462009-04-06 21:46:51 +0000402 return false;
Evan Chenge21e3962007-04-04 00:13:29 +0000403 case 'P': // Print a VFP double precision register.
Evan Chengd831cda2009-12-08 23:06:22 +0000404 case 'q': // Print a NEON quad precision register.
Chris Lattner35c33bd2010-04-04 04:47:45 +0000405 printOperand(MI, OpNum, O);
Evan Cheng23a95702007-03-08 22:42:46 +0000406 return false;
Evan Chenga8e29892007-01-19 07:51:42 +0000407 case 'Q':
Bob Wilsond984eb62010-05-27 20:23:42 +0000408 case 'R':
Bob Wilsond984eb62010-05-27 20:23:42 +0000409 case 'H':
Bob Wilson9bb43e12010-12-17 23:06:42 +0000410 // These modifiers are not yet supported.
Bob Wilsond984eb62010-05-27 20:23:42 +0000411 return true;
Evan Cheng84f60b72010-05-27 22:08:38 +0000412 }
Evan Chenga8e29892007-01-19 07:51:42 +0000413 }
Jim Grosbache9952212009-09-04 01:38:51 +0000414
Chris Lattner35c33bd2010-04-04 04:47:45 +0000415 printOperand(MI, OpNum, O);
Evan Chenga8e29892007-01-19 07:51:42 +0000416 return false;
417}
418
Bob Wilson224c2442009-05-19 05:53:42 +0000419bool ARMAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
Evan Cheng055b0312009-06-29 07:51:04 +0000420 unsigned OpNum, unsigned AsmVariant,
Chris Lattnerc75c0282010-04-04 05:29:35 +0000421 const char *ExtraCode,
422 raw_ostream &O) {
Bob Wilson224c2442009-05-19 05:53:42 +0000423 if (ExtraCode && ExtraCode[0])
424 return true; // Unknown modifier.
Bob Wilson765cc0b2009-10-13 20:50:28 +0000425
426 const MachineOperand &MO = MI->getOperand(OpNum);
427 assert(MO.isReg() && "unexpected inline asm memory operand");
Jim Grosbach2317e402010-09-30 01:57:53 +0000428 O << "[" << ARMInstPrinter::getRegisterName(MO.getReg()) << "]";
Bob Wilson224c2442009-05-19 05:53:42 +0000429 return false;
430}
431
Bob Wilson812209a2009-09-30 22:06:26 +0000432void ARMAsmPrinter::EmitStartOfAsmFile(Module &M) {
Bob Wilson0fb34682009-09-30 00:23:42 +0000433 if (Subtarget->isTargetDarwin()) {
434 Reloc::Model RelocM = TM.getRelocationModel();
435 if (RelocM == Reloc::PIC_ || RelocM == Reloc::DynamicNoPIC) {
436 // Declare all the text sections up front (before the DWARF sections
437 // emitted by AsmPrinter::doInitialization) so the assembler will keep
438 // them together at the beginning of the object file. This helps
439 // avoid out-of-range branches that are due a fundamental limitation of
440 // the way symbol offsets are encoded with the current Darwin ARM
441 // relocations.
Jim Grosbachb0739b72010-09-02 01:02:06 +0000442 const TargetLoweringObjectFileMachO &TLOFMacho =
Dan Gohman0d805c32010-04-17 16:44:48 +0000443 static_cast<const TargetLoweringObjectFileMachO &>(
444 getObjFileLowering());
Bob Wilson29e06692009-09-30 22:25:37 +0000445 OutStreamer.SwitchSection(TLOFMacho.getTextSection());
446 OutStreamer.SwitchSection(TLOFMacho.getTextCoalSection());
447 OutStreamer.SwitchSection(TLOFMacho.getConstTextCoalSection());
448 if (RelocM == Reloc::DynamicNoPIC) {
449 const MCSection *sect =
Chris Lattner22772212010-04-08 20:40:11 +0000450 OutContext.getMachOSection("__TEXT", "__symbol_stub4",
451 MCSectionMachO::S_SYMBOL_STUBS,
452 12, SectionKind::getText());
Bob Wilson29e06692009-09-30 22:25:37 +0000453 OutStreamer.SwitchSection(sect);
454 } else {
455 const MCSection *sect =
Chris Lattner22772212010-04-08 20:40:11 +0000456 OutContext.getMachOSection("__TEXT", "__picsymbolstub4",
457 MCSectionMachO::S_SYMBOL_STUBS,
458 16, SectionKind::getText());
Bob Wilson29e06692009-09-30 22:25:37 +0000459 OutStreamer.SwitchSection(sect);
460 }
Bob Wilson63db5942010-07-30 19:55:47 +0000461 const MCSection *StaticInitSect =
462 OutContext.getMachOSection("__TEXT", "__StaticInit",
463 MCSectionMachO::S_REGULAR |
464 MCSectionMachO::S_ATTR_PURE_INSTRUCTIONS,
465 SectionKind::getText());
466 OutStreamer.SwitchSection(StaticInitSect);
Bob Wilson0fb34682009-09-30 00:23:42 +0000467 }
468 }
469
Jim Grosbache5165492009-11-09 00:11:35 +0000470 // Use unified assembler syntax.
Jason W Kimafd1cc22010-09-30 02:45:56 +0000471 OutStreamer.EmitAssemblerFlag(MCAF_SyntaxUnified);
Anton Korobeynikovd61eca52009-06-17 23:43:18 +0000472
Anton Korobeynikov88ce6672009-05-23 19:51:20 +0000473 // Emit ARM Build Attributes
474 if (Subtarget->isTargetELF()) {
Anton Korobeynikov88ce6672009-05-23 19:51:20 +0000475
Jason W Kimdef9ac42010-10-06 22:36:46 +0000476 emitAttributes();
Anton Korobeynikov88ce6672009-05-23 19:51:20 +0000477 }
Rafael Espindola7bc59bc2006-05-14 22:18:28 +0000478}
479
Anton Korobeynikov0f3cc652008-08-07 09:54:23 +0000480
Chris Lattner4a071d62009-10-19 17:59:19 +0000481void ARMAsmPrinter::EmitEndOfAsmFile(Module &M) {
Evan Cheng5be54b02007-01-19 19:25:36 +0000482 if (Subtarget->isTargetDarwin()) {
Chris Lattnerf61159b2009-08-03 22:18:15 +0000483 // All darwin targets use mach-o.
Dan Gohman0d805c32010-04-17 16:44:48 +0000484 const TargetLoweringObjectFileMachO &TLOFMacho =
485 static_cast<const TargetLoweringObjectFileMachO &>(getObjFileLowering());
Chris Lattnerb0f294c2009-10-19 18:38:33 +0000486 MachineModuleInfoMachO &MMIMacho =
487 MMI->getObjFileInfo<MachineModuleInfoMachO>();
Jim Grosbache9952212009-09-04 01:38:51 +0000488
Evan Chenga8e29892007-01-19 07:51:42 +0000489 // Output non-lazy-pointers for external and common global variables.
Chris Lattnerb0f294c2009-10-19 18:38:33 +0000490 MachineModuleInfoMachO::SymbolListTy Stubs = MMIMacho.GetGVStubList();
Bill Wendlingcebae362010-03-10 22:34:10 +0000491
Chris Lattnerb0f294c2009-10-19 18:38:33 +0000492 if (!Stubs.empty()) {
Chris Lattnerff4bc462009-08-10 01:39:42 +0000493 // Switch with ".non_lazy_symbol_pointer" directive.
Chris Lattner6c2f9e12009-08-19 05:49:37 +0000494 OutStreamer.SwitchSection(TLOFMacho.getNonLazySymbolPointerSection());
Chris Lattnerc076a972009-08-10 18:01:34 +0000495 EmitAlignment(2);
Chris Lattnerb0f294c2009-10-19 18:38:33 +0000496 for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
Bill Wendlingbecd83e2010-03-09 00:40:17 +0000497 // L_foo$stub:
498 OutStreamer.EmitLabel(Stubs[i].first);
499 // .indirect_symbol _foo
Bill Wendling52a50e52010-03-11 01:18:13 +0000500 MachineModuleInfoImpl::StubValueTy &MCSym = Stubs[i].second;
501 OutStreamer.EmitSymbolAttribute(MCSym.getPointer(),MCSA_IndirectSymbol);
Bill Wendlingcf6f28d2010-03-09 00:43:34 +0000502
Bill Wendling52a50e52010-03-11 01:18:13 +0000503 if (MCSym.getInt())
Bill Wendlingcf6f28d2010-03-09 00:43:34 +0000504 // External to current translation unit.
505 OutStreamer.EmitIntValue(0, 4/*size*/, 0/*addrspace*/);
506 else
507 // Internal to current translation unit.
Bill Wendling5e1b55d2010-03-31 18:47:10 +0000508 //
Jim Grosbach1b935a32010-09-22 16:45:13 +0000509 // When we place the LSDA into the TEXT section, the type info
510 // pointers need to be indirect and pc-rel. We accomplish this by
511 // using NLPs; however, sometimes the types are local to the file.
512 // We need to fill in the value for the NLP in those cases.
Bill Wendling52a50e52010-03-11 01:18:13 +0000513 OutStreamer.EmitValue(MCSymbolRefExpr::Create(MCSym.getPointer(),
514 OutContext),
Bill Wendlingcf6f28d2010-03-09 00:43:34 +0000515 4/*size*/, 0/*addrspace*/);
Evan Chengae94e592008-12-05 01:06:39 +0000516 }
Bill Wendlingbecd83e2010-03-09 00:40:17 +0000517
518 Stubs.clear();
519 OutStreamer.AddBlankLine();
Evan Chenga8e29892007-01-19 07:51:42 +0000520 }
521
Chris Lattnere4d9ea82009-10-19 18:44:38 +0000522 Stubs = MMIMacho.GetHiddenGVStubList();
523 if (!Stubs.empty()) {
Chris Lattner6c2f9e12009-08-19 05:49:37 +0000524 OutStreamer.SwitchSection(getObjFileLowering().getDataSection());
Chris Lattnerf3231de2009-08-10 18:02:16 +0000525 EmitAlignment(2);
Bill Wendlingbecd83e2010-03-09 00:40:17 +0000526 for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
527 // L_foo$stub:
528 OutStreamer.EmitLabel(Stubs[i].first);
529 // .long _foo
Bill Wendlingcebae362010-03-10 22:34:10 +0000530 OutStreamer.EmitValue(MCSymbolRefExpr::
531 Create(Stubs[i].second.getPointer(),
532 OutContext),
Bill Wendlingbecd83e2010-03-09 00:40:17 +0000533 4/*size*/, 0/*addrspace*/);
534 }
Bill Wendlingcf6f28d2010-03-09 00:43:34 +0000535
536 Stubs.clear();
537 OutStreamer.AddBlankLine();
Evan Chengae94e592008-12-05 01:06:39 +0000538 }
539
Evan Chenga8e29892007-01-19 07:51:42 +0000540 // Funny Darwin hack: This flag tells the linker that no global symbols
541 // contain code that falls through to other global symbols (e.g. the obvious
542 // implementation of multiple entry points). If this doesn't occur, the
543 // linker can safely perform dead code stripping. Since LLVM never
544 // generates code that does this, it is always safe to set.
Chris Lattnera5ad93a2010-01-23 06:39:22 +0000545 OutStreamer.EmitAssemblerFlag(MCAF_SubsectionsViaSymbols);
Rafael Espindolab01c4bb2006-07-27 11:38:51 +0000546 }
Rafael Espindola7bc59bc2006-05-14 22:18:28 +0000547}
Anton Korobeynikov0bd89712008-08-17 13:55:10 +0000548
Chris Lattner97f06932009-10-19 20:20:46 +0000549//===----------------------------------------------------------------------===//
Jason W Kimdef9ac42010-10-06 22:36:46 +0000550// Helper routines for EmitStartOfAsmFile() and EmitEndOfAsmFile()
551// FIXME:
552// The following seem like one-off assembler flags, but they actually need
Jim Grosbachfa7fb642010-10-06 22:46:47 +0000553// to appear in the .ARM.attributes section in ELF.
Jason W Kimdef9ac42010-10-06 22:36:46 +0000554// Instead of subclassing the MCELFStreamer, we do the work here.
555
556void ARMAsmPrinter::emitAttributes() {
Jim Grosbachfa7fb642010-10-06 22:46:47 +0000557
Jason W Kim17b443d2010-10-11 23:01:44 +0000558 emitARMAttributeSection();
559
Renato Golin728ff0d2011-02-28 22:04:27 +0000560 /* GAS expect .fpu to be emitted, regardless of VFP build attribute */
561 bool emitFPU = false;
Rafael Espindolacecbc3d2010-10-25 17:50:35 +0000562 AttributeEmitter *AttrEmitter;
Renato Golin728ff0d2011-02-28 22:04:27 +0000563 if (OutStreamer.hasRawTextSupport()) {
Rafael Espindolacecbc3d2010-10-25 17:50:35 +0000564 AttrEmitter = new AsmAttributeEmitter(OutStreamer);
Renato Golin728ff0d2011-02-28 22:04:27 +0000565 emitFPU = true;
566 } else {
Rafael Espindolacecbc3d2010-10-25 17:50:35 +0000567 MCObjectStreamer &O = static_cast<MCObjectStreamer&>(OutStreamer);
568 AttrEmitter = new ObjectAttributeEmitter(O);
569 }
570
571 AttrEmitter->MaybeSwitchVendor("aeabi");
572
Jason W Kimdef9ac42010-10-06 22:36:46 +0000573 std::string CPUString = Subtarget->getCPUString();
Jason W Kimf009a962011-02-07 00:49:53 +0000574
575 if (CPUString == "cortex-a8" ||
576 Subtarget->isCortexA8()) {
Jason W Kimc046d642011-02-07 19:07:11 +0000577 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::CPU_name, "cortex-a8");
Jason W Kimf009a962011-02-07 00:49:53 +0000578 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v7);
579 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch_profile,
580 ARMBuildAttrs::ApplicationProfile);
581 AttrEmitter->EmitAttribute(ARMBuildAttrs::ARM_ISA_use,
582 ARMBuildAttrs::Allowed);
583 AttrEmitter->EmitAttribute(ARMBuildAttrs::THUMB_ISA_use,
584 ARMBuildAttrs::AllowThumb32);
585 // Fixme: figure out when this is emitted.
586 //AttrEmitter->EmitAttribute(ARMBuildAttrs::WMMX_arch,
587 // ARMBuildAttrs::AllowWMMXv1);
588 //
589
590 /// ADD additional Else-cases here!
Rafael Espindolab8adb8a2011-05-20 20:10:34 +0000591 } else if (CPUString == "xscale") {
592 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v5TEJ);
593 AttrEmitter->EmitAttribute(ARMBuildAttrs::ARM_ISA_use,
594 ARMBuildAttrs::Allowed);
595 AttrEmitter->EmitAttribute(ARMBuildAttrs::THUMB_ISA_use,
596 ARMBuildAttrs::Allowed);
Jason W Kimf009a962011-02-07 00:49:53 +0000597 } else if (CPUString == "generic") {
Dale Johannesen7179d1e2010-11-08 19:17:22 +0000598 // FIXME: Why these defaults?
599 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v4T);
Jason W Kimf009a962011-02-07 00:49:53 +0000600 AttrEmitter->EmitAttribute(ARMBuildAttrs::ARM_ISA_use,
601 ARMBuildAttrs::Allowed);
602 AttrEmitter->EmitAttribute(ARMBuildAttrs::THUMB_ISA_use,
603 ARMBuildAttrs::Allowed);
Rafael Espindolacecbc3d2010-10-25 17:50:35 +0000604 }
Jason W Kimdef9ac42010-10-06 22:36:46 +0000605
Renato Goline89a0532011-03-02 21:20:09 +0000606 if (Subtarget->hasNEON() && emitFPU) {
Renato Golin728ff0d2011-02-28 22:04:27 +0000607 /* NEON is not exactly a VFP architecture, but GAS emit one of
608 * neon/vfpv3/vfpv2 for .fpu parameters */
609 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::Advanced_SIMD_arch, "neon");
610 /* If emitted for NEON, omit from VFP below, since you can have both
611 * NEON and VFP in build attributes but only one .fpu */
612 emitFPU = false;
613 }
614
615 /* VFPv3 + .fpu */
616 if (Subtarget->hasVFP3()) {
617 AttrEmitter->EmitAttribute(ARMBuildAttrs::VFP_arch,
618 ARMBuildAttrs::AllowFPv3A);
619 if (emitFPU)
620 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::VFP_arch, "vfpv3");
621
622 /* VFPv2 + .fpu */
623 } else if (Subtarget->hasVFP2()) {
Jason W Kimf009a962011-02-07 00:49:53 +0000624 AttrEmitter->EmitAttribute(ARMBuildAttrs::VFP_arch,
625 ARMBuildAttrs::AllowFPv2);
Renato Golin728ff0d2011-02-28 22:04:27 +0000626 if (emitFPU)
627 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::VFP_arch, "vfpv2");
628 }
629
630 /* TODO: ARMBuildAttrs::Allowed is not completely accurate,
631 * since NEON can have 1 (allowed) or 2 (fused MAC operations) */
632 if (Subtarget->hasNEON()) {
633 AttrEmitter->EmitAttribute(ARMBuildAttrs::Advanced_SIMD_arch,
634 ARMBuildAttrs::Allowed);
635 }
Jason W Kimdef9ac42010-10-06 22:36:46 +0000636
637 // Signal various FP modes.
638 if (!UnsafeFPMath) {
Jason W Kimf009a962011-02-07 00:49:53 +0000639 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_denormal,
640 ARMBuildAttrs::Allowed);
641 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_exceptions,
642 ARMBuildAttrs::Allowed);
Jason W Kimdef9ac42010-10-06 22:36:46 +0000643 }
644
645 if (NoInfsFPMath && NoNaNsFPMath)
Jason W Kimf009a962011-02-07 00:49:53 +0000646 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_number_model,
647 ARMBuildAttrs::Allowed);
Jason W Kimdef9ac42010-10-06 22:36:46 +0000648 else
Jason W Kimf009a962011-02-07 00:49:53 +0000649 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_number_model,
650 ARMBuildAttrs::AllowIEE754);
Jason W Kimdef9ac42010-10-06 22:36:46 +0000651
Jason W Kimf009a962011-02-07 00:49:53 +0000652 // FIXME: add more flags to ARMBuildAttrs.h
Jason W Kimdef9ac42010-10-06 22:36:46 +0000653 // 8-bytes alignment stuff.
Rafael Espindolacecbc3d2010-10-25 17:50:35 +0000654 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_align8_needed, 1);
655 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_align8_preserved, 1);
Jason W Kimdef9ac42010-10-06 22:36:46 +0000656
657 // Hard float. Use both S and D registers and conform to AAPCS-VFP.
658 if (Subtarget->isAAPCS_ABI() && FloatABIType == FloatABI::Hard) {
Rafael Espindolacecbc3d2010-10-25 17:50:35 +0000659 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_HardFP_use, 3);
660 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_VFP_args, 1);
Jason W Kimdef9ac42010-10-06 22:36:46 +0000661 }
662 // FIXME: Should we signal R9 usage?
Rafael Espindolacecbc3d2010-10-25 17:50:35 +0000663
Jason W Kimf009a962011-02-07 00:49:53 +0000664 if (Subtarget->hasDivide())
665 AttrEmitter->EmitAttribute(ARMBuildAttrs::DIV_use, 1);
Rafael Espindolacecbc3d2010-10-25 17:50:35 +0000666
667 AttrEmitter->Finish();
668 delete AttrEmitter;
Jason W Kimdef9ac42010-10-06 22:36:46 +0000669}
670
Jason W Kim17b443d2010-10-11 23:01:44 +0000671void ARMAsmPrinter::emitARMAttributeSection() {
672 // <format-version>
673 // [ <section-length> "vendor-name"
674 // [ <file-tag> <size> <attribute>*
675 // | <section-tag> <size> <section-number>* 0 <attribute>*
676 // | <symbol-tag> <size> <symbol-number>* 0 <attribute>*
677 // ]+
678 // ]*
679
680 if (OutStreamer.hasRawTextSupport())
681 return;
682
683 const ARMElfTargetObjectFile &TLOFELF =
684 static_cast<const ARMElfTargetObjectFile &>
685 (getObjFileLowering());
686
687 OutStreamer.SwitchSection(TLOFELF.getAttributesSection());
Jason W Kim17b443d2010-10-11 23:01:44 +0000688
Rafael Espindolacecbc3d2010-10-25 17:50:35 +0000689 // Format version
690 OutStreamer.EmitIntValue(0x41, 1);
Jason W Kim17b443d2010-10-11 23:01:44 +0000691}
692
Jason W Kimdef9ac42010-10-06 22:36:46 +0000693//===----------------------------------------------------------------------===//
Chris Lattner97f06932009-10-19 20:20:46 +0000694
Jim Grosbach988ce092010-09-18 00:05:05 +0000695static MCSymbol *getPICLabel(const char *Prefix, unsigned FunctionNumber,
696 unsigned LabelId, MCContext &Ctx) {
697
698 MCSymbol *Label = Ctx.GetOrCreateSymbol(Twine(Prefix)
699 + "PC" + Twine(FunctionNumber) + "_" + Twine(LabelId));
700 return Label;
701}
702
Jim Grosbach2c4d5122010-11-10 03:26:07 +0000703static MCSymbolRefExpr::VariantKind
704getModifierVariantKind(ARMCP::ARMCPModifier Modifier) {
705 switch (Modifier) {
706 default: llvm_unreachable("Unknown modifier!");
707 case ARMCP::no_modifier: return MCSymbolRefExpr::VK_None;
708 case ARMCP::TLSGD: return MCSymbolRefExpr::VK_ARM_TLSGD;
709 case ARMCP::TPOFF: return MCSymbolRefExpr::VK_ARM_TPOFF;
710 case ARMCP::GOTTPOFF: return MCSymbolRefExpr::VK_ARM_GOTTPOFF;
711 case ARMCP::GOT: return MCSymbolRefExpr::VK_ARM_GOT;
712 case ARMCP::GOTOFF: return MCSymbolRefExpr::VK_ARM_GOTOFF;
713 }
714 return MCSymbolRefExpr::VK_None;
715}
716
Evan Cheng5de5d4b2011-01-17 08:03:18 +0000717MCSymbol *ARMAsmPrinter::GetARMGVSymbol(const GlobalValue *GV) {
718 bool isIndirect = Subtarget->isTargetDarwin() &&
719 Subtarget->GVIsIndirectSymbol(GV, TM.getRelocationModel());
720 if (!isIndirect)
721 return Mang->getSymbol(GV);
722
723 // FIXME: Remove this when Darwin transition to @GOT like syntax.
724 MCSymbol *MCSym = GetSymbolWithGlobalValueBase(GV, "$non_lazy_ptr");
725 MachineModuleInfoMachO &MMIMachO =
726 MMI->getObjFileInfo<MachineModuleInfoMachO>();
727 MachineModuleInfoImpl::StubValueTy &StubSym =
728 GV->hasHiddenVisibility() ? MMIMachO.getHiddenGVStubEntry(MCSym) :
729 MMIMachO.getGVStubEntry(MCSym);
730 if (StubSym.getPointer() == 0)
731 StubSym = MachineModuleInfoImpl::
732 StubValueTy(Mang->getSymbol(GV), !GV->hasInternalLinkage());
733 return MCSym;
734}
735
Jim Grosbach5df08d82010-11-09 18:45:04 +0000736void ARMAsmPrinter::
737EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) {
738 int Size = TM.getTargetData()->getTypeAllocSize(MCPV->getType());
739
740 ARMConstantPoolValue *ACPV = static_cast<ARMConstantPoolValue*>(MCPV);
Jim Grosbach5df08d82010-11-09 18:45:04 +0000741
Jim Grosbach7c7ddb22010-11-10 17:59:10 +0000742 MCSymbol *MCSym;
Jim Grosbach5df08d82010-11-09 18:45:04 +0000743 if (ACPV->isLSDA()) {
Jim Grosbach7c7ddb22010-11-10 17:59:10 +0000744 SmallString<128> Str;
745 raw_svector_ostream OS(Str);
Jim Grosbach5df08d82010-11-09 18:45:04 +0000746 OS << MAI->getPrivateGlobalPrefix() << "_LSDA_" << getFunctionNumber();
Jim Grosbach7c7ddb22010-11-10 17:59:10 +0000747 MCSym = OutContext.GetOrCreateSymbol(OS.str());
Jim Grosbach5df08d82010-11-09 18:45:04 +0000748 } else if (ACPV->isBlockAddress()) {
Jim Grosbach7c7ddb22010-11-10 17:59:10 +0000749 MCSym = GetBlockAddressSymbol(ACPV->getBlockAddress());
Jim Grosbach5df08d82010-11-09 18:45:04 +0000750 } else if (ACPV->isGlobalValue()) {
751 const GlobalValue *GV = ACPV->getGV();
Evan Cheng5de5d4b2011-01-17 08:03:18 +0000752 MCSym = GetARMGVSymbol(GV);
Jim Grosbach5df08d82010-11-09 18:45:04 +0000753 } else {
754 assert(ACPV->isExtSymbol() && "unrecognized constant pool value");
Jim Grosbach7c7ddb22010-11-10 17:59:10 +0000755 MCSym = GetExternalSymbolSymbol(ACPV->getSymbol());
Jim Grosbach5df08d82010-11-09 18:45:04 +0000756 }
757
758 // Create an MCSymbol for the reference.
Jim Grosbach2c4d5122010-11-10 03:26:07 +0000759 const MCExpr *Expr =
760 MCSymbolRefExpr::Create(MCSym, getModifierVariantKind(ACPV->getModifier()),
761 OutContext);
Jim Grosbach5df08d82010-11-09 18:45:04 +0000762
Jim Grosbach2c4d5122010-11-10 03:26:07 +0000763 if (ACPV->getPCAdjustment()) {
764 MCSymbol *PCLabel = getPICLabel(MAI->getPrivateGlobalPrefix(),
765 getFunctionNumber(),
766 ACPV->getLabelId(),
767 OutContext);
768 const MCExpr *PCRelExpr = MCSymbolRefExpr::Create(PCLabel, OutContext);
769 PCRelExpr =
770 MCBinaryExpr::CreateAdd(PCRelExpr,
771 MCConstantExpr::Create(ACPV->getPCAdjustment(),
772 OutContext),
773 OutContext);
774 if (ACPV->mustAddCurrentAddress()) {
775 // We want "(<expr> - .)", but MC doesn't have a concept of the '.'
776 // label, so just emit a local label end reference that instead.
777 MCSymbol *DotSym = OutContext.CreateTempSymbol();
778 OutStreamer.EmitLabel(DotSym);
779 const MCExpr *DotExpr = MCSymbolRefExpr::Create(DotSym, OutContext);
780 PCRelExpr = MCBinaryExpr::CreateSub(PCRelExpr, DotExpr, OutContext);
Jim Grosbach5df08d82010-11-09 18:45:04 +0000781 }
Jim Grosbach2c4d5122010-11-10 03:26:07 +0000782 Expr = MCBinaryExpr::CreateSub(Expr, PCRelExpr, OutContext);
Jim Grosbach5df08d82010-11-09 18:45:04 +0000783 }
Jim Grosbach2c4d5122010-11-10 03:26:07 +0000784 OutStreamer.EmitValue(Expr, Size);
Jim Grosbach5df08d82010-11-09 18:45:04 +0000785}
786
Jim Grosbacha2244cb2010-09-22 17:39:48 +0000787void ARMAsmPrinter::EmitJumpTable(const MachineInstr *MI) {
788 unsigned Opcode = MI->getOpcode();
789 int OpNum = 1;
790 if (Opcode == ARM::BR_JTadd)
791 OpNum = 2;
792 else if (Opcode == ARM::BR_JTm)
793 OpNum = 3;
794
795 const MachineOperand &MO1 = MI->getOperand(OpNum);
796 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
797 unsigned JTI = MO1.getIndex();
798
799 // Emit a label for the jump table.
800 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
801 OutStreamer.EmitLabel(JTISymbol);
802
803 // Emit each entry of the table.
804 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
805 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
806 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
807
808 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
809 MachineBasicBlock *MBB = JTBBs[i];
810 // Construct an MCExpr for the entry. We want a value of the form:
811 // (BasicBlockAddr - TableBeginAddr)
812 //
813 // For example, a table with entries jumping to basic blocks BB0 and BB1
814 // would look like:
815 // LJTI_0_0:
816 // .word (LBB0 - LJTI_0_0)
817 // .word (LBB1 - LJTI_0_0)
818 const MCExpr *Expr = MCSymbolRefExpr::Create(MBB->getSymbol(), OutContext);
819
820 if (TM.getRelocationModel() == Reloc::PIC_)
821 Expr = MCBinaryExpr::CreateSub(Expr, MCSymbolRefExpr::Create(JTISymbol,
822 OutContext),
823 OutContext);
824 OutStreamer.EmitValue(Expr, 4);
825 }
826}
827
Jim Grosbach882ef2b2010-09-21 23:28:16 +0000828void ARMAsmPrinter::EmitJump2Table(const MachineInstr *MI) {
829 unsigned Opcode = MI->getOpcode();
830 int OpNum = (Opcode == ARM::t2BR_JT) ? 2 : 1;
831 const MachineOperand &MO1 = MI->getOperand(OpNum);
832 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
833 unsigned JTI = MO1.getIndex();
834
835 // Emit a label for the jump table.
836 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
837 OutStreamer.EmitLabel(JTISymbol);
838
839 // Emit each entry of the table.
840 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
841 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
842 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
Jim Grosbach205a5fa2010-09-22 17:15:35 +0000843 unsigned OffsetWidth = 4;
Jim Grosbachd092a872010-11-29 21:28:32 +0000844 if (MI->getOpcode() == ARM::t2TBB_JT)
Jim Grosbach205a5fa2010-09-22 17:15:35 +0000845 OffsetWidth = 1;
Jim Grosbachd092a872010-11-29 21:28:32 +0000846 else if (MI->getOpcode() == ARM::t2TBH_JT)
Jim Grosbach205a5fa2010-09-22 17:15:35 +0000847 OffsetWidth = 2;
Jim Grosbach882ef2b2010-09-21 23:28:16 +0000848
849 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
850 MachineBasicBlock *MBB = JTBBs[i];
Jim Grosbach205a5fa2010-09-22 17:15:35 +0000851 const MCExpr *MBBSymbolExpr = MCSymbolRefExpr::Create(MBB->getSymbol(),
852 OutContext);
Jim Grosbach882ef2b2010-09-21 23:28:16 +0000853 // If this isn't a TBB or TBH, the entries are direct branch instructions.
Jim Grosbach205a5fa2010-09-22 17:15:35 +0000854 if (OffsetWidth == 4) {
Jim Grosbach882ef2b2010-09-21 23:28:16 +0000855 MCInst BrInst;
856 BrInst.setOpcode(ARM::t2B);
Jim Grosbach205a5fa2010-09-22 17:15:35 +0000857 BrInst.addOperand(MCOperand::CreateExpr(MBBSymbolExpr));
Jim Grosbach882ef2b2010-09-21 23:28:16 +0000858 OutStreamer.EmitInstruction(BrInst);
859 continue;
860 }
861 // Otherwise it's an offset from the dispatch instruction. Construct an
Jim Grosbach205a5fa2010-09-22 17:15:35 +0000862 // MCExpr for the entry. We want a value of the form:
863 // (BasicBlockAddr - TableBeginAddr) / 2
864 //
865 // For example, a TBB table with entries jumping to basic blocks BB0 and BB1
866 // would look like:
867 // LJTI_0_0:
868 // .byte (LBB0 - LJTI_0_0) / 2
869 // .byte (LBB1 - LJTI_0_0) / 2
870 const MCExpr *Expr =
871 MCBinaryExpr::CreateSub(MBBSymbolExpr,
872 MCSymbolRefExpr::Create(JTISymbol, OutContext),
873 OutContext);
874 Expr = MCBinaryExpr::CreateDiv(Expr, MCConstantExpr::Create(2, OutContext),
875 OutContext);
876 OutStreamer.EmitValue(Expr, OffsetWidth);
Jim Grosbach882ef2b2010-09-21 23:28:16 +0000877 }
878}
879
Jim Grosbach2d0f53b2010-09-28 17:05:56 +0000880void ARMAsmPrinter::PrintDebugValueComment(const MachineInstr *MI,
881 raw_ostream &OS) {
882 unsigned NOps = MI->getNumOperands();
883 assert(NOps==4);
884 OS << '\t' << MAI->getCommentString() << "DEBUG_VALUE: ";
885 // cast away const; DIetc do not take const operands for some reason.
886 DIVariable V(const_cast<MDNode *>(MI->getOperand(NOps-1).getMetadata()));
887 OS << V.getName();
888 OS << " <- ";
889 // Frame address. Currently handles register +- offset only.
890 assert(MI->getOperand(0).isReg() && MI->getOperand(1).isImm());
891 OS << '['; printOperand(MI, 0, OS); OS << '+'; printOperand(MI, 1, OS);
892 OS << ']';
893 OS << "+";
894 printOperand(MI, NOps-2, OS);
895}
896
Jim Grosbach40edf732010-12-14 21:10:47 +0000897static void populateADROperands(MCInst &Inst, unsigned Dest,
898 const MCSymbol *Label,
899 unsigned pred, unsigned ccreg,
900 MCContext &Ctx) {
901 const MCExpr *SymbolExpr = MCSymbolRefExpr::Create(Label, Ctx);
902 Inst.addOperand(MCOperand::CreateReg(Dest));
903 Inst.addOperand(MCOperand::CreateExpr(SymbolExpr));
904 // Add predicate operands.
905 Inst.addOperand(MCOperand::CreateImm(pred));
906 Inst.addOperand(MCOperand::CreateReg(ccreg));
907}
908
Anton Korobeynikov4d728602011-01-01 20:38:38 +0000909void ARMAsmPrinter::EmitPatchedInstruction(const MachineInstr *MI,
910 unsigned Opcode) {
911 MCInst TmpInst;
912
913 // Emit the instruction as usual, just patch the opcode.
914 LowerARMMachineInstrToMCInst(MI, TmpInst, *this);
915 TmpInst.setOpcode(Opcode);
916 OutStreamer.EmitInstruction(TmpInst);
917}
918
Anton Korobeynikov57caad72011-03-05 18:43:32 +0000919void ARMAsmPrinter::EmitUnwindingInstruction(const MachineInstr *MI) {
920 assert(MI->getFlag(MachineInstr::FrameSetup) &&
921 "Only instruction which are involved into frame setup code are allowed");
922
923 const MachineFunction &MF = *MI->getParent()->getParent();
924 const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo();
Anton Korobeynikovb3fcc062011-03-05 18:43:55 +0000925 const ARMFunctionInfo &AFI = *MF.getInfo<ARMFunctionInfo>();
Anton Korobeynikov57caad72011-03-05 18:43:32 +0000926
927 unsigned FramePtr = RegInfo->getFrameRegister(MF);
Anton Korobeynikov57caad72011-03-05 18:43:32 +0000928 unsigned Opc = MI->getOpcode();
Anton Korobeynikov7a764162011-03-05 18:43:43 +0000929 unsigned SrcReg, DstReg;
930
Anton Korobeynikov3daccd82011-03-05 18:43:50 +0000931 if (Opc == ARM::tPUSH || Opc == ARM::tLDRpci) {
932 // Two special cases:
933 // 1) tPUSH does not have src/dst regs.
934 // 2) for Thumb1 code we sometimes materialize the constant via constpool
935 // load. Yes, this is pretty fragile, but for now I don't see better
936 // way... :(
Anton Korobeynikov7a764162011-03-05 18:43:43 +0000937 SrcReg = DstReg = ARM::SP;
938 } else {
Anton Korobeynikov3daccd82011-03-05 18:43:50 +0000939 SrcReg = MI->getOperand(1).getReg();
Anton Korobeynikov7a764162011-03-05 18:43:43 +0000940 DstReg = MI->getOperand(0).getReg();
941 }
Anton Korobeynikov57caad72011-03-05 18:43:32 +0000942
943 // Try to figure out the unwinding opcode out of src / dst regs.
944 if (MI->getDesc().mayStore()) {
945 // Register saves.
946 assert(DstReg == ARM::SP &&
947 "Only stack pointer as a destination reg is supported");
948
949 SmallVector<unsigned, 4> RegList;
Anton Korobeynikov7a764162011-03-05 18:43:43 +0000950 // Skip src & dst reg, and pred ops.
951 unsigned StartOp = 2 + 2;
952 // Use all the operands.
953 unsigned NumOffset = 0;
954
Anton Korobeynikov57caad72011-03-05 18:43:32 +0000955 switch (Opc) {
956 default:
957 MI->dump();
958 assert(0 && "Unsupported opcode for unwinding information");
Anton Korobeynikov7a764162011-03-05 18:43:43 +0000959 case ARM::tPUSH:
960 // Special case here: no src & dst reg, but two extra imp ops.
961 StartOp = 2; NumOffset = 2;
Anton Korobeynikov57caad72011-03-05 18:43:32 +0000962 case ARM::STMDB_UPD:
Anton Korobeynikov7a764162011-03-05 18:43:43 +0000963 case ARM::t2STMDB_UPD:
Anton Korobeynikov57caad72011-03-05 18:43:32 +0000964 case ARM::VSTMDDB_UPD:
965 assert(SrcReg == ARM::SP &&
966 "Only stack pointer as a source reg is supported");
Anton Korobeynikov7a764162011-03-05 18:43:43 +0000967 for (unsigned i = StartOp, NumOps = MI->getNumOperands() - NumOffset;
968 i != NumOps; ++i)
Anton Korobeynikov57caad72011-03-05 18:43:32 +0000969 RegList.push_back(MI->getOperand(i).getReg());
970 break;
971 case ARM::STR_PRE:
972 assert(MI->getOperand(2).getReg() == ARM::SP &&
973 "Only stack pointer as a source reg is supported");
974 RegList.push_back(SrcReg);
975 break;
976 }
977 OutStreamer.EmitRegSave(RegList, Opc == ARM::VSTMDDB_UPD);
978 } else {
979 // Changes of stack / frame pointer.
980 if (SrcReg == ARM::SP) {
981 int64_t Offset = 0;
982 switch (Opc) {
983 default:
984 MI->dump();
985 assert(0 && "Unsupported opcode for unwinding information");
986 case ARM::MOVr:
Anton Korobeynikov7a764162011-03-05 18:43:43 +0000987 case ARM::tMOVgpr2gpr:
Anton Korobeynikov3daccd82011-03-05 18:43:50 +0000988 case ARM::tMOVgpr2tgpr:
Anton Korobeynikov57caad72011-03-05 18:43:32 +0000989 Offset = 0;
990 break;
991 case ARM::ADDri:
992 Offset = -MI->getOperand(2).getImm();
993 break;
994 case ARM::SUBri:
Anton Korobeynikov7a764162011-03-05 18:43:43 +0000995 case ARM::t2SUBrSPi:
Anton Korobeynikov57caad72011-03-05 18:43:32 +0000996 Offset = MI->getOperand(2).getImm();
997 break;
Anton Korobeynikov7a764162011-03-05 18:43:43 +0000998 case ARM::tSUBspi:
999 Offset = MI->getOperand(2).getImm()*4;
1000 break;
1001 case ARM::tADDspi:
1002 case ARM::tADDrSPi:
1003 Offset = -MI->getOperand(2).getImm()*4;
1004 break;
Anton Korobeynikovb3fcc062011-03-05 18:43:55 +00001005 case ARM::tLDRpci: {
1006 // Grab the constpool index and check, whether it corresponds to
1007 // original or cloned constpool entry.
1008 unsigned CPI = MI->getOperand(1).getIndex();
1009 const MachineConstantPool *MCP = MF.getConstantPool();
1010 if (CPI >= MCP->getConstants().size())
1011 CPI = AFI.getOriginalCPIdx(CPI);
1012 assert(CPI != -1U && "Invalid constpool index");
1013
1014 // Derive the actual offset.
1015 const MachineConstantPoolEntry &CPE = MCP->getConstants()[CPI];
1016 assert(!CPE.isMachineConstantPoolEntry() && "Invalid constpool entry");
1017 // FIXME: Check for user, it should be "add" instruction!
1018 Offset = -cast<ConstantInt>(CPE.Val.ConstVal)->getSExtValue();
Anton Korobeynikov3daccd82011-03-05 18:43:50 +00001019 break;
Anton Korobeynikov57caad72011-03-05 18:43:32 +00001020 }
Anton Korobeynikovb3fcc062011-03-05 18:43:55 +00001021 }
Anton Korobeynikov57caad72011-03-05 18:43:32 +00001022
1023 if (DstReg == FramePtr && FramePtr != ARM::SP)
Anton Korobeynikove5163792011-03-05 18:44:00 +00001024 // Set-up of the frame pointer. Positive values correspond to "add"
1025 // instruction.
1026 OutStreamer.EmitSetFP(FramePtr, ARM::SP, -Offset);
Anton Korobeynikov57caad72011-03-05 18:43:32 +00001027 else if (DstReg == ARM::SP) {
Anton Korobeynikove5163792011-03-05 18:44:00 +00001028 // Change of SP by an offset. Positive values correspond to "sub"
Anton Korobeynikov57caad72011-03-05 18:43:32 +00001029 // instruction.
1030 OutStreamer.EmitPad(Offset);
1031 } else {
1032 MI->dump();
1033 assert(0 && "Unsupported opcode for unwinding information");
1034 }
1035 } else if (DstReg == ARM::SP) {
1036 // FIXME: .movsp goes here
1037 MI->dump();
1038 assert(0 && "Unsupported opcode for unwinding information");
1039 }
1040 else {
1041 MI->dump();
1042 assert(0 && "Unsupported opcode for unwinding information");
1043 }
1044 }
1045}
1046
1047extern cl::opt<bool> EnableARMEHABI;
1048
Jim Grosbachb454cda2010-09-29 15:23:40 +00001049void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
Evan Cheng5de5d4b2011-01-17 08:03:18 +00001050 unsigned Opc = MI->getOpcode();
1051 switch (Opc) {
Chris Lattner4d152222009-10-19 22:23:04 +00001052 default: break;
Jim Grosbach72422d32011-03-11 23:24:15 +00001053 case ARM::B: {
1054 // B is just a Bcc with an 'always' predicate.
1055 MCInst TmpInst;
1056 LowerARMMachineInstrToMCInst(MI, TmpInst, *this);
1057 TmpInst.setOpcode(ARM::Bcc);
1058 // Add predicate operands.
1059 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1060 TmpInst.addOperand(MCOperand::CreateReg(0));
1061 OutStreamer.EmitInstruction(TmpInst);
1062 return;
1063 }
Jim Grosbachdd119882011-03-11 22:51:41 +00001064 case ARM::LDMIA_RET: {
1065 // LDMIA_RET is just a normal LDMIA_UPD instruction that targets PC and as
1066 // such has additional code-gen properties and scheduling information.
1067 // To emit it, we just construct as normal and set the opcode to LDMIA_UPD.
1068 MCInst TmpInst;
1069 LowerARMMachineInstrToMCInst(MI, TmpInst, *this);
1070 TmpInst.setOpcode(ARM::LDMIA_UPD);
1071 OutStreamer.EmitInstruction(TmpInst);
1072 return;
1073 }
Jim Grosbach9702e602010-12-09 01:22:19 +00001074 case ARM::t2ADDrSPi:
1075 case ARM::t2ADDrSPi12:
1076 case ARM::t2SUBrSPi:
1077 case ARM::t2SUBrSPi12:
Jim Grosbach766a63d2010-12-09 01:23:51 +00001078 assert ((MI->getOperand(1).getReg() == ARM::SP) &&
1079 "Unexpected source register!");
Jim Grosbach9702e602010-12-09 01:22:19 +00001080 break;
1081
Chris Lattner112f2392010-11-14 20:31:06 +00001082 case ARM::t2MOVi32imm: assert(0 && "Should be lowered by thumb2it pass");
Jim Grosbach2d0f53b2010-09-28 17:05:56 +00001083 case ARM::DBG_VALUE: {
1084 if (isVerbose() && OutStreamer.hasRawTextSupport()) {
1085 SmallString<128> TmpStr;
1086 raw_svector_ostream OS(TmpStr);
1087 PrintDebugValueComment(MI, OS);
1088 OutStreamer.EmitRawText(StringRef(OS.str()));
1089 }
1090 return;
1091 }
Jim Grosbach3efad8f2010-12-16 19:11:16 +00001092 case ARM::tBfar: {
1093 MCInst TmpInst;
1094 TmpInst.setOpcode(ARM::tBL);
1095 TmpInst.addOperand(MCOperand::CreateExpr(MCSymbolRefExpr::Create(
1096 MI->getOperand(0).getMBB()->getSymbol(), OutContext)));
1097 OutStreamer.EmitInstruction(TmpInst);
1098 return;
1099 }
Jim Grosbach40edf732010-12-14 21:10:47 +00001100 case ARM::LEApcrel:
Jim Grosbachd40963c2010-12-14 22:28:03 +00001101 case ARM::tLEApcrel:
Jim Grosbach40edf732010-12-14 21:10:47 +00001102 case ARM::t2LEApcrel: {
Jim Grosbachdff84b02010-12-02 00:28:45 +00001103 // FIXME: Need to also handle globals and externals
Jim Grosbachdff84b02010-12-02 00:28:45 +00001104 MCInst TmpInst;
Jim Grosbachd40963c2010-12-14 22:28:03 +00001105 TmpInst.setOpcode(MI->getOpcode() == ARM::t2LEApcrel ? ARM::t2ADR
1106 : (MI->getOpcode() == ARM::tLEApcrel ? ARM::tADR
1107 : ARM::ADR));
Jim Grosbach40edf732010-12-14 21:10:47 +00001108 populateADROperands(TmpInst, MI->getOperand(0).getReg(),
1109 GetCPISymbol(MI->getOperand(1).getIndex()),
1110 MI->getOperand(2).getImm(), MI->getOperand(3).getReg(),
1111 OutContext);
Jim Grosbachdff84b02010-12-02 00:28:45 +00001112 OutStreamer.EmitInstruction(TmpInst);
1113 return;
1114 }
Jim Grosbachd40963c2010-12-14 22:28:03 +00001115 case ARM::LEApcrelJT:
1116 case ARM::tLEApcrelJT:
1117 case ARM::t2LEApcrelJT: {
Jim Grosbach5d14f9b2010-12-01 19:47:31 +00001118 MCInst TmpInst;
Jim Grosbachd40963c2010-12-14 22:28:03 +00001119 TmpInst.setOpcode(MI->getOpcode() == ARM::t2LEApcrelJT ? ARM::t2ADR
1120 : (MI->getOpcode() == ARM::tLEApcrelJT ? ARM::tADR
1121 : ARM::ADR));
Jim Grosbach40edf732010-12-14 21:10:47 +00001122 populateADROperands(TmpInst, MI->getOperand(0).getReg(),
1123 GetARMJTIPICJumpTableLabel2(MI->getOperand(1).getIndex(),
1124 MI->getOperand(2).getImm()),
1125 MI->getOperand(3).getImm(), MI->getOperand(4).getReg(),
1126 OutContext);
Jim Grosbach5d14f9b2010-12-01 19:47:31 +00001127 OutStreamer.EmitInstruction(TmpInst);
1128 return;
1129 }
Jim Grosbach2e812e12010-11-30 18:56:36 +00001130 case ARM::MOVPCRX: {
1131 MCInst TmpInst;
1132 TmpInst.setOpcode(ARM::MOVr);
1133 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1134 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1135 // Add predicate operands.
1136 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1137 TmpInst.addOperand(MCOperand::CreateReg(0));
1138 // Add 's' bit operand (always reg0 for this)
1139 TmpInst.addOperand(MCOperand::CreateReg(0));
1140 OutStreamer.EmitInstruction(TmpInst);
1141 return;
1142 }
Jim Grosbachf859a542011-03-12 00:45:26 +00001143 // Darwin call instructions are just normal call instructions with different
1144 // clobber semantics (they clobber R9).
1145 case ARM::BLr9:
1146 case ARM::BLr9_pred:
1147 case ARM::BLXr9:
1148 case ARM::BLXr9_pred: {
1149 unsigned newOpc;
1150 switch (Opc) {
1151 default: assert(0);
1152 case ARM::BLr9: newOpc = ARM::BL; break;
1153 case ARM::BLr9_pred: newOpc = ARM::BL_pred; break;
1154 case ARM::BLXr9: newOpc = ARM::BLX; break;
1155 case ARM::BLXr9_pred: newOpc = ARM::BLX_pred; break;
1156 }
1157 MCInst TmpInst;
1158 LowerARMMachineInstrToMCInst(MI, TmpInst, *this);
1159 TmpInst.setOpcode(newOpc);
1160 OutStreamer.EmitInstruction(TmpInst);
1161 return;
1162 }
Jim Grosbacha0d2c8a2010-11-30 18:30:19 +00001163 case ARM::BXr9_CALL:
1164 case ARM::BX_CALL: {
1165 {
1166 MCInst TmpInst;
1167 TmpInst.setOpcode(ARM::MOVr);
1168 TmpInst.addOperand(MCOperand::CreateReg(ARM::LR));
1169 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1170 // Add predicate operands.
1171 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1172 TmpInst.addOperand(MCOperand::CreateReg(0));
1173 // Add 's' bit operand (always reg0 for this)
1174 TmpInst.addOperand(MCOperand::CreateReg(0));
1175 OutStreamer.EmitInstruction(TmpInst);
1176 }
1177 {
1178 MCInst TmpInst;
1179 TmpInst.setOpcode(ARM::BX);
1180 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1181 OutStreamer.EmitInstruction(TmpInst);
1182 }
1183 return;
1184 }
1185 case ARM::BMOVPCRXr9_CALL:
1186 case ARM::BMOVPCRX_CALL: {
1187 {
1188 MCInst TmpInst;
1189 TmpInst.setOpcode(ARM::MOVr);
1190 TmpInst.addOperand(MCOperand::CreateReg(ARM::LR));
1191 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1192 // Add predicate operands.
1193 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1194 TmpInst.addOperand(MCOperand::CreateReg(0));
1195 // Add 's' bit operand (always reg0 for this)
1196 TmpInst.addOperand(MCOperand::CreateReg(0));
1197 OutStreamer.EmitInstruction(TmpInst);
1198 }
1199 {
1200 MCInst TmpInst;
1201 TmpInst.setOpcode(ARM::MOVr);
1202 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1203 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1204 // Add predicate operands.
1205 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1206 TmpInst.addOperand(MCOperand::CreateReg(0));
1207 // Add 's' bit operand (always reg0 for this)
1208 TmpInst.addOperand(MCOperand::CreateReg(0));
1209 OutStreamer.EmitInstruction(TmpInst);
1210 }
1211 return;
1212 }
Evan Cheng53519f02011-01-21 18:55:51 +00001213 case ARM::MOVi16_ga_pcrel:
1214 case ARM::t2MOVi16_ga_pcrel: {
Evan Cheng5de5d4b2011-01-17 08:03:18 +00001215 MCInst TmpInst;
Evan Cheng53519f02011-01-21 18:55:51 +00001216 TmpInst.setOpcode(Opc == ARM::MOVi16_ga_pcrel? ARM::MOVi16 : ARM::t2MOVi16);
Evan Cheng5de5d4b2011-01-17 08:03:18 +00001217 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1218
Evan Cheng53519f02011-01-21 18:55:51 +00001219 unsigned TF = MI->getOperand(1).getTargetFlags();
1220 bool isPIC = TF == ARMII::MO_LO16_NONLAZY_PIC;
Evan Cheng5de5d4b2011-01-17 08:03:18 +00001221 const GlobalValue *GV = MI->getOperand(1).getGlobal();
1222 MCSymbol *GVSym = GetARMGVSymbol(GV);
1223 const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
Evan Cheng53519f02011-01-21 18:55:51 +00001224 if (isPIC) {
1225 MCSymbol *LabelSym = getPICLabel(MAI->getPrivateGlobalPrefix(),
1226 getFunctionNumber(),
1227 MI->getOperand(2).getImm(), OutContext);
1228 const MCExpr *LabelSymExpr= MCSymbolRefExpr::Create(LabelSym, OutContext);
1229 unsigned PCAdj = (Opc == ARM::MOVi16_ga_pcrel) ? 8 : 4;
1230 const MCExpr *PCRelExpr =
1231 ARMMCExpr::CreateLower16(MCBinaryExpr::CreateSub(GVSymExpr,
1232 MCBinaryExpr::CreateAdd(LabelSymExpr,
1233 MCConstantExpr::Create(PCAdj, OutContext),
Evan Cheng5de5d4b2011-01-17 08:03:18 +00001234 OutContext), OutContext), OutContext);
Evan Cheng53519f02011-01-21 18:55:51 +00001235 TmpInst.addOperand(MCOperand::CreateExpr(PCRelExpr));
1236 } else {
1237 const MCExpr *RefExpr= ARMMCExpr::CreateLower16(GVSymExpr, OutContext);
1238 TmpInst.addOperand(MCOperand::CreateExpr(RefExpr));
1239 }
1240
Evan Cheng5de5d4b2011-01-17 08:03:18 +00001241 // Add predicate operands.
1242 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1243 TmpInst.addOperand(MCOperand::CreateReg(0));
1244 // Add 's' bit operand (always reg0 for this)
1245 TmpInst.addOperand(MCOperand::CreateReg(0));
1246 OutStreamer.EmitInstruction(TmpInst);
1247 return;
1248 }
Evan Cheng53519f02011-01-21 18:55:51 +00001249 case ARM::MOVTi16_ga_pcrel:
1250 case ARM::t2MOVTi16_ga_pcrel: {
Evan Cheng5de5d4b2011-01-17 08:03:18 +00001251 MCInst TmpInst;
Evan Cheng53519f02011-01-21 18:55:51 +00001252 TmpInst.setOpcode(Opc == ARM::MOVTi16_ga_pcrel
1253 ? ARM::MOVTi16 : ARM::t2MOVTi16);
Evan Cheng5de5d4b2011-01-17 08:03:18 +00001254 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1255 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1256
Evan Cheng53519f02011-01-21 18:55:51 +00001257 unsigned TF = MI->getOperand(2).getTargetFlags();
1258 bool isPIC = TF == ARMII::MO_HI16_NONLAZY_PIC;
Evan Cheng5de5d4b2011-01-17 08:03:18 +00001259 const GlobalValue *GV = MI->getOperand(2).getGlobal();
1260 MCSymbol *GVSym = GetARMGVSymbol(GV);
1261 const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
Evan Cheng53519f02011-01-21 18:55:51 +00001262 if (isPIC) {
1263 MCSymbol *LabelSym = getPICLabel(MAI->getPrivateGlobalPrefix(),
1264 getFunctionNumber(),
1265 MI->getOperand(3).getImm(), OutContext);
1266 const MCExpr *LabelSymExpr= MCSymbolRefExpr::Create(LabelSym, OutContext);
1267 unsigned PCAdj = (Opc == ARM::MOVTi16_ga_pcrel) ? 8 : 4;
1268 const MCExpr *PCRelExpr =
1269 ARMMCExpr::CreateUpper16(MCBinaryExpr::CreateSub(GVSymExpr,
1270 MCBinaryExpr::CreateAdd(LabelSymExpr,
1271 MCConstantExpr::Create(PCAdj, OutContext),
Evan Cheng5de5d4b2011-01-17 08:03:18 +00001272 OutContext), OutContext), OutContext);
Evan Cheng53519f02011-01-21 18:55:51 +00001273 TmpInst.addOperand(MCOperand::CreateExpr(PCRelExpr));
1274 } else {
1275 const MCExpr *RefExpr= ARMMCExpr::CreateUpper16(GVSymExpr, OutContext);
1276 TmpInst.addOperand(MCOperand::CreateExpr(RefExpr));
1277 }
Evan Cheng5de5d4b2011-01-17 08:03:18 +00001278 // Add predicate operands.
1279 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1280 TmpInst.addOperand(MCOperand::CreateReg(0));
1281 // Add 's' bit operand (always reg0 for this)
1282 TmpInst.addOperand(MCOperand::CreateReg(0));
1283 OutStreamer.EmitInstruction(TmpInst);
1284 return;
1285 }
Jim Grosbachfbd18732010-09-17 23:41:53 +00001286 case ARM::tPICADD: {
1287 // This is a pseudo op for a label + instruction sequence, which looks like:
1288 // LPC0:
1289 // add r0, pc
1290 // This adds the address of LPC0 to r0.
1291
1292 // Emit the label.
Jim Grosbach988ce092010-09-18 00:05:05 +00001293 OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(),
1294 getFunctionNumber(), MI->getOperand(2).getImm(),
1295 OutContext));
Jim Grosbachfbd18732010-09-17 23:41:53 +00001296
1297 // Form and emit the add.
1298 MCInst AddInst;
1299 AddInst.setOpcode(ARM::tADDhirr);
1300 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1301 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1302 AddInst.addOperand(MCOperand::CreateReg(ARM::PC));
1303 // Add predicate operands.
1304 AddInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1305 AddInst.addOperand(MCOperand::CreateReg(0));
1306 OutStreamer.EmitInstruction(AddInst);
1307 return;
1308 }
Jim Grosbacha3fbadf2010-09-30 19:53:58 +00001309 case ARM::PICADD: {
Chris Lattner4d152222009-10-19 22:23:04 +00001310 // This is a pseudo op for a label + instruction sequence, which looks like:
1311 // LPC0:
1312 // add r0, pc, r0
1313 // This adds the address of LPC0 to r0.
Jim Grosbachb0739b72010-09-02 01:02:06 +00001314
Chris Lattner4d152222009-10-19 22:23:04 +00001315 // Emit the label.
Jim Grosbach988ce092010-09-18 00:05:05 +00001316 OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(),
1317 getFunctionNumber(), MI->getOperand(2).getImm(),
1318 OutContext));
Jim Grosbachb0739b72010-09-02 01:02:06 +00001319
Jim Grosbachf3f09522010-09-14 21:05:34 +00001320 // Form and emit the add.
Chris Lattner4d152222009-10-19 22:23:04 +00001321 MCInst AddInst;
1322 AddInst.setOpcode(ARM::ADDrr);
1323 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1324 AddInst.addOperand(MCOperand::CreateReg(ARM::PC));
1325 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
Jim Grosbach5b46d622010-09-14 21:28:17 +00001326 // Add predicate operands.
1327 AddInst.addOperand(MCOperand::CreateImm(MI->getOperand(3).getImm()));
1328 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(4).getReg()));
1329 // Add 's' bit operand (always reg0 for this)
1330 AddInst.addOperand(MCOperand::CreateReg(0));
Chris Lattner850d2e22010-02-03 01:16:28 +00001331 OutStreamer.EmitInstruction(AddInst);
Chris Lattner4d152222009-10-19 22:23:04 +00001332 return;
1333 }
Jim Grosbacha28abbe2010-09-17 16:25:52 +00001334 case ARM::PICSTR:
1335 case ARM::PICSTRB:
1336 case ARM::PICSTRH:
1337 case ARM::PICLDR:
1338 case ARM::PICLDRB:
1339 case ARM::PICLDRH:
1340 case ARM::PICLDRSB:
1341 case ARM::PICLDRSH: {
Jim Grosbachb74ca9d2010-09-16 17:43:25 +00001342 // This is a pseudo op for a label + instruction sequence, which looks like:
1343 // LPC0:
Jim Grosbacha28abbe2010-09-17 16:25:52 +00001344 // OP r0, [pc, r0]
Jim Grosbachb74ca9d2010-09-16 17:43:25 +00001345 // The LCP0 label is referenced by a constant pool entry in order to get
1346 // a PC-relative address at the ldr instruction.
1347
1348 // Emit the label.
Jim Grosbach988ce092010-09-18 00:05:05 +00001349 OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(),
1350 getFunctionNumber(), MI->getOperand(2).getImm(),
1351 OutContext));
Jim Grosbachb74ca9d2010-09-16 17:43:25 +00001352
1353 // Form and emit the load
Jim Grosbacha28abbe2010-09-17 16:25:52 +00001354 unsigned Opcode;
1355 switch (MI->getOpcode()) {
1356 default:
1357 llvm_unreachable("Unexpected opcode!");
Jim Grosbach7e3383c2010-10-27 23:12:14 +00001358 case ARM::PICSTR: Opcode = ARM::STRrs; break;
1359 case ARM::PICSTRB: Opcode = ARM::STRBrs; break;
Jim Grosbacha28abbe2010-09-17 16:25:52 +00001360 case ARM::PICSTRH: Opcode = ARM::STRH; break;
Jim Grosbach3e556122010-10-26 22:37:02 +00001361 case ARM::PICLDR: Opcode = ARM::LDRrs; break;
Jim Grosbachc1d30212010-10-27 00:19:44 +00001362 case ARM::PICLDRB: Opcode = ARM::LDRBrs; break;
Jim Grosbacha28abbe2010-09-17 16:25:52 +00001363 case ARM::PICLDRH: Opcode = ARM::LDRH; break;
1364 case ARM::PICLDRSB: Opcode = ARM::LDRSB; break;
1365 case ARM::PICLDRSH: Opcode = ARM::LDRSH; break;
1366 }
1367 MCInst LdStInst;
1368 LdStInst.setOpcode(Opcode);
1369 LdStInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1370 LdStInst.addOperand(MCOperand::CreateReg(ARM::PC));
1371 LdStInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1372 LdStInst.addOperand(MCOperand::CreateImm(0));
Jim Grosbachb74ca9d2010-09-16 17:43:25 +00001373 // Add predicate operands.
Jim Grosbacha28abbe2010-09-17 16:25:52 +00001374 LdStInst.addOperand(MCOperand::CreateImm(MI->getOperand(3).getImm()));
1375 LdStInst.addOperand(MCOperand::CreateReg(MI->getOperand(4).getReg()));
1376 OutStreamer.EmitInstruction(LdStInst);
Jim Grosbachb74ca9d2010-09-16 17:43:25 +00001377
1378 return;
1379 }
Jim Grosbacha3fbadf2010-09-30 19:53:58 +00001380 case ARM::CONSTPOOL_ENTRY: {
Chris Lattnera70e6442009-10-19 22:33:05 +00001381 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool
1382 /// in the function. The first operand is the ID# for this instruction, the
1383 /// second is the index into the MachineConstantPool that this is, the third
1384 /// is the size in bytes of this constant pool entry.
1385 unsigned LabelId = (unsigned)MI->getOperand(0).getImm();
1386 unsigned CPIdx = (unsigned)MI->getOperand(1).getIndex();
1387
1388 EmitAlignment(2);
Chris Lattner1b46f432010-01-23 07:00:21 +00001389 OutStreamer.EmitLabel(GetCPISymbol(LabelId));
Chris Lattnera70e6442009-10-19 22:33:05 +00001390
1391 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIdx];
1392 if (MCPE.isMachineConstantPoolEntry())
1393 EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
1394 else
1395 EmitGlobalConstant(MCPE.Val.ConstVal);
Jim Grosbachb0739b72010-09-02 01:02:06 +00001396
Chris Lattnera70e6442009-10-19 22:33:05 +00001397 return;
1398 }
Jim Grosbach882ef2b2010-09-21 23:28:16 +00001399 case ARM::t2BR_JT: {
1400 // Lower and emit the instruction itself, then the jump table following it.
1401 MCInst TmpInst;
Jim Grosbach5ca66692010-11-29 22:37:40 +00001402 TmpInst.setOpcode(ARM::tMOVgpr2gpr);
1403 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1404 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1405 // Add predicate operands.
1406 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1407 TmpInst.addOperand(MCOperand::CreateReg(0));
Jim Grosbach882ef2b2010-09-21 23:28:16 +00001408 OutStreamer.EmitInstruction(TmpInst);
Jim Grosbach5ca66692010-11-29 22:37:40 +00001409 // Output the data for the jump table itself
1410 EmitJump2Table(MI);
1411 return;
1412 }
1413 case ARM::t2TBB_JT: {
1414 // Lower and emit the instruction itself, then the jump table following it.
1415 MCInst TmpInst;
1416
1417 TmpInst.setOpcode(ARM::t2TBB);
1418 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1419 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1420 // Add predicate operands.
1421 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1422 TmpInst.addOperand(MCOperand::CreateReg(0));
1423 OutStreamer.EmitInstruction(TmpInst);
1424 // Output the data for the jump table itself
1425 EmitJump2Table(MI);
1426 // Make sure the next instruction is 2-byte aligned.
1427 EmitAlignment(1);
1428 return;
1429 }
1430 case ARM::t2TBH_JT: {
1431 // Lower and emit the instruction itself, then the jump table following it.
1432 MCInst TmpInst;
1433
1434 TmpInst.setOpcode(ARM::t2TBH);
1435 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1436 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1437 // Add predicate operands.
1438 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1439 TmpInst.addOperand(MCOperand::CreateReg(0));
1440 OutStreamer.EmitInstruction(TmpInst);
1441 // Output the data for the jump table itself
Jim Grosbach882ef2b2010-09-21 23:28:16 +00001442 EmitJump2Table(MI);
1443 return;
1444 }
Jim Grosbachf1aa47d2010-11-29 19:32:47 +00001445 case ARM::tBR_JTr:
Jim Grosbach2dc77682010-11-29 18:37:44 +00001446 case ARM::BR_JTr: {
1447 // Lower and emit the instruction itself, then the jump table following it.
1448 // mov pc, target
1449 MCInst TmpInst;
Jim Grosbach5ca66692010-11-29 22:37:40 +00001450 unsigned Opc = MI->getOpcode() == ARM::BR_JTr ?
1451 ARM::MOVr : ARM::tMOVgpr2gpr;
Jim Grosbachf1aa47d2010-11-29 19:32:47 +00001452 TmpInst.setOpcode(Opc);
Jim Grosbach2dc77682010-11-29 18:37:44 +00001453 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1454 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1455 // Add predicate operands.
1456 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1457 TmpInst.addOperand(MCOperand::CreateReg(0));
Jim Grosbacha0d2c8a2010-11-30 18:30:19 +00001458 // Add 's' bit operand (always reg0 for this)
1459 if (Opc == ARM::MOVr)
1460 TmpInst.addOperand(MCOperand::CreateReg(0));
Jim Grosbach2dc77682010-11-29 18:37:44 +00001461 OutStreamer.EmitInstruction(TmpInst);
1462
Jim Grosbachf1aa47d2010-11-29 19:32:47 +00001463 // Make sure the Thumb jump table is 4-byte aligned.
Bill Wendlinga68a4fd2010-12-18 02:13:59 +00001464 if (Opc == ARM::tMOVgpr2gpr)
Jim Grosbachf1aa47d2010-11-29 19:32:47 +00001465 EmitAlignment(2);
1466
Jim Grosbach2dc77682010-11-29 18:37:44 +00001467 // Output the data for the jump table itself
1468 EmitJumpTable(MI);
1469 return;
1470 }
1471 case ARM::BR_JTm: {
1472 // Lower and emit the instruction itself, then the jump table following it.
1473 // ldr pc, target
1474 MCInst TmpInst;
1475 if (MI->getOperand(1).getReg() == 0) {
1476 // literal offset
1477 TmpInst.setOpcode(ARM::LDRi12);
1478 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1479 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1480 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
1481 } else {
1482 TmpInst.setOpcode(ARM::LDRrs);
1483 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1484 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1485 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1486 TmpInst.addOperand(MCOperand::CreateImm(0));
1487 }
1488 // Add predicate operands.
1489 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1490 TmpInst.addOperand(MCOperand::CreateReg(0));
1491 OutStreamer.EmitInstruction(TmpInst);
1492
1493 // Output the data for the jump table itself
Jim Grosbacha2244cb2010-09-22 17:39:48 +00001494 EmitJumpTable(MI);
1495 return;
1496 }
Jim Grosbachf8dabac2010-11-17 21:05:55 +00001497 case ARM::BR_JTadd: {
1498 // Lower and emit the instruction itself, then the jump table following it.
1499 // add pc, target, idx
Jim Grosbach2dc77682010-11-29 18:37:44 +00001500 MCInst TmpInst;
1501 TmpInst.setOpcode(ARM::ADDrr);
1502 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1503 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1504 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
Jim Grosbachf8dabac2010-11-17 21:05:55 +00001505 // Add predicate operands.
Jim Grosbach2dc77682010-11-29 18:37:44 +00001506 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1507 TmpInst.addOperand(MCOperand::CreateReg(0));
Jim Grosbachf8dabac2010-11-17 21:05:55 +00001508 // Add 's' bit operand (always reg0 for this)
Jim Grosbach2dc77682010-11-29 18:37:44 +00001509 TmpInst.addOperand(MCOperand::CreateReg(0));
1510 OutStreamer.EmitInstruction(TmpInst);
Jim Grosbachf8dabac2010-11-17 21:05:55 +00001511
1512 // Output the data for the jump table itself
1513 EmitJumpTable(MI);
1514 return;
1515 }
Jim Grosbach2e6ae132010-09-23 18:05:37 +00001516 case ARM::TRAP: {
1517 // Non-Darwin binutils don't yet support the "trap" mnemonic.
1518 // FIXME: Remove this special case when they do.
1519 if (!Subtarget->isTargetDarwin()) {
Jim Grosbach78890f42010-10-01 23:21:38 +00001520 //.long 0xe7ffdefe @ trap
Jim Grosbachb2dda4b2010-09-23 19:42:17 +00001521 uint32_t Val = 0xe7ffdefeUL;
Jim Grosbach2e6ae132010-09-23 18:05:37 +00001522 OutStreamer.AddComment("trap");
1523 OutStreamer.EmitIntValue(Val, 4);
1524 return;
1525 }
1526 break;
1527 }
1528 case ARM::tTRAP: {
1529 // Non-Darwin binutils don't yet support the "trap" mnemonic.
1530 // FIXME: Remove this special case when they do.
1531 if (!Subtarget->isTargetDarwin()) {
Jim Grosbach78890f42010-10-01 23:21:38 +00001532 //.short 57086 @ trap
Benjamin Kramerc8ab9eb2010-09-23 18:57:26 +00001533 uint16_t Val = 0xdefe;
Jim Grosbach2e6ae132010-09-23 18:05:37 +00001534 OutStreamer.AddComment("trap");
1535 OutStreamer.EmitIntValue(Val, 2);
1536 return;
1537 }
1538 break;
1539 }
Jim Grosbach433a5782010-09-24 20:47:58 +00001540 case ARM::t2Int_eh_sjlj_setjmp:
1541 case ARM::t2Int_eh_sjlj_setjmp_nofp:
Jim Grosbacha3fbadf2010-09-30 19:53:58 +00001542 case ARM::tInt_eh_sjlj_setjmp: {
Jim Grosbach433a5782010-09-24 20:47:58 +00001543 // Two incoming args: GPR:$src, GPR:$val
1544 // mov $val, pc
1545 // adds $val, #7
1546 // str $val, [$src, #4]
1547 // movs r0, #0
1548 // b 1f
1549 // movs r0, #1
1550 // 1:
1551 unsigned SrcReg = MI->getOperand(0).getReg();
1552 unsigned ValReg = MI->getOperand(1).getReg();
1553 MCSymbol *Label = GetARMSJLJEHLabel();
1554 {
1555 MCInst TmpInst;
1556 TmpInst.setOpcode(ARM::tMOVgpr2tgpr);
1557 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1558 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1559 // 's' bit operand
1560 TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1561 OutStreamer.AddComment("eh_setjmp begin");
1562 OutStreamer.EmitInstruction(TmpInst);
1563 }
1564 {
1565 MCInst TmpInst;
1566 TmpInst.setOpcode(ARM::tADDi3);
1567 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1568 // 's' bit operand
1569 TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1570 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1571 TmpInst.addOperand(MCOperand::CreateImm(7));
1572 // Predicate.
1573 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1574 TmpInst.addOperand(MCOperand::CreateReg(0));
1575 OutStreamer.EmitInstruction(TmpInst);
1576 }
1577 {
1578 MCInst TmpInst;
Bill Wendlingf4caf692010-12-14 03:36:38 +00001579 TmpInst.setOpcode(ARM::tSTRi);
Jim Grosbach433a5782010-09-24 20:47:58 +00001580 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1581 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1582 // The offset immediate is #4. The operand value is scaled by 4 for the
1583 // tSTR instruction.
1584 TmpInst.addOperand(MCOperand::CreateImm(1));
Jim Grosbach433a5782010-09-24 20:47:58 +00001585 // Predicate.
1586 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1587 TmpInst.addOperand(MCOperand::CreateReg(0));
1588 OutStreamer.EmitInstruction(TmpInst);
1589 }
1590 {
1591 MCInst TmpInst;
1592 TmpInst.setOpcode(ARM::tMOVi8);
1593 TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
1594 TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1595 TmpInst.addOperand(MCOperand::CreateImm(0));
1596 // Predicate.
1597 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1598 TmpInst.addOperand(MCOperand::CreateReg(0));
1599 OutStreamer.EmitInstruction(TmpInst);
1600 }
1601 {
1602 const MCExpr *SymbolExpr = MCSymbolRefExpr::Create(Label, OutContext);
1603 MCInst TmpInst;
1604 TmpInst.setOpcode(ARM::tB);
1605 TmpInst.addOperand(MCOperand::CreateExpr(SymbolExpr));
1606 OutStreamer.EmitInstruction(TmpInst);
1607 }
1608 {
1609 MCInst TmpInst;
1610 TmpInst.setOpcode(ARM::tMOVi8);
1611 TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
1612 TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1613 TmpInst.addOperand(MCOperand::CreateImm(1));
1614 // Predicate.
1615 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1616 TmpInst.addOperand(MCOperand::CreateReg(0));
1617 OutStreamer.AddComment("eh_setjmp end");
1618 OutStreamer.EmitInstruction(TmpInst);
1619 }
1620 OutStreamer.EmitLabel(Label);
1621 return;
1622 }
1623
Jim Grosbach45390082010-09-23 23:33:56 +00001624 case ARM::Int_eh_sjlj_setjmp_nofp:
Jim Grosbacha3fbadf2010-09-30 19:53:58 +00001625 case ARM::Int_eh_sjlj_setjmp: {
Jim Grosbach45390082010-09-23 23:33:56 +00001626 // Two incoming args: GPR:$src, GPR:$val
1627 // add $val, pc, #8
1628 // str $val, [$src, #+4]
1629 // mov r0, #0
1630 // add pc, pc, #0
1631 // mov r0, #1
1632 unsigned SrcReg = MI->getOperand(0).getReg();
1633 unsigned ValReg = MI->getOperand(1).getReg();
1634
1635 {
1636 MCInst TmpInst;
1637 TmpInst.setOpcode(ARM::ADDri);
1638 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1639 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1640 TmpInst.addOperand(MCOperand::CreateImm(8));
1641 // Predicate.
1642 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1643 TmpInst.addOperand(MCOperand::CreateReg(0));
1644 // 's' bit operand (always reg0 for this).
1645 TmpInst.addOperand(MCOperand::CreateReg(0));
1646 OutStreamer.AddComment("eh_setjmp begin");
1647 OutStreamer.EmitInstruction(TmpInst);
1648 }
1649 {
1650 MCInst TmpInst;
Jim Grosbach7e3383c2010-10-27 23:12:14 +00001651 TmpInst.setOpcode(ARM::STRi12);
Jim Grosbach45390082010-09-23 23:33:56 +00001652 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1653 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
Jim Grosbach45390082010-09-23 23:33:56 +00001654 TmpInst.addOperand(MCOperand::CreateImm(4));
1655 // Predicate.
1656 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1657 TmpInst.addOperand(MCOperand::CreateReg(0));
1658 OutStreamer.EmitInstruction(TmpInst);
1659 }
1660 {
1661 MCInst TmpInst;
1662 TmpInst.setOpcode(ARM::MOVi);
1663 TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
1664 TmpInst.addOperand(MCOperand::CreateImm(0));
1665 // Predicate.
1666 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1667 TmpInst.addOperand(MCOperand::CreateReg(0));
1668 // 's' bit operand (always reg0 for this).
1669 TmpInst.addOperand(MCOperand::CreateReg(0));
1670 OutStreamer.EmitInstruction(TmpInst);
1671 }
1672 {
1673 MCInst TmpInst;
1674 TmpInst.setOpcode(ARM::ADDri);
1675 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1676 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1677 TmpInst.addOperand(MCOperand::CreateImm(0));
1678 // Predicate.
1679 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1680 TmpInst.addOperand(MCOperand::CreateReg(0));
1681 // 's' bit operand (always reg0 for this).
1682 TmpInst.addOperand(MCOperand::CreateReg(0));
1683 OutStreamer.EmitInstruction(TmpInst);
1684 }
1685 {
1686 MCInst TmpInst;
1687 TmpInst.setOpcode(ARM::MOVi);
1688 TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
1689 TmpInst.addOperand(MCOperand::CreateImm(1));
1690 // Predicate.
1691 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1692 TmpInst.addOperand(MCOperand::CreateReg(0));
1693 // 's' bit operand (always reg0 for this).
1694 TmpInst.addOperand(MCOperand::CreateReg(0));
1695 OutStreamer.AddComment("eh_setjmp end");
1696 OutStreamer.EmitInstruction(TmpInst);
1697 }
1698 return;
1699 }
Jim Grosbach5acb3de2010-09-27 21:47:04 +00001700 case ARM::Int_eh_sjlj_longjmp: {
1701 // ldr sp, [$src, #8]
1702 // ldr $scratch, [$src, #4]
1703 // ldr r7, [$src]
1704 // bx $scratch
1705 unsigned SrcReg = MI->getOperand(0).getReg();
1706 unsigned ScratchReg = MI->getOperand(1).getReg();
1707 {
1708 MCInst TmpInst;
Jim Grosbach3e556122010-10-26 22:37:02 +00001709 TmpInst.setOpcode(ARM::LDRi12);
Jim Grosbach5acb3de2010-09-27 21:47:04 +00001710 TmpInst.addOperand(MCOperand::CreateReg(ARM::SP));
1711 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
Jim Grosbach5acb3de2010-09-27 21:47:04 +00001712 TmpInst.addOperand(MCOperand::CreateImm(8));
1713 // Predicate.
1714 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1715 TmpInst.addOperand(MCOperand::CreateReg(0));
1716 OutStreamer.EmitInstruction(TmpInst);
1717 }
1718 {
1719 MCInst TmpInst;
Jim Grosbach3e556122010-10-26 22:37:02 +00001720 TmpInst.setOpcode(ARM::LDRi12);
Jim Grosbach5acb3de2010-09-27 21:47:04 +00001721 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1722 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
Jim Grosbach5acb3de2010-09-27 21:47:04 +00001723 TmpInst.addOperand(MCOperand::CreateImm(4));
1724 // Predicate.
1725 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1726 TmpInst.addOperand(MCOperand::CreateReg(0));
1727 OutStreamer.EmitInstruction(TmpInst);
1728 }
1729 {
1730 MCInst TmpInst;
Jim Grosbach3e556122010-10-26 22:37:02 +00001731 TmpInst.setOpcode(ARM::LDRi12);
Jim Grosbach5acb3de2010-09-27 21:47:04 +00001732 TmpInst.addOperand(MCOperand::CreateReg(ARM::R7));
1733 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
Jim Grosbach5acb3de2010-09-27 21:47:04 +00001734 TmpInst.addOperand(MCOperand::CreateImm(0));
1735 // Predicate.
1736 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1737 TmpInst.addOperand(MCOperand::CreateReg(0));
1738 OutStreamer.EmitInstruction(TmpInst);
1739 }
1740 {
1741 MCInst TmpInst;
Bill Wendling6e46d842010-11-30 00:48:15 +00001742 TmpInst.setOpcode(ARM::BX);
Jim Grosbach5acb3de2010-09-27 21:47:04 +00001743 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1744 // Predicate.
1745 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1746 TmpInst.addOperand(MCOperand::CreateReg(0));
1747 OutStreamer.EmitInstruction(TmpInst);
1748 }
1749 return;
1750 }
Jim Grosbach385cc5e2010-09-27 22:28:11 +00001751 case ARM::tInt_eh_sjlj_longjmp: {
1752 // ldr $scratch, [$src, #8]
1753 // mov sp, $scratch
1754 // ldr $scratch, [$src, #4]
1755 // ldr r7, [$src]
1756 // bx $scratch
1757 unsigned SrcReg = MI->getOperand(0).getReg();
1758 unsigned ScratchReg = MI->getOperand(1).getReg();
1759 {
1760 MCInst TmpInst;
Bill Wendlingf4caf692010-12-14 03:36:38 +00001761 TmpInst.setOpcode(ARM::tLDRi);
Jim Grosbach385cc5e2010-09-27 22:28:11 +00001762 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1763 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1764 // The offset immediate is #8. The operand value is scaled by 4 for the
Bill Wendlingf4caf692010-12-14 03:36:38 +00001765 // tLDR instruction.
Jim Grosbach385cc5e2010-09-27 22:28:11 +00001766 TmpInst.addOperand(MCOperand::CreateImm(2));
Jim Grosbach385cc5e2010-09-27 22:28:11 +00001767 // Predicate.
1768 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1769 TmpInst.addOperand(MCOperand::CreateReg(0));
1770 OutStreamer.EmitInstruction(TmpInst);
1771 }
1772 {
1773 MCInst TmpInst;
1774 TmpInst.setOpcode(ARM::tMOVtgpr2gpr);
1775 TmpInst.addOperand(MCOperand::CreateReg(ARM::SP));
1776 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1777 // Predicate.
1778 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1779 TmpInst.addOperand(MCOperand::CreateReg(0));
1780 OutStreamer.EmitInstruction(TmpInst);
1781 }
1782 {
1783 MCInst TmpInst;
Bill Wendlingf4caf692010-12-14 03:36:38 +00001784 TmpInst.setOpcode(ARM::tLDRi);
Jim Grosbach385cc5e2010-09-27 22:28:11 +00001785 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1786 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1787 TmpInst.addOperand(MCOperand::CreateImm(1));
Jim Grosbach385cc5e2010-09-27 22:28:11 +00001788 // Predicate.
1789 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1790 TmpInst.addOperand(MCOperand::CreateReg(0));
1791 OutStreamer.EmitInstruction(TmpInst);
1792 }
1793 {
1794 MCInst TmpInst;
Bill Wendlingf4caf692010-12-14 03:36:38 +00001795 TmpInst.setOpcode(ARM::tLDRr);
Jim Grosbach385cc5e2010-09-27 22:28:11 +00001796 TmpInst.addOperand(MCOperand::CreateReg(ARM::R7));
1797 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
Jim Grosbach385cc5e2010-09-27 22:28:11 +00001798 TmpInst.addOperand(MCOperand::CreateReg(0));
1799 // Predicate.
1800 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1801 TmpInst.addOperand(MCOperand::CreateReg(0));
1802 OutStreamer.EmitInstruction(TmpInst);
1803 }
1804 {
1805 MCInst TmpInst;
1806 TmpInst.setOpcode(ARM::tBX_RET_vararg);
1807 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1808 // Predicate.
1809 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1810 TmpInst.addOperand(MCOperand::CreateReg(0));
1811 OutStreamer.EmitInstruction(TmpInst);
1812 }
1813 return;
1814 }
Jim Grosbach5edf24e2011-03-15 00:30:40 +00001815 // Tail jump branches are really just branch instructions with additional
Chris Lattner7a2bdde2011-04-15 05:18:47 +00001816 // code-gen attributes. Convert them to the canonical form here.
Jim Grosbach5edf24e2011-03-15 00:30:40 +00001817 case ARM::TAILJMPd:
1818 case ARM::TAILJMPdND: {
1819 MCInst TmpInst, TmpInst2;
1820 // Lower the instruction as-is to get the operands properly converted.
1821 LowerARMMachineInstrToMCInst(MI, TmpInst2, *this);
1822 TmpInst.setOpcode(ARM::Bcc);
1823 TmpInst.addOperand(TmpInst2.getOperand(0));
1824 // Add predicate operands.
1825 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1826 TmpInst.addOperand(MCOperand::CreateReg(0));
1827 OutStreamer.AddComment("TAILCALL");
1828 OutStreamer.EmitInstruction(TmpInst);
1829 return;
1830 }
1831 case ARM::tTAILJMPd:
1832 case ARM::tTAILJMPdND: {
1833 MCInst TmpInst, TmpInst2;
1834 LowerARMMachineInstrToMCInst(MI, TmpInst2, *this);
Cameron Zwarichd34d4292011-05-23 01:57:17 +00001835 // The Darwin toolchain doesn't support tail call relocations of 16-bit
1836 // branches.
1837 TmpInst.setOpcode(Opc == ARM::tTAILJMPd ? ARM::t2B : ARM::tB);
Jim Grosbach5edf24e2011-03-15 00:30:40 +00001838 TmpInst.addOperand(TmpInst2.getOperand(0));
1839 OutStreamer.AddComment("TAILCALL");
1840 OutStreamer.EmitInstruction(TmpInst);
1841 return;
1842 }
1843 case ARM::TAILJMPrND:
1844 case ARM::tTAILJMPrND:
1845 case ARM::TAILJMPr:
1846 case ARM::tTAILJMPr: {
1847 unsigned newOpc = (Opc == ARM::TAILJMPr || Opc == ARM::TAILJMPrND)
1848 ? ARM::BX : ARM::tBX;
1849 MCInst TmpInst;
1850 TmpInst.setOpcode(newOpc);
1851 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1852 // Predicate.
1853 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1854 TmpInst.addOperand(MCOperand::CreateReg(0));
1855 OutStreamer.AddComment("TAILCALL");
1856 OutStreamer.EmitInstruction(TmpInst);
1857 return;
1858 }
1859
Anton Korobeynikov4d728602011-01-01 20:38:38 +00001860 // These are the pseudos created to comply with stricter operand restrictions
1861 // on ARMv5. Lower them now to "normal" instructions, since all the
1862 // restrictions are already satisfied.
1863 case ARM::MULv5:
1864 EmitPatchedInstruction(MI, ARM::MUL);
1865 return;
1866 case ARM::MLAv5:
1867 EmitPatchedInstruction(MI, ARM::MLA);
1868 return;
1869 case ARM::SMULLv5:
1870 EmitPatchedInstruction(MI, ARM::SMULL);
1871 return;
1872 case ARM::UMULLv5:
1873 EmitPatchedInstruction(MI, ARM::UMULL);
1874 return;
1875 case ARM::SMLALv5:
1876 EmitPatchedInstruction(MI, ARM::SMLAL);
1877 return;
1878 case ARM::UMLALv5:
1879 EmitPatchedInstruction(MI, ARM::UMLAL);
1880 return;
1881 case ARM::UMAALv5:
1882 EmitPatchedInstruction(MI, ARM::UMAAL);
1883 return;
Chris Lattner97f06932009-10-19 20:20:46 +00001884 }
Jim Grosbachb0739b72010-09-02 01:02:06 +00001885
Chris Lattner97f06932009-10-19 20:20:46 +00001886 MCInst TmpInst;
Chris Lattner30e2cc22010-11-14 21:00:02 +00001887 LowerARMMachineInstrToMCInst(MI, TmpInst, *this);
Anton Korobeynikov57caad72011-03-05 18:43:32 +00001888
1889 // Emit unwinding stuff for frame-related instructions
1890 if (EnableARMEHABI && MI->getFlag(MachineInstr::FrameSetup))
1891 EmitUnwindingInstruction(MI);
1892
Chris Lattner850d2e22010-02-03 01:16:28 +00001893 OutStreamer.EmitInstruction(TmpInst);
Chris Lattner97f06932009-10-19 20:20:46 +00001894}
Daniel Dunbar2685a292009-10-20 05:15:36 +00001895
1896//===----------------------------------------------------------------------===//
1897// Target Registry Stuff
1898//===----------------------------------------------------------------------===//
1899
1900static MCInstPrinter *createARMMCInstPrinter(const Target &T,
Bill Wendlinga5c177e2011-03-21 04:13:46 +00001901 TargetMachine &TM,
Daniel Dunbar2685a292009-10-20 05:15:36 +00001902 unsigned SyntaxVariant,
Chris Lattnerd3740872010-04-04 05:04:31 +00001903 const MCAsmInfo &MAI) {
Daniel Dunbar2685a292009-10-20 05:15:36 +00001904 if (SyntaxVariant == 0)
Bill Wendlinga5c177e2011-03-21 04:13:46 +00001905 return new ARMInstPrinter(TM, MAI);
Daniel Dunbar2685a292009-10-20 05:15:36 +00001906 return 0;
1907}
1908
1909// Force static initialization.
1910extern "C" void LLVMInitializeARMAsmPrinter() {
1911 RegisterAsmPrinter<ARMAsmPrinter> X(TheARMTarget);
1912 RegisterAsmPrinter<ARMAsmPrinter> Y(TheThumbTarget);
1913
1914 TargetRegistry::RegisterMCInstPrinter(TheARMTarget, createARMMCInstPrinter);
1915 TargetRegistry::RegisterMCInstPrinter(TheThumbTarget, createARMMCInstPrinter);
1916}
1917