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Chris Lattner1c08c712005-01-07 07:47:53 +00001//===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===//
Misha Brukmanedf128a2005-04-21 22:36:52 +00002//
Chris Lattner1c08c712005-01-07 07:47:53 +00003// The LLVM Compiler Infrastructure
4//
Chris Lattner4ee451d2007-12-29 20:36:04 +00005// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
Misha Brukmanedf128a2005-04-21 22:36:52 +00007//
Chris Lattner1c08c712005-01-07 07:47:53 +00008//===----------------------------------------------------------------------===//
9//
10// This implements the SelectionDAGISel class.
11//
12//===----------------------------------------------------------------------===//
13
14#define DEBUG_TYPE "isel"
Evan Cheng381cb072008-08-08 07:27:28 +000015#include "llvm/CodeGen/SelectionDAGISel.h"
Dan Gohmanf0cbcd42008-09-03 16:12:24 +000016#include "SelectionDAGBuild.h"
Anton Korobeynikov5502bf62007-04-04 21:14:49 +000017#include "llvm/ADT/BitVector.h"
Jim Laskeyc7c3f112006-10-16 20:52:31 +000018#include "llvm/Analysis/AliasAnalysis.h"
Anton Korobeynikov5502bf62007-04-04 21:14:49 +000019#include "llvm/Constants.h"
Chris Lattneradf6a962005-05-13 18:50:42 +000020#include "llvm/CallingConv.h"
Chris Lattner1c08c712005-01-07 07:47:53 +000021#include "llvm/DerivedTypes.h"
22#include "llvm/Function.h"
Chris Lattner36ce6912005-11-29 06:21:05 +000023#include "llvm/GlobalVariable.h"
Chris Lattnerce7518c2006-01-26 22:24:51 +000024#include "llvm/InlineAsm.h"
Chris Lattner1c08c712005-01-07 07:47:53 +000025#include "llvm/Instructions.h"
26#include "llvm/Intrinsics.h"
Jim Laskey43970fe2006-03-23 18:06:46 +000027#include "llvm/IntrinsicInst.h"
Reid Spencer5694b6e2007-04-09 06:17:21 +000028#include "llvm/ParameterAttributes.h"
Dan Gohman78eca172008-08-19 22:33:34 +000029#include "llvm/CodeGen/FastISel.h"
Gordon Henriksen5a29c9e2008-08-17 12:56:54 +000030#include "llvm/CodeGen/GCStrategy.h"
Gordon Henriksen5eca0752008-08-17 18:44:35 +000031#include "llvm/CodeGen/GCMetadata.h"
Chris Lattner1c08c712005-01-07 07:47:53 +000032#include "llvm/CodeGen/MachineFunction.h"
33#include "llvm/CodeGen/MachineFrameInfo.h"
34#include "llvm/CodeGen/MachineInstrBuilder.h"
Chris Lattner84bc5422007-12-31 04:13:23 +000035#include "llvm/CodeGen/MachineJumpTableInfo.h"
36#include "llvm/CodeGen/MachineModuleInfo.h"
37#include "llvm/CodeGen/MachineRegisterInfo.h"
Evan Cheng381cb072008-08-08 07:27:28 +000038#include "llvm/CodeGen/ScheduleDAG.h"
Jim Laskeyeb577ba2006-08-02 12:30:23 +000039#include "llvm/CodeGen/SchedulerRegistry.h"
Chris Lattner1c08c712005-01-07 07:47:53 +000040#include "llvm/CodeGen/SelectionDAG.h"
Dan Gohman6f0d0242008-02-10 18:45:23 +000041#include "llvm/Target/TargetRegisterInfo.h"
Chris Lattner1c08c712005-01-07 07:47:53 +000042#include "llvm/Target/TargetData.h"
43#include "llvm/Target/TargetFrameInfo.h"
44#include "llvm/Target/TargetInstrInfo.h"
45#include "llvm/Target/TargetLowering.h"
46#include "llvm/Target/TargetMachine.h"
Vladimir Prus12472912006-05-23 13:43:15 +000047#include "llvm/Target/TargetOptions.h"
Chris Lattnera4f0b3a2006-08-27 12:54:02 +000048#include "llvm/Support/Compiler.h"
Evan Chengdb8d56b2008-06-30 20:45:06 +000049#include "llvm/Support/Debug.h"
50#include "llvm/Support/MathExtras.h"
51#include "llvm/Support/Timer.h"
Jeff Cohen7e881032006-02-24 02:52:40 +000052#include <algorithm>
Chris Lattner1c08c712005-01-07 07:47:53 +000053using namespace llvm;
54
Chris Lattneread0d882008-06-17 06:09:18 +000055static cl::opt<bool>
Chris Lattner70587ea2008-07-10 23:37:50 +000056EnableValueProp("enable-value-prop", cl::Hidden);
57static cl::opt<bool>
Duncan Sandsf00e74f2008-07-17 17:06:03 +000058EnableLegalizeTypes("enable-legalize-types", cl::Hidden);
Dan Gohman78eca172008-08-19 22:33:34 +000059static cl::opt<bool>
60EnableFastISel("fast-isel", cl::Hidden,
61 cl::desc("Enable the experimental \"fast\" instruction selector"));
Dan Gohman3e697cf2008-08-20 00:47:54 +000062static cl::opt<bool>
Dan Gohman293d5f82008-09-09 22:06:46 +000063EnableFastISelVerbose("fast-isel-verbose", cl::Hidden,
64 cl::desc("Enable verbose messages in the experimental \"fast\" "
65 "instruction selector"));
66static cl::opt<bool>
Dan Gohman4344a5d2008-09-09 23:05:00 +000067EnableFastISelAbort("fast-isel-abort", cl::Hidden,
68 cl::desc("Enable abort calls when \"fast\" instruction fails"));
Dan Gohman8a110532008-09-05 22:59:21 +000069static cl::opt<bool>
70SchedLiveInCopies("schedule-livein-copies",
71 cl::desc("Schedule copies of livein registers"),
72 cl::init(false));
Chris Lattneread0d882008-06-17 06:09:18 +000073
Chris Lattnerda8abb02005-09-01 18:44:10 +000074#ifndef NDEBUG
Chris Lattner7944d9d2005-01-12 03:41:21 +000075static cl::opt<bool>
Dan Gohman462dc7f2008-07-21 20:00:07 +000076ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden,
77 cl::desc("Pop up a window to show dags before the first "
78 "dag combine pass"));
79static cl::opt<bool>
80ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden,
81 cl::desc("Pop up a window to show dags before legalize types"));
82static cl::opt<bool>
83ViewLegalizeDAGs("view-legalize-dags", cl::Hidden,
84 cl::desc("Pop up a window to show dags before legalize"));
85static cl::opt<bool>
86ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden,
87 cl::desc("Pop up a window to show dags before the second "
88 "dag combine pass"));
89static cl::opt<bool>
Evan Chenga9c20912006-01-21 02:32:06 +000090ViewISelDAGs("view-isel-dags", cl::Hidden,
91 cl::desc("Pop up a window to show isel dags as they are selected"));
92static cl::opt<bool>
93ViewSchedDAGs("view-sched-dags", cl::Hidden,
94 cl::desc("Pop up a window to show sched dags as they are processed"));
Dan Gohman3e1a7ae2007-08-28 20:32:58 +000095static cl::opt<bool>
96ViewSUnitDAGs("view-sunit-dags", cl::Hidden,
Chris Lattner5bab7852008-01-25 17:24:52 +000097 cl::desc("Pop up a window to show SUnit dags after they are processed"));
Chris Lattner7944d9d2005-01-12 03:41:21 +000098#else
Dan Gohman462dc7f2008-07-21 20:00:07 +000099static const bool ViewDAGCombine1 = false,
100 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false,
101 ViewDAGCombine2 = false,
102 ViewISelDAGs = false, ViewSchedDAGs = false,
103 ViewSUnitDAGs = false;
Chris Lattner7944d9d2005-01-12 03:41:21 +0000104#endif
105
Jim Laskeyeb577ba2006-08-02 12:30:23 +0000106//===---------------------------------------------------------------------===//
107///
108/// RegisterScheduler class - Track the registration of instruction schedulers.
109///
110//===---------------------------------------------------------------------===//
111MachinePassRegistry RegisterScheduler::Registry;
112
113//===---------------------------------------------------------------------===//
114///
115/// ISHeuristic command line option for instruction schedulers.
116///
117//===---------------------------------------------------------------------===//
Dan Gohman844731a2008-05-13 00:00:25 +0000118static cl::opt<RegisterScheduler::FunctionPassCtor, false,
119 RegisterPassParser<RegisterScheduler> >
120ISHeuristic("pre-RA-sched",
121 cl::init(&createDefaultScheduler),
122 cl::desc("Instruction schedulers available (before register"
123 " allocation):"));
Jim Laskey13ec7022006-08-01 14:21:23 +0000124
Dan Gohman844731a2008-05-13 00:00:25 +0000125static RegisterScheduler
126defaultListDAGScheduler("default", " Best scheduler for the target",
127 createDefaultScheduler);
Evan Cheng4ef10862006-01-23 07:01:07 +0000128
Chris Lattner1c08c712005-01-07 07:47:53 +0000129namespace llvm {
130 //===--------------------------------------------------------------------===//
Jim Laskey9373beb2006-08-01 19:14:14 +0000131 /// createDefaultScheduler - This creates an instruction scheduler appropriate
132 /// for the target.
133 ScheduleDAG* createDefaultScheduler(SelectionDAGISel *IS,
134 SelectionDAG *DAG,
Evan Cheng4576f6d2008-07-01 18:05:03 +0000135 MachineBasicBlock *BB,
136 bool Fast) {
Jim Laskey9373beb2006-08-01 19:14:14 +0000137 TargetLowering &TLI = IS->getTargetLowering();
138
139 if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency) {
Evan Cheng4576f6d2008-07-01 18:05:03 +0000140 return createTDListDAGScheduler(IS, DAG, BB, Fast);
Jim Laskey9373beb2006-08-01 19:14:14 +0000141 } else {
142 assert(TLI.getSchedulingPreference() ==
143 TargetLowering::SchedulingForRegPressure && "Unknown sched type!");
Evan Cheng4576f6d2008-07-01 18:05:03 +0000144 return createBURRListDAGScheduler(IS, DAG, BB, Fast);
Jim Laskey9373beb2006-08-01 19:14:14 +0000145 }
146 }
Chris Lattner1c08c712005-01-07 07:47:53 +0000147}
148
Evan Chengff9b3732008-01-30 18:18:23 +0000149// EmitInstrWithCustomInserter - This method should be implemented by targets
150// that mark instructions with the 'usesCustomDAGSchedInserter' flag. These
Chris Lattner025c39b2005-08-26 20:54:47 +0000151// instructions are special in various ways, which require special support to
152// insert. The specified MachineInstr is created but not inserted into any
153// basic blocks, and the scheduler passes ownership of it to this method.
Evan Chengff9b3732008-01-30 18:18:23 +0000154MachineBasicBlock *TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
Chris Lattner025c39b2005-08-26 20:54:47 +0000155 MachineBasicBlock *MBB) {
Bill Wendling832171c2006-12-07 20:04:42 +0000156 cerr << "If a target marks an instruction with "
157 << "'usesCustomDAGSchedInserter', it must implement "
Evan Chengff9b3732008-01-30 18:18:23 +0000158 << "TargetLowering::EmitInstrWithCustomInserter!\n";
Chris Lattner025c39b2005-08-26 20:54:47 +0000159 abort();
160 return 0;
161}
162
Dan Gohman8a110532008-09-05 22:59:21 +0000163/// EmitLiveInCopy - Emit a copy for a live in physical register. If the
164/// physical register has only a single copy use, then coalesced the copy
165/// if possible.
166static void EmitLiveInCopy(MachineBasicBlock *MBB,
167 MachineBasicBlock::iterator &InsertPos,
168 unsigned VirtReg, unsigned PhysReg,
169 const TargetRegisterClass *RC,
170 DenseMap<MachineInstr*, unsigned> &CopyRegMap,
171 const MachineRegisterInfo &MRI,
172 const TargetRegisterInfo &TRI,
173 const TargetInstrInfo &TII) {
174 unsigned NumUses = 0;
175 MachineInstr *UseMI = NULL;
176 for (MachineRegisterInfo::use_iterator UI = MRI.use_begin(VirtReg),
177 UE = MRI.use_end(); UI != UE; ++UI) {
178 UseMI = &*UI;
179 if (++NumUses > 1)
180 break;
181 }
182
183 // If the number of uses is not one, or the use is not a move instruction,
184 // don't coalesce. Also, only coalesce away a virtual register to virtual
185 // register copy.
186 bool Coalesced = false;
187 unsigned SrcReg, DstReg;
188 if (NumUses == 1 &&
189 TII.isMoveInstr(*UseMI, SrcReg, DstReg) &&
190 TargetRegisterInfo::isVirtualRegister(DstReg)) {
191 VirtReg = DstReg;
192 Coalesced = true;
193 }
194
195 // Now find an ideal location to insert the copy.
196 MachineBasicBlock::iterator Pos = InsertPos;
197 while (Pos != MBB->begin()) {
198 MachineInstr *PrevMI = prior(Pos);
199 DenseMap<MachineInstr*, unsigned>::iterator RI = CopyRegMap.find(PrevMI);
200 // copyRegToReg might emit multiple instructions to do a copy.
201 unsigned CopyDstReg = (RI == CopyRegMap.end()) ? 0 : RI->second;
202 if (CopyDstReg && !TRI.regsOverlap(CopyDstReg, PhysReg))
203 // This is what the BB looks like right now:
204 // r1024 = mov r0
205 // ...
206 // r1 = mov r1024
207 //
208 // We want to insert "r1025 = mov r1". Inserting this copy below the
209 // move to r1024 makes it impossible for that move to be coalesced.
210 //
211 // r1025 = mov r1
212 // r1024 = mov r0
213 // ...
214 // r1 = mov 1024
215 // r2 = mov 1025
216 break; // Woot! Found a good location.
217 --Pos;
218 }
219
220 TII.copyRegToReg(*MBB, Pos, VirtReg, PhysReg, RC, RC);
221 CopyRegMap.insert(std::make_pair(prior(Pos), VirtReg));
222 if (Coalesced) {
223 if (&*InsertPos == UseMI) ++InsertPos;
224 MBB->erase(UseMI);
225 }
226}
227
228/// EmitLiveInCopies - If this is the first basic block in the function,
229/// and if it has live ins that need to be copied into vregs, emit the
230/// copies into the block.
231static void EmitLiveInCopies(MachineBasicBlock *EntryMBB,
232 const MachineRegisterInfo &MRI,
233 const TargetRegisterInfo &TRI,
234 const TargetInstrInfo &TII) {
235 if (SchedLiveInCopies) {
236 // Emit the copies at a heuristically-determined location in the block.
237 DenseMap<MachineInstr*, unsigned> CopyRegMap;
238 MachineBasicBlock::iterator InsertPos = EntryMBB->begin();
239 for (MachineRegisterInfo::livein_iterator LI = MRI.livein_begin(),
240 E = MRI.livein_end(); LI != E; ++LI)
241 if (LI->second) {
242 const TargetRegisterClass *RC = MRI.getRegClass(LI->second);
243 EmitLiveInCopy(EntryMBB, InsertPos, LI->second, LI->first,
244 RC, CopyRegMap, MRI, TRI, TII);
245 }
246 } else {
247 // Emit the copies into the top of the block.
248 for (MachineRegisterInfo::livein_iterator LI = MRI.livein_begin(),
249 E = MRI.livein_end(); LI != E; ++LI)
250 if (LI->second) {
251 const TargetRegisterClass *RC = MRI.getRegClass(LI->second);
252 TII.copyRegToReg(*EntryMBB, EntryMBB->begin(),
253 LI->second, LI->first, RC, RC);
254 }
255 }
256}
257
Chris Lattner7041ee32005-01-11 05:56:49 +0000258//===----------------------------------------------------------------------===//
259// SelectionDAGISel code
260//===----------------------------------------------------------------------===//
Chris Lattner1c08c712005-01-07 07:47:53 +0000261
Dan Gohman7c3234c2008-08-27 23:52:12 +0000262SelectionDAGISel::SelectionDAGISel(TargetLowering &tli, bool fast) :
Dan Gohmanae73dc12008-09-04 17:05:41 +0000263 FunctionPass(&ID), TLI(tli),
Dan Gohman7c3234c2008-08-27 23:52:12 +0000264 FuncInfo(new FunctionLoweringInfo(TLI)),
265 CurDAG(new SelectionDAG(TLI, *FuncInfo)),
266 SDL(new SelectionDAGLowering(*CurDAG, TLI, *FuncInfo)),
267 GFI(),
268 Fast(fast),
269 DAGSize(0)
270{}
271
272SelectionDAGISel::~SelectionDAGISel() {
273 delete SDL;
274 delete CurDAG;
275 delete FuncInfo;
276}
277
Duncan Sands83ec4b62008-06-06 12:08:01 +0000278unsigned SelectionDAGISel::MakeReg(MVT VT) {
Chris Lattner84bc5422007-12-31 04:13:23 +0000279 return RegInfo->createVirtualRegister(TLI.getRegClassFor(VT));
Chris Lattner1c08c712005-01-07 07:47:53 +0000280}
281
Chris Lattner495a0b52005-08-17 06:37:43 +0000282void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
Jim Laskeyc7c3f112006-10-16 20:52:31 +0000283 AU.addRequired<AliasAnalysis>();
Gordon Henriksen5eca0752008-08-17 18:44:35 +0000284 AU.addRequired<GCModuleInfo>();
Chris Lattnerc8d288f2007-03-31 04:18:03 +0000285 AU.setPreservesAll();
Chris Lattner495a0b52005-08-17 06:37:43 +0000286}
Chris Lattner1c08c712005-01-07 07:47:53 +0000287
Chris Lattner1c08c712005-01-07 07:47:53 +0000288bool SelectionDAGISel::runOnFunction(Function &Fn) {
Dan Gohman4344a5d2008-09-09 23:05:00 +0000289 // Do some sanity-checking on the command-line options.
290 assert((!EnableFastISelVerbose || EnableFastISel) &&
291 "-fast-isel-verbose requires -fast-isel");
292 assert((!EnableFastISelAbort || EnableFastISel) &&
293 "-fast-isel-abort requires -fast-isel");
294
Dan Gohman5f43f922007-08-27 16:26:13 +0000295 // Get alias analysis for load/store combining.
296 AA = &getAnalysis<AliasAnalysis>();
297
Dan Gohman8a110532008-09-05 22:59:21 +0000298 TargetMachine &TM = TLI.getTargetMachine();
299 MachineFunction &MF = MachineFunction::construct(&Fn, TM);
300 const MachineRegisterInfo &MRI = MF.getRegInfo();
301 const TargetInstrInfo &TII = *TM.getInstrInfo();
302 const TargetRegisterInfo &TRI = *TM.getRegisterInfo();
303
Gordon Henriksen5eca0752008-08-17 18:44:35 +0000304 if (MF.getFunction()->hasGC())
305 GFI = &getAnalysis<GCModuleInfo>().getFunctionInfo(*MF.getFunction());
Gordon Henriksence224772008-01-07 01:30:38 +0000306 else
Gordon Henriksen5eca0752008-08-17 18:44:35 +0000307 GFI = 0;
Chris Lattner84bc5422007-12-31 04:13:23 +0000308 RegInfo = &MF.getRegInfo();
Bill Wendling832171c2006-12-07 20:04:42 +0000309 DOUT << "\n\n\n=== " << Fn.getName() << "\n";
Chris Lattner1c08c712005-01-07 07:47:53 +0000310
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000311 FuncInfo->set(Fn, MF, EnableFastISel);
Dan Gohman7c3234c2008-08-27 23:52:12 +0000312 CurDAG->init(MF, getAnalysisToUpdate<MachineModuleInfo>());
313 SDL->init(GFI, *AA);
Chris Lattner1c08c712005-01-07 07:47:53 +0000314
Dale Johannesen1532f3d2008-04-02 00:25:04 +0000315 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
316 if (InvokeInst *Invoke = dyn_cast<InvokeInst>(I->getTerminator()))
317 // Mark landing pad.
Dan Gohman7c3234c2008-08-27 23:52:12 +0000318 FuncInfo->MBBMap[Invoke->getSuccessor(1)]->setIsLandingPad();
Duncan Sands9fac0b52007-06-06 10:05:18 +0000319
Dan Gohman7c3234c2008-08-27 23:52:12 +0000320 SelectAllBasicBlocks(Fn, MF);
Misha Brukmanedf128a2005-04-21 22:36:52 +0000321
Dan Gohman8a110532008-09-05 22:59:21 +0000322 // If the first basic block in the function has live ins that need to be
323 // copied into vregs, emit the copies into the top of the block before
324 // emitting the code for the block.
325 EmitLiveInCopies(MF.begin(), MRI, TRI, TII);
326
Evan Chengad2070c2007-02-10 02:43:39 +0000327 // Add function live-ins to entry block live-in set.
Dan Gohman8a110532008-09-05 22:59:21 +0000328 for (MachineRegisterInfo::livein_iterator I = RegInfo->livein_begin(),
329 E = RegInfo->livein_end(); I != E; ++I)
330 MF.begin()->addLiveIn(I->first);
Evan Chengad2070c2007-02-10 02:43:39 +0000331
Duncan Sandsf4070822007-06-15 19:04:19 +0000332#ifndef NDEBUG
Dan Gohman7c3234c2008-08-27 23:52:12 +0000333 assert(FuncInfo->CatchInfoFound.size() == FuncInfo->CatchInfoLost.size() &&
Duncan Sandsf4070822007-06-15 19:04:19 +0000334 "Not all catch info was assigned to a landing pad!");
335#endif
336
Dan Gohman7c3234c2008-08-27 23:52:12 +0000337 FuncInfo->clear();
338
Chris Lattner1c08c712005-01-07 07:47:53 +0000339 return true;
340}
341
Duncan Sandsf4070822007-06-15 19:04:19 +0000342static void copyCatchInfo(BasicBlock *SrcBB, BasicBlock *DestBB,
343 MachineModuleInfo *MMI, FunctionLoweringInfo &FLI) {
Duncan Sandsf4070822007-06-15 19:04:19 +0000344 for (BasicBlock::iterator I = SrcBB->begin(), E = --SrcBB->end(); I != E; ++I)
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000345 if (EHSelectorInst *EHSel = dyn_cast<EHSelectorInst>(I)) {
Duncan Sandsf4070822007-06-15 19:04:19 +0000346 // Apply the catch info to DestBB.
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000347 AddCatchInfo(*EHSel, MMI, FLI.MBBMap[DestBB]);
Duncan Sandsf4070822007-06-15 19:04:19 +0000348#ifndef NDEBUG
Duncan Sands560a7372007-11-15 09:54:37 +0000349 if (!FLI.MBBMap[SrcBB]->isLandingPad())
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000350 FLI.CatchInfoFound.insert(EHSel);
Duncan Sandsf4070822007-06-15 19:04:19 +0000351#endif
352 }
353}
354
Arnold Schwaighofer30e62c02008-04-30 09:16:33 +0000355/// IsFixedFrameObjectWithPosOffset - Check if object is a fixed frame object and
356/// whether object offset >= 0.
357static bool
Dan Gohman475871a2008-07-27 21:46:04 +0000358IsFixedFrameObjectWithPosOffset(MachineFrameInfo * MFI, SDValue Op) {
Arnold Schwaighofer30e62c02008-04-30 09:16:33 +0000359 if (!isa<FrameIndexSDNode>(Op)) return false;
360
361 FrameIndexSDNode * FrameIdxNode = dyn_cast<FrameIndexSDNode>(Op);
362 int FrameIdx = FrameIdxNode->getIndex();
363 return MFI->isFixedObjectIndex(FrameIdx) &&
364 MFI->getObjectOffset(FrameIdx) >= 0;
365}
366
367/// IsPossiblyOverwrittenArgumentOfTailCall - Check if the operand could
368/// possibly be overwritten when lowering the outgoing arguments in a tail
369/// call. Currently the implementation of this call is very conservative and
370/// assumes all arguments sourcing from FORMAL_ARGUMENTS or a CopyFromReg with
371/// virtual registers would be overwritten by direct lowering.
Dan Gohman475871a2008-07-27 21:46:04 +0000372static bool IsPossiblyOverwrittenArgumentOfTailCall(SDValue Op,
Arnold Schwaighofer30e62c02008-04-30 09:16:33 +0000373 MachineFrameInfo * MFI) {
374 RegisterSDNode * OpReg = NULL;
375 if (Op.getOpcode() == ISD::FORMAL_ARGUMENTS ||
376 (Op.getOpcode()== ISD::CopyFromReg &&
377 (OpReg = dyn_cast<RegisterSDNode>(Op.getOperand(1))) &&
378 (OpReg->getReg() >= TargetRegisterInfo::FirstVirtualRegister)) ||
379 (Op.getOpcode() == ISD::LOAD &&
380 IsFixedFrameObjectWithPosOffset(MFI, Op.getOperand(1))) ||
381 (Op.getOpcode() == ISD::MERGE_VALUES &&
Gabor Greif99a6cb92008-08-26 22:36:50 +0000382 Op.getOperand(Op.getResNo()).getOpcode() == ISD::LOAD &&
383 IsFixedFrameObjectWithPosOffset(MFI, Op.getOperand(Op.getResNo()).
Arnold Schwaighofer30e62c02008-04-30 09:16:33 +0000384 getOperand(1))))
385 return true;
386 return false;
387}
388
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +0000389/// CheckDAGForTailCallsAndFixThem - This Function looks for CALL nodes in the
Arnold Schwaighofer48abc5c2007-10-12 21:30:57 +0000390/// DAG and fixes their tailcall attribute operand.
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +0000391static void CheckDAGForTailCallsAndFixThem(SelectionDAG &DAG,
392 TargetLowering& TLI) {
393 SDNode * Ret = NULL;
Dan Gohman475871a2008-07-27 21:46:04 +0000394 SDValue Terminator = DAG.getRoot();
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +0000395
396 // Find RET node.
397 if (Terminator.getOpcode() == ISD::RET) {
Gabor Greifba36cb52008-08-28 21:40:38 +0000398 Ret = Terminator.getNode();
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +0000399 }
400
401 // Fix tail call attribute of CALL nodes.
402 for (SelectionDAG::allnodes_iterator BE = DAG.allnodes_begin(),
Dan Gohman0e5f1302008-07-07 23:02:41 +0000403 BI = DAG.allnodes_end(); BI != BE; ) {
404 --BI;
Dan Gohman095cc292008-09-13 01:54:27 +0000405 if (CallSDNode *TheCall = dyn_cast<CallSDNode>(BI)) {
Dan Gohman475871a2008-07-27 21:46:04 +0000406 SDValue OpRet(Ret, 0);
407 SDValue OpCall(BI, 0);
Dan Gohman095cc292008-09-13 01:54:27 +0000408 bool isMarkedTailCall = TheCall->isTailCall();
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +0000409 // If CALL node has tail call attribute set to true and the call is not
410 // eligible (no RET or the target rejects) the attribute is fixed to
Arnold Schwaighofer48abc5c2007-10-12 21:30:57 +0000411 // false. The TargetLowering::IsEligibleForTailCallOptimization function
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +0000412 // must correctly identify tail call optimizable calls.
Arnold Schwaighofer30e62c02008-04-30 09:16:33 +0000413 if (!isMarkedTailCall) continue;
414 if (Ret==NULL ||
Dan Gohman095cc292008-09-13 01:54:27 +0000415 !TLI.IsEligibleForTailCallOptimization(TheCall, OpRet, DAG)) {
416 // Not eligible. Mark CALL node as non tail call. Note that we
417 // can modify the call node in place since calls are not CSE'd.
418 TheCall->setNotTailCall();
Arnold Schwaighofer30e62c02008-04-30 09:16:33 +0000419 } else {
420 // Look for tail call clobbered arguments. Emit a series of
421 // copyto/copyfrom virtual register nodes to protect them.
Dan Gohman475871a2008-07-27 21:46:04 +0000422 SmallVector<SDValue, 32> Ops;
Dan Gohman095cc292008-09-13 01:54:27 +0000423 SDValue Chain = TheCall->getChain(), InFlag;
424 Ops.push_back(Chain);
425 Ops.push_back(TheCall->getCallee());
426 for (unsigned i = 0, e = TheCall->getNumArgs(); i != e; ++i) {
427 SDValue Arg = TheCall->getArg(i);
428 bool isByVal = TheCall->getArgFlags(i).isByVal();
429 MachineFunction &MF = DAG.getMachineFunction();
430 MachineFrameInfo *MFI = MF.getFrameInfo();
431 if (!isByVal &&
432 IsPossiblyOverwrittenArgumentOfTailCall(Arg, MFI)) {
433 MVT VT = Arg.getValueType();
434 unsigned VReg = MF.getRegInfo().
435 createVirtualRegister(TLI.getRegClassFor(VT));
436 Chain = DAG.getCopyToReg(Chain, VReg, Arg, InFlag);
437 InFlag = Chain.getValue(1);
438 Arg = DAG.getCopyFromReg(Chain, VReg, VT, InFlag);
439 Chain = Arg.getValue(1);
440 InFlag = Arg.getValue(2);
Arnold Schwaighofer30e62c02008-04-30 09:16:33 +0000441 }
442 Ops.push_back(Arg);
Dan Gohman095cc292008-09-13 01:54:27 +0000443 Ops.push_back(TheCall->getArgFlagsVal(i));
Arnold Schwaighofer30e62c02008-04-30 09:16:33 +0000444 }
445 // Link in chain of CopyTo/CopyFromReg.
446 Ops[0] = Chain;
447 DAG.UpdateNodeOperands(OpCall, Ops.begin(), Ops.size());
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +0000448 }
449 }
450 }
451}
452
Dan Gohmanf350b272008-08-23 02:25:05 +0000453void SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB,
454 BasicBlock::iterator Begin,
Dan Gohman5edd3612008-08-28 20:28:56 +0000455 BasicBlock::iterator End) {
Dan Gohman7c3234c2008-08-27 23:52:12 +0000456 SDL->setCurrentBasicBlock(BB);
Dan Gohmanf350b272008-08-23 02:25:05 +0000457
458 MachineModuleInfo *MMI = CurDAG->getMachineModuleInfo();
459
460 if (MMI && BB->isLandingPad()) {
461 // Add a label to mark the beginning of the landing pad. Deletion of the
462 // landing pad can thus be detected via the MachineModuleInfo.
463 unsigned LabelID = MMI->addLandingPad(BB);
464 CurDAG->setRoot(CurDAG->getLabel(ISD::EH_LABEL,
465 CurDAG->getEntryNode(), LabelID));
466
467 // Mark exception register as live in.
468 unsigned Reg = TLI.getExceptionAddressRegister();
469 if (Reg) BB->addLiveIn(Reg);
470
471 // Mark exception selector register as live in.
472 Reg = TLI.getExceptionSelectorRegister();
473 if (Reg) BB->addLiveIn(Reg);
474
475 // FIXME: Hack around an exception handling flaw (PR1508): the personality
476 // function and list of typeids logically belong to the invoke (or, if you
477 // like, the basic block containing the invoke), and need to be associated
478 // with it in the dwarf exception handling tables. Currently however the
479 // information is provided by an intrinsic (eh.selector) that can be moved
480 // to unexpected places by the optimizers: if the unwind edge is critical,
481 // then breaking it can result in the intrinsics being in the successor of
482 // the landing pad, not the landing pad itself. This results in exceptions
483 // not being caught because no typeids are associated with the invoke.
484 // This may not be the only way things can go wrong, but it is the only way
485 // we try to work around for the moment.
486 BranchInst *Br = dyn_cast<BranchInst>(LLVMBB->getTerminator());
487
488 if (Br && Br->isUnconditional()) { // Critical edge?
489 BasicBlock::iterator I, E;
490 for (I = LLVMBB->begin(), E = --LLVMBB->end(); I != E; ++I)
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000491 if (isa<EHSelectorInst>(I))
Dan Gohmanf350b272008-08-23 02:25:05 +0000492 break;
493
494 if (I == E)
495 // No catch info found - try to extract some from the successor.
Dan Gohman7c3234c2008-08-27 23:52:12 +0000496 copyCatchInfo(Br->getSuccessor(0), LLVMBB, MMI, *FuncInfo);
Dan Gohmanf350b272008-08-23 02:25:05 +0000497 }
498 }
499
500 // Lower all of the non-terminator instructions.
501 for (BasicBlock::iterator I = Begin; I != End; ++I)
502 if (!isa<TerminatorInst>(I))
Dan Gohman7c3234c2008-08-27 23:52:12 +0000503 SDL->visit(*I);
Dan Gohmanf350b272008-08-23 02:25:05 +0000504
505 // Ensure that all instructions which are used outside of their defining
506 // blocks are available as virtual registers. Invoke is handled elsewhere.
507 for (BasicBlock::iterator I = Begin; I != End; ++I)
508 if (!I->use_empty() && !isa<PHINode>(I) && !isa<InvokeInst>(I)) {
Dan Gohman7c3234c2008-08-27 23:52:12 +0000509 DenseMap<const Value*,unsigned>::iterator VMI =FuncInfo->ValueMap.find(I);
510 if (VMI != FuncInfo->ValueMap.end())
511 SDL->CopyValueToVirtualRegister(I, VMI->second);
Dan Gohmanf350b272008-08-23 02:25:05 +0000512 }
513
514 // Handle PHI nodes in successor blocks.
Dan Gohman3df24e62008-09-03 23:12:08 +0000515 if (End == LLVMBB->end()) {
Dan Gohman7c3234c2008-08-27 23:52:12 +0000516 HandlePHINodesInSuccessorBlocks(LLVMBB);
Dan Gohman3df24e62008-09-03 23:12:08 +0000517
518 // Lower the terminator after the copies are emitted.
519 SDL->visit(*LLVMBB->getTerminator());
520 }
Anton Korobeynikov4198c582007-04-09 12:31:58 +0000521
Chris Lattnera651cf62005-01-17 19:43:36 +0000522 // Make sure the root of the DAG is up-to-date.
Dan Gohman7c3234c2008-08-27 23:52:12 +0000523 CurDAG->setRoot(SDL->getControlRoot());
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +0000524
525 // Check whether calls in this block are real tail calls. Fix up CALL nodes
526 // with correct tailcall attribute so that the target can rely on the tailcall
527 // attribute indicating whether the call is really eligible for tail call
528 // optimization.
Dan Gohman1937e2f2008-09-16 01:42:28 +0000529 if (PerformTailCallOpt)
530 CheckDAGForTailCallsAndFixThem(*CurDAG, TLI);
Dan Gohmanf350b272008-08-23 02:25:05 +0000531
532 // Final step, emit the lowered DAG as machine code.
533 CodeGenAndEmitDAG();
Dan Gohman7c3234c2008-08-27 23:52:12 +0000534 SDL->clear();
Chris Lattner1c08c712005-01-07 07:47:53 +0000535}
536
Dan Gohmanf350b272008-08-23 02:25:05 +0000537void SelectionDAGISel::ComputeLiveOutVRegInfo() {
Chris Lattneread0d882008-06-17 06:09:18 +0000538 SmallPtrSet<SDNode*, 128> VisitedNodes;
539 SmallVector<SDNode*, 128> Worklist;
540
Gabor Greifba36cb52008-08-28 21:40:38 +0000541 Worklist.push_back(CurDAG->getRoot().getNode());
Chris Lattneread0d882008-06-17 06:09:18 +0000542
543 APInt Mask;
544 APInt KnownZero;
545 APInt KnownOne;
546
547 while (!Worklist.empty()) {
548 SDNode *N = Worklist.back();
549 Worklist.pop_back();
550
551 // If we've already seen this node, ignore it.
552 if (!VisitedNodes.insert(N))
553 continue;
554
555 // Otherwise, add all chain operands to the worklist.
556 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
557 if (N->getOperand(i).getValueType() == MVT::Other)
Gabor Greifba36cb52008-08-28 21:40:38 +0000558 Worklist.push_back(N->getOperand(i).getNode());
Chris Lattneread0d882008-06-17 06:09:18 +0000559
560 // If this is a CopyToReg with a vreg dest, process it.
561 if (N->getOpcode() != ISD::CopyToReg)
562 continue;
563
564 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg();
565 if (!TargetRegisterInfo::isVirtualRegister(DestReg))
566 continue;
567
568 // Ignore non-scalar or non-integer values.
Dan Gohman475871a2008-07-27 21:46:04 +0000569 SDValue Src = N->getOperand(2);
Chris Lattneread0d882008-06-17 06:09:18 +0000570 MVT SrcVT = Src.getValueType();
571 if (!SrcVT.isInteger() || SrcVT.isVector())
572 continue;
573
Dan Gohmanf350b272008-08-23 02:25:05 +0000574 unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src);
Chris Lattneread0d882008-06-17 06:09:18 +0000575 Mask = APInt::getAllOnesValue(SrcVT.getSizeInBits());
Dan Gohmanf350b272008-08-23 02:25:05 +0000576 CurDAG->ComputeMaskedBits(Src, Mask, KnownZero, KnownOne);
Chris Lattneread0d882008-06-17 06:09:18 +0000577
578 // Only install this information if it tells us something.
579 if (NumSignBits != 1 || KnownZero != 0 || KnownOne != 0) {
580 DestReg -= TargetRegisterInfo::FirstVirtualRegister;
Dan Gohmanf350b272008-08-23 02:25:05 +0000581 FunctionLoweringInfo &FLI = CurDAG->getFunctionLoweringInfo();
Chris Lattneread0d882008-06-17 06:09:18 +0000582 if (DestReg >= FLI.LiveOutRegInfo.size())
583 FLI.LiveOutRegInfo.resize(DestReg+1);
584 FunctionLoweringInfo::LiveOutInfo &LOI = FLI.LiveOutRegInfo[DestReg];
585 LOI.NumSignBits = NumSignBits;
586 LOI.KnownOne = NumSignBits;
587 LOI.KnownZero = NumSignBits;
588 }
589 }
590}
591
Dan Gohmanf350b272008-08-23 02:25:05 +0000592void SelectionDAGISel::CodeGenAndEmitDAG() {
Dan Gohman462dc7f2008-07-21 20:00:07 +0000593 std::string GroupName;
594 if (TimePassesIsEnabled)
595 GroupName = "Instruction Selection and Scheduling";
596 std::string BlockName;
597 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs ||
598 ViewDAGCombine2 || ViewISelDAGs || ViewSchedDAGs || ViewSUnitDAGs)
Dan Gohmanf350b272008-08-23 02:25:05 +0000599 BlockName = CurDAG->getMachineFunction().getFunction()->getName() + ':' +
Dan Gohman462dc7f2008-07-21 20:00:07 +0000600 BB->getBasicBlock()->getName();
601
602 DOUT << "Initial selection DAG:\n";
Dan Gohmanf350b272008-08-23 02:25:05 +0000603 DEBUG(CurDAG->dump());
Dan Gohman462dc7f2008-07-21 20:00:07 +0000604
Dan Gohmanf350b272008-08-23 02:25:05 +0000605 if (ViewDAGCombine1) CurDAG->viewGraph("dag-combine1 input for " + BlockName);
Dan Gohman417e11b2007-10-08 15:12:17 +0000606
Chris Lattneraf21d552005-10-10 16:47:10 +0000607 // Run the DAG combiner in pre-legalize mode.
Evan Chengebffb662008-07-01 17:59:20 +0000608 if (TimePassesIsEnabled) {
Dan Gohman5e843682008-07-14 18:19:29 +0000609 NamedRegionTimer T("DAG Combining 1", GroupName);
Dan Gohmanf350b272008-08-23 02:25:05 +0000610 CurDAG->Combine(false, *AA, Fast);
Evan Chengebffb662008-07-01 17:59:20 +0000611 } else {
Dan Gohmanf350b272008-08-23 02:25:05 +0000612 CurDAG->Combine(false, *AA, Fast);
Evan Chengebffb662008-07-01 17:59:20 +0000613 }
Nate Begeman2300f552005-09-07 00:15:36 +0000614
Dan Gohman417e11b2007-10-08 15:12:17 +0000615 DOUT << "Optimized lowered selection DAG:\n";
Dan Gohmanf350b272008-08-23 02:25:05 +0000616 DEBUG(CurDAG->dump());
Duncan Sandsf00e74f2008-07-17 17:06:03 +0000617
Chris Lattner1c08c712005-01-07 07:47:53 +0000618 // Second step, hack on the DAG until it only uses operations and types that
619 // the target supports.
Duncan Sandsf00e74f2008-07-17 17:06:03 +0000620 if (EnableLegalizeTypes) {// Enable this some day.
Dan Gohmanf350b272008-08-23 02:25:05 +0000621 if (ViewLegalizeTypesDAGs) CurDAG->viewGraph("legalize-types input for " +
622 BlockName);
Dan Gohman462dc7f2008-07-21 20:00:07 +0000623
624 if (TimePassesIsEnabled) {
625 NamedRegionTimer T("Type Legalization", GroupName);
Dan Gohmanf350b272008-08-23 02:25:05 +0000626 CurDAG->LegalizeTypes();
Dan Gohman462dc7f2008-07-21 20:00:07 +0000627 } else {
Dan Gohmanf350b272008-08-23 02:25:05 +0000628 CurDAG->LegalizeTypes();
Dan Gohman462dc7f2008-07-21 20:00:07 +0000629 }
630
631 DOUT << "Type-legalized selection DAG:\n";
Dan Gohmanf350b272008-08-23 02:25:05 +0000632 DEBUG(CurDAG->dump());
Dan Gohman462dc7f2008-07-21 20:00:07 +0000633
Chris Lattner70587ea2008-07-10 23:37:50 +0000634 // TODO: enable a dag combine pass here.
635 }
Duncan Sandsf00e74f2008-07-17 17:06:03 +0000636
Dan Gohmanf350b272008-08-23 02:25:05 +0000637 if (ViewLegalizeDAGs) CurDAG->viewGraph("legalize input for " + BlockName);
Dan Gohman462dc7f2008-07-21 20:00:07 +0000638
Evan Chengebffb662008-07-01 17:59:20 +0000639 if (TimePassesIsEnabled) {
Dan Gohman5e843682008-07-14 18:19:29 +0000640 NamedRegionTimer T("DAG Legalization", GroupName);
Dan Gohmanf350b272008-08-23 02:25:05 +0000641 CurDAG->Legalize();
Evan Chengebffb662008-07-01 17:59:20 +0000642 } else {
Dan Gohmanf350b272008-08-23 02:25:05 +0000643 CurDAG->Legalize();
Evan Chengebffb662008-07-01 17:59:20 +0000644 }
Nate Begemanf15485a2006-03-27 01:32:24 +0000645
Bill Wendling832171c2006-12-07 20:04:42 +0000646 DOUT << "Legalized selection DAG:\n";
Dan Gohmanf350b272008-08-23 02:25:05 +0000647 DEBUG(CurDAG->dump());
Nate Begemanf15485a2006-03-27 01:32:24 +0000648
Dan Gohmanf350b272008-08-23 02:25:05 +0000649 if (ViewDAGCombine2) CurDAG->viewGraph("dag-combine2 input for " + BlockName);
Dan Gohman462dc7f2008-07-21 20:00:07 +0000650
Chris Lattneraf21d552005-10-10 16:47:10 +0000651 // Run the DAG combiner in post-legalize mode.
Evan Chengebffb662008-07-01 17:59:20 +0000652 if (TimePassesIsEnabled) {
Dan Gohman5e843682008-07-14 18:19:29 +0000653 NamedRegionTimer T("DAG Combining 2", GroupName);
Dan Gohmanf350b272008-08-23 02:25:05 +0000654 CurDAG->Combine(true, *AA, Fast);
Evan Chengebffb662008-07-01 17:59:20 +0000655 } else {
Dan Gohmanf350b272008-08-23 02:25:05 +0000656 CurDAG->Combine(true, *AA, Fast);
Evan Chengebffb662008-07-01 17:59:20 +0000657 }
Nate Begeman2300f552005-09-07 00:15:36 +0000658
Dan Gohman417e11b2007-10-08 15:12:17 +0000659 DOUT << "Optimized legalized selection DAG:\n";
Dan Gohmanf350b272008-08-23 02:25:05 +0000660 DEBUG(CurDAG->dump());
Dan Gohman417e11b2007-10-08 15:12:17 +0000661
Dan Gohmanf350b272008-08-23 02:25:05 +0000662 if (ViewISelDAGs) CurDAG->viewGraph("isel input for " + BlockName);
Chris Lattneread0d882008-06-17 06:09:18 +0000663
Dan Gohman925a7e82008-08-13 19:47:40 +0000664 if (!Fast && EnableValueProp)
Dan Gohmanf350b272008-08-23 02:25:05 +0000665 ComputeLiveOutVRegInfo();
Evan Cheng552c4a82006-04-28 02:09:19 +0000666
Chris Lattnera33ef482005-03-30 01:10:47 +0000667 // Third, instruction select all of the operations to machine code, adding the
668 // code to the MachineBasicBlock.
Evan Chengebffb662008-07-01 17:59:20 +0000669 if (TimePassesIsEnabled) {
Dan Gohman5e843682008-07-14 18:19:29 +0000670 NamedRegionTimer T("Instruction Selection", GroupName);
Dan Gohmanf350b272008-08-23 02:25:05 +0000671 InstructionSelect();
Evan Chengebffb662008-07-01 17:59:20 +0000672 } else {
Dan Gohmanf350b272008-08-23 02:25:05 +0000673 InstructionSelect();
Evan Chengebffb662008-07-01 17:59:20 +0000674 }
Evan Chengdb8d56b2008-06-30 20:45:06 +0000675
Dan Gohman462dc7f2008-07-21 20:00:07 +0000676 DOUT << "Selected selection DAG:\n";
Dan Gohmanf350b272008-08-23 02:25:05 +0000677 DEBUG(CurDAG->dump());
Dan Gohman462dc7f2008-07-21 20:00:07 +0000678
Dan Gohmanf350b272008-08-23 02:25:05 +0000679 if (ViewSchedDAGs) CurDAG->viewGraph("scheduler input for " + BlockName);
Dan Gohman462dc7f2008-07-21 20:00:07 +0000680
Dan Gohman5e843682008-07-14 18:19:29 +0000681 // Schedule machine code.
682 ScheduleDAG *Scheduler;
683 if (TimePassesIsEnabled) {
684 NamedRegionTimer T("Instruction Scheduling", GroupName);
Dan Gohmanf350b272008-08-23 02:25:05 +0000685 Scheduler = Schedule();
Dan Gohman5e843682008-07-14 18:19:29 +0000686 } else {
Dan Gohmanf350b272008-08-23 02:25:05 +0000687 Scheduler = Schedule();
Dan Gohman5e843682008-07-14 18:19:29 +0000688 }
689
Dan Gohman462dc7f2008-07-21 20:00:07 +0000690 if (ViewSUnitDAGs) Scheduler->viewGraph();
691
Evan Chengdb8d56b2008-06-30 20:45:06 +0000692 // Emit machine code to BB. This can change 'BB' to the last block being
693 // inserted into.
Evan Chengebffb662008-07-01 17:59:20 +0000694 if (TimePassesIsEnabled) {
Dan Gohman5e843682008-07-14 18:19:29 +0000695 NamedRegionTimer T("Instruction Creation", GroupName);
696 BB = Scheduler->EmitSchedule();
Evan Chengebffb662008-07-01 17:59:20 +0000697 } else {
Dan Gohman5e843682008-07-14 18:19:29 +0000698 BB = Scheduler->EmitSchedule();
699 }
700
701 // Free the scheduler state.
702 if (TimePassesIsEnabled) {
703 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName);
704 delete Scheduler;
705 } else {
706 delete Scheduler;
Evan Chengebffb662008-07-01 17:59:20 +0000707 }
Evan Chengdb8d56b2008-06-30 20:45:06 +0000708
Bill Wendling832171c2006-12-07 20:04:42 +0000709 DOUT << "Selected machine code:\n";
Chris Lattner1c08c712005-01-07 07:47:53 +0000710 DEBUG(BB->dump());
Nate Begemanf15485a2006-03-27 01:32:24 +0000711}
Chris Lattner1c08c712005-01-07 07:47:53 +0000712
Dan Gohman7c3234c2008-08-27 23:52:12 +0000713void SelectionDAGISel::SelectAllBasicBlocks(Function &Fn, MachineFunction &MF) {
Evan Cheng39fd6e82008-08-07 00:43:25 +0000714 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) {
715 BasicBlock *LLVMBB = &*I;
Dan Gohman7c3234c2008-08-27 23:52:12 +0000716 BB = FuncInfo->MBBMap[LLVMBB];
Dan Gohmanf350b272008-08-23 02:25:05 +0000717
Dan Gohman3df24e62008-09-03 23:12:08 +0000718 BasicBlock::iterator const Begin = LLVMBB->begin();
719 BasicBlock::iterator const End = LLVMBB->end();
Evan Cheng9f118502008-09-08 16:01:27 +0000720 BasicBlock::iterator BI = Begin;
Dan Gohman5edd3612008-08-28 20:28:56 +0000721
722 // Lower any arguments needed in this block if this is the entry block.
723 if (LLVMBB == &Fn.getEntryBlock())
724 LowerArguments(LLVMBB);
Dan Gohmanf350b272008-08-23 02:25:05 +0000725
726 // Before doing SelectionDAG ISel, see if FastISel has been requested.
727 // FastISel doesn't support EH landing pads, which require special handling.
728 if (EnableFastISel && !BB->isLandingPad()) {
Dan Gohman3df24e62008-09-03 23:12:08 +0000729 if (FastISel *F = TLI.createFastISel(*FuncInfo->MF, FuncInfo->ValueMap,
Dan Gohman0586d912008-09-10 20:11:02 +0000730 FuncInfo->MBBMap,
731 FuncInfo->StaticAllocaMap)) {
Dan Gohman5edd3612008-08-28 20:28:56 +0000732 // Emit code for any incoming arguments. This must happen before
733 // beginning FastISel on the entry block.
734 if (LLVMBB == &Fn.getEntryBlock()) {
735 CurDAG->setRoot(SDL->getControlRoot());
736 CodeGenAndEmitDAG();
737 SDL->clear();
738 }
Dan Gohman3df24e62008-09-03 23:12:08 +0000739 F->setCurrentBlock(BB);
Dan Gohman5edd3612008-08-28 20:28:56 +0000740 // Do FastISel on as many instructions as possible.
Evan Cheng9f118502008-09-08 16:01:27 +0000741 for (; BI != End; ++BI) {
Dan Gohman3df24e62008-09-03 23:12:08 +0000742 // Just before the terminator instruction, insert instructions to
743 // feed PHI nodes in successor blocks.
Dan Gohmana8657e32008-09-08 20:37:59 +0000744 if (isa<TerminatorInst>(BI))
Dan Gohman3df24e62008-09-03 23:12:08 +0000745 if (!HandlePHINodesInSuccessorBlocksFast(LLVMBB, F)) {
Dan Gohman4344a5d2008-09-09 23:05:00 +0000746 if (EnableFastISelVerbose || EnableFastISelAbort) {
Dan Gohman293d5f82008-09-09 22:06:46 +0000747 cerr << "FastISel miss: ";
748 BI->dump();
749 }
Dan Gohman4344a5d2008-09-09 23:05:00 +0000750 if (EnableFastISelAbort)
Dan Gohman293d5f82008-09-09 22:06:46 +0000751 assert(0 && "FastISel didn't handle a PHI in a successor");
Dan Gohman3ee25dc2008-09-10 15:52:34 +0000752 break;
Dan Gohmanf350b272008-08-23 02:25:05 +0000753 }
754
Dan Gohman3df24e62008-09-03 23:12:08 +0000755 // First try normal tablegen-generated "fast" selection.
Evan Cheng9f118502008-09-08 16:01:27 +0000756 if (F->SelectInstruction(BI))
Dan Gohman3df24e62008-09-03 23:12:08 +0000757 continue;
758
759 // Next, try calling the target to attempt to handle the instruction.
Evan Cheng9f118502008-09-08 16:01:27 +0000760 if (F->TargetSelectInstruction(BI))
Dan Gohman3df24e62008-09-03 23:12:08 +0000761 continue;
762
763 // Then handle certain instructions as single-LLVM-Instruction blocks.
Dan Gohmancf01f7a2008-09-09 02:40:04 +0000764 if (isa<CallInst>(BI)) {
Evan Cheng9f118502008-09-08 16:01:27 +0000765 if (BI->getType() != Type::VoidTy) {
Dan Gohmana8657e32008-09-08 20:37:59 +0000766 unsigned &R = FuncInfo->ValueMap[BI];
Dan Gohman3df24e62008-09-03 23:12:08 +0000767 if (!R)
Evan Cheng9f118502008-09-08 16:01:27 +0000768 R = FuncInfo->CreateRegForValue(BI);
Dan Gohman3df24e62008-09-03 23:12:08 +0000769 }
770
Evan Cheng9f118502008-09-08 16:01:27 +0000771 SelectBasicBlock(LLVMBB, BI, next(BI));
Dan Gohmanf350b272008-08-23 02:25:05 +0000772 continue;
773 }
774
Dan Gohman293d5f82008-09-09 22:06:46 +0000775 // Otherwise, give up on FastISel for the rest of the block.
776 // For now, be a little lenient about non-branch terminators.
777 if (!isa<TerminatorInst>(BI) || isa<BranchInst>(BI)) {
Dan Gohman4344a5d2008-09-09 23:05:00 +0000778 if (EnableFastISelVerbose || EnableFastISelAbort) {
Dan Gohman293d5f82008-09-09 22:06:46 +0000779 cerr << "FastISel miss: ";
780 BI->dump();
781 }
Dan Gohman4344a5d2008-09-09 23:05:00 +0000782 if (EnableFastISelAbort)
Dan Gohman293d5f82008-09-09 22:06:46 +0000783 // The "fast" selector couldn't handle something and bailed.
784 // For the purpose of debugging, just abort.
785 assert(0 && "FastISel didn't select the entire block");
Dan Gohmanf350b272008-08-23 02:25:05 +0000786 }
787 break;
788 }
789 delete F;
790 }
791 }
792
Dan Gohmand2ff6472008-09-02 20:17:56 +0000793 // Run SelectionDAG instruction selection on the remainder of the block
794 // not handled by FastISel. If FastISel is not run, this is the entire
Dan Gohman3df24e62008-09-03 23:12:08 +0000795 // block.
Evan Cheng9f118502008-09-08 16:01:27 +0000796 if (BI != End)
797 SelectBasicBlock(LLVMBB, BI, End);
Dan Gohmanf350b272008-08-23 02:25:05 +0000798
Dan Gohman7c3234c2008-08-27 23:52:12 +0000799 FinishBasicBlock();
Evan Cheng39fd6e82008-08-07 00:43:25 +0000800 }
Dan Gohman0e5f1302008-07-07 23:02:41 +0000801}
802
Dan Gohmanfed90b62008-07-28 21:51:04 +0000803void
Dan Gohman7c3234c2008-08-27 23:52:12 +0000804SelectionDAGISel::FinishBasicBlock() {
Dan Gohmanf350b272008-08-23 02:25:05 +0000805
806 // Perform target specific isel post processing.
807 InstructionSelectPostProcessing();
Nate Begemanf15485a2006-03-27 01:32:24 +0000808
Dan Gohmanf350b272008-08-23 02:25:05 +0000809 DOUT << "Target-post-processed machine code:\n";
810 DEBUG(BB->dump());
Nate Begemanf15485a2006-03-27 01:32:24 +0000811
Anton Korobeynikov4198c582007-04-09 12:31:58 +0000812 DOUT << "Total amount of phi nodes to update: "
Dan Gohman7c3234c2008-08-27 23:52:12 +0000813 << SDL->PHINodesToUpdate.size() << "\n";
814 DEBUG(for (unsigned i = 0, e = SDL->PHINodesToUpdate.size(); i != e; ++i)
815 DOUT << "Node " << i << " : (" << SDL->PHINodesToUpdate[i].first
816 << ", " << SDL->PHINodesToUpdate[i].second << ")\n";);
Nate Begemanf15485a2006-03-27 01:32:24 +0000817
Chris Lattnera33ef482005-03-30 01:10:47 +0000818 // Next, now that we know what the last MBB the LLVM BB expanded is, update
Chris Lattner1c08c712005-01-07 07:47:53 +0000819 // PHI nodes in successors.
Dan Gohman7c3234c2008-08-27 23:52:12 +0000820 if (SDL->SwitchCases.empty() &&
821 SDL->JTCases.empty() &&
822 SDL->BitTestCases.empty()) {
823 for (unsigned i = 0, e = SDL->PHINodesToUpdate.size(); i != e; ++i) {
824 MachineInstr *PHI = SDL->PHINodesToUpdate[i].first;
Nate Begemanf15485a2006-03-27 01:32:24 +0000825 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
826 "This is not a machine PHI node that we are updating!");
Dan Gohman7c3234c2008-08-27 23:52:12 +0000827 PHI->addOperand(MachineOperand::CreateReg(SDL->PHINodesToUpdate[i].second,
Chris Lattner9ce2e9d2007-12-30 00:57:42 +0000828 false));
829 PHI->addOperand(MachineOperand::CreateMBB(BB));
Nate Begemanf15485a2006-03-27 01:32:24 +0000830 }
Dan Gohman7c3234c2008-08-27 23:52:12 +0000831 SDL->PHINodesToUpdate.clear();
Nate Begemanf15485a2006-03-27 01:32:24 +0000832 return;
Chris Lattner1c08c712005-01-07 07:47:53 +0000833 }
Anton Korobeynikov4198c582007-04-09 12:31:58 +0000834
Dan Gohman7c3234c2008-08-27 23:52:12 +0000835 for (unsigned i = 0, e = SDL->BitTestCases.size(); i != e; ++i) {
Anton Korobeynikov4198c582007-04-09 12:31:58 +0000836 // Lower header first, if it wasn't already lowered
Dan Gohman7c3234c2008-08-27 23:52:12 +0000837 if (!SDL->BitTestCases[i].Emitted) {
Anton Korobeynikov4198c582007-04-09 12:31:58 +0000838 // Set the current basic block to the mbb we wish to insert the code into
Dan Gohman7c3234c2008-08-27 23:52:12 +0000839 BB = SDL->BitTestCases[i].Parent;
840 SDL->setCurrentBasicBlock(BB);
Anton Korobeynikov4198c582007-04-09 12:31:58 +0000841 // Emit the code
Dan Gohman7c3234c2008-08-27 23:52:12 +0000842 SDL->visitBitTestHeader(SDL->BitTestCases[i]);
843 CurDAG->setRoot(SDL->getRoot());
Dan Gohmanf350b272008-08-23 02:25:05 +0000844 CodeGenAndEmitDAG();
Dan Gohman7c3234c2008-08-27 23:52:12 +0000845 SDL->clear();
Anton Korobeynikov4198c582007-04-09 12:31:58 +0000846 }
847
Dan Gohman7c3234c2008-08-27 23:52:12 +0000848 for (unsigned j = 0, ej = SDL->BitTestCases[i].Cases.size(); j != ej; ++j) {
Anton Korobeynikov4198c582007-04-09 12:31:58 +0000849 // Set the current basic block to the mbb we wish to insert the code into
Dan Gohman7c3234c2008-08-27 23:52:12 +0000850 BB = SDL->BitTestCases[i].Cases[j].ThisBB;
851 SDL->setCurrentBasicBlock(BB);
Anton Korobeynikov4198c582007-04-09 12:31:58 +0000852 // Emit the code
853 if (j+1 != ej)
Dan Gohman7c3234c2008-08-27 23:52:12 +0000854 SDL->visitBitTestCase(SDL->BitTestCases[i].Cases[j+1].ThisBB,
855 SDL->BitTestCases[i].Reg,
856 SDL->BitTestCases[i].Cases[j]);
Anton Korobeynikov4198c582007-04-09 12:31:58 +0000857 else
Dan Gohman7c3234c2008-08-27 23:52:12 +0000858 SDL->visitBitTestCase(SDL->BitTestCases[i].Default,
859 SDL->BitTestCases[i].Reg,
860 SDL->BitTestCases[i].Cases[j]);
Anton Korobeynikov4198c582007-04-09 12:31:58 +0000861
862
Dan Gohman7c3234c2008-08-27 23:52:12 +0000863 CurDAG->setRoot(SDL->getRoot());
Dan Gohmanf350b272008-08-23 02:25:05 +0000864 CodeGenAndEmitDAG();
Dan Gohman7c3234c2008-08-27 23:52:12 +0000865 SDL->clear();
Anton Korobeynikov4198c582007-04-09 12:31:58 +0000866 }
867
868 // Update PHI Nodes
Dan Gohman7c3234c2008-08-27 23:52:12 +0000869 for (unsigned pi = 0, pe = SDL->PHINodesToUpdate.size(); pi != pe; ++pi) {
870 MachineInstr *PHI = SDL->PHINodesToUpdate[pi].first;
Anton Korobeynikov4198c582007-04-09 12:31:58 +0000871 MachineBasicBlock *PHIBB = PHI->getParent();
872 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
873 "This is not a machine PHI node that we are updating!");
874 // This is "default" BB. We have two jumps to it. From "header" BB and
875 // from last "case" BB.
Dan Gohman7c3234c2008-08-27 23:52:12 +0000876 if (PHIBB == SDL->BitTestCases[i].Default) {
877 PHI->addOperand(MachineOperand::CreateReg(SDL->PHINodesToUpdate[pi].second,
Chris Lattner9ce2e9d2007-12-30 00:57:42 +0000878 false));
Dan Gohman7c3234c2008-08-27 23:52:12 +0000879 PHI->addOperand(MachineOperand::CreateMBB(SDL->BitTestCases[i].Parent));
880 PHI->addOperand(MachineOperand::CreateReg(SDL->PHINodesToUpdate[pi].second,
Chris Lattner9ce2e9d2007-12-30 00:57:42 +0000881 false));
Dan Gohman7c3234c2008-08-27 23:52:12 +0000882 PHI->addOperand(MachineOperand::CreateMBB(SDL->BitTestCases[i].Cases.
Chris Lattner9ce2e9d2007-12-30 00:57:42 +0000883 back().ThisBB));
Anton Korobeynikov4198c582007-04-09 12:31:58 +0000884 }
885 // One of "cases" BB.
Dan Gohman7c3234c2008-08-27 23:52:12 +0000886 for (unsigned j = 0, ej = SDL->BitTestCases[i].Cases.size();
887 j != ej; ++j) {
888 MachineBasicBlock* cBB = SDL->BitTestCases[i].Cases[j].ThisBB;
Anton Korobeynikov4198c582007-04-09 12:31:58 +0000889 if (cBB->succ_end() !=
890 std::find(cBB->succ_begin(),cBB->succ_end(), PHIBB)) {
Dan Gohman7c3234c2008-08-27 23:52:12 +0000891 PHI->addOperand(MachineOperand::CreateReg(SDL->PHINodesToUpdate[pi].second,
Chris Lattner9ce2e9d2007-12-30 00:57:42 +0000892 false));
893 PHI->addOperand(MachineOperand::CreateMBB(cBB));
Anton Korobeynikov4198c582007-04-09 12:31:58 +0000894 }
895 }
896 }
897 }
Dan Gohman7c3234c2008-08-27 23:52:12 +0000898 SDL->BitTestCases.clear();
Anton Korobeynikov4198c582007-04-09 12:31:58 +0000899
Nate Begeman9453eea2006-04-23 06:26:20 +0000900 // If the JumpTable record is filled in, then we need to emit a jump table.
901 // Updating the PHI nodes is tricky in this case, since we need to determine
902 // whether the PHI is a successor of the range check MBB or the jump table MBB
Dan Gohman7c3234c2008-08-27 23:52:12 +0000903 for (unsigned i = 0, e = SDL->JTCases.size(); i != e; ++i) {
Anton Korobeynikov3a84b9b2007-03-25 15:07:15 +0000904 // Lower header first, if it wasn't already lowered
Dan Gohman7c3234c2008-08-27 23:52:12 +0000905 if (!SDL->JTCases[i].first.Emitted) {
Anton Korobeynikov3a84b9b2007-03-25 15:07:15 +0000906 // Set the current basic block to the mbb we wish to insert the code into
Dan Gohman7c3234c2008-08-27 23:52:12 +0000907 BB = SDL->JTCases[i].first.HeaderBB;
908 SDL->setCurrentBasicBlock(BB);
Anton Korobeynikov3a84b9b2007-03-25 15:07:15 +0000909 // Emit the code
Dan Gohman7c3234c2008-08-27 23:52:12 +0000910 SDL->visitJumpTableHeader(SDL->JTCases[i].second, SDL->JTCases[i].first);
911 CurDAG->setRoot(SDL->getRoot());
Dan Gohmanf350b272008-08-23 02:25:05 +0000912 CodeGenAndEmitDAG();
Dan Gohman7c3234c2008-08-27 23:52:12 +0000913 SDL->clear();
Anton Korobeynikov4198c582007-04-09 12:31:58 +0000914 }
Anton Korobeynikov3a84b9b2007-03-25 15:07:15 +0000915
Nate Begeman37efe672006-04-22 18:53:45 +0000916 // Set the current basic block to the mbb we wish to insert the code into
Dan Gohman7c3234c2008-08-27 23:52:12 +0000917 BB = SDL->JTCases[i].second.MBB;
918 SDL->setCurrentBasicBlock(BB);
Nate Begeman37efe672006-04-22 18:53:45 +0000919 // Emit the code
Dan Gohman7c3234c2008-08-27 23:52:12 +0000920 SDL->visitJumpTable(SDL->JTCases[i].second);
921 CurDAG->setRoot(SDL->getRoot());
Dan Gohmanf350b272008-08-23 02:25:05 +0000922 CodeGenAndEmitDAG();
Dan Gohman7c3234c2008-08-27 23:52:12 +0000923 SDL->clear();
Anton Korobeynikov3a84b9b2007-03-25 15:07:15 +0000924
Nate Begeman37efe672006-04-22 18:53:45 +0000925 // Update PHI Nodes
Dan Gohman7c3234c2008-08-27 23:52:12 +0000926 for (unsigned pi = 0, pe = SDL->PHINodesToUpdate.size(); pi != pe; ++pi) {
927 MachineInstr *PHI = SDL->PHINodesToUpdate[pi].first;
Nate Begeman37efe672006-04-22 18:53:45 +0000928 MachineBasicBlock *PHIBB = PHI->getParent();
929 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
930 "This is not a machine PHI node that we are updating!");
Anton Korobeynikov4198c582007-04-09 12:31:58 +0000931 // "default" BB. We can go there only from header BB.
Dan Gohman7c3234c2008-08-27 23:52:12 +0000932 if (PHIBB == SDL->JTCases[i].second.Default) {
933 PHI->addOperand(MachineOperand::CreateReg(SDL->PHINodesToUpdate[pi].second,
Chris Lattner9ce2e9d2007-12-30 00:57:42 +0000934 false));
Dan Gohman7c3234c2008-08-27 23:52:12 +0000935 PHI->addOperand(MachineOperand::CreateMBB(SDL->JTCases[i].first.HeaderBB));
Nate Begemanf4360a42006-05-03 03:48:02 +0000936 }
Anton Korobeynikov4198c582007-04-09 12:31:58 +0000937 // JT BB. Just iterate over successors here
Nate Begemanf4360a42006-05-03 03:48:02 +0000938 if (BB->succ_end() != std::find(BB->succ_begin(),BB->succ_end(), PHIBB)) {
Dan Gohman7c3234c2008-08-27 23:52:12 +0000939 PHI->addOperand(MachineOperand::CreateReg(SDL->PHINodesToUpdate[pi].second,
Chris Lattner9ce2e9d2007-12-30 00:57:42 +0000940 false));
941 PHI->addOperand(MachineOperand::CreateMBB(BB));
Nate Begeman37efe672006-04-22 18:53:45 +0000942 }
943 }
Nate Begeman37efe672006-04-22 18:53:45 +0000944 }
Dan Gohman7c3234c2008-08-27 23:52:12 +0000945 SDL->JTCases.clear();
Nate Begeman37efe672006-04-22 18:53:45 +0000946
Chris Lattnerb2e806e2006-10-22 23:00:53 +0000947 // If the switch block involved a branch to one of the actual successors, we
948 // need to update PHI nodes in that block.
Dan Gohman7c3234c2008-08-27 23:52:12 +0000949 for (unsigned i = 0, e = SDL->PHINodesToUpdate.size(); i != e; ++i) {
950 MachineInstr *PHI = SDL->PHINodesToUpdate[i].first;
Chris Lattnerb2e806e2006-10-22 23:00:53 +0000951 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
952 "This is not a machine PHI node that we are updating!");
953 if (BB->isSuccessor(PHI->getParent())) {
Dan Gohman7c3234c2008-08-27 23:52:12 +0000954 PHI->addOperand(MachineOperand::CreateReg(SDL->PHINodesToUpdate[i].second,
Chris Lattner9ce2e9d2007-12-30 00:57:42 +0000955 false));
956 PHI->addOperand(MachineOperand::CreateMBB(BB));
Chris Lattnerb2e806e2006-10-22 23:00:53 +0000957 }
958 }
959
Nate Begemanf15485a2006-03-27 01:32:24 +0000960 // If we generated any switch lowering information, build and codegen any
961 // additional DAGs necessary.
Dan Gohman7c3234c2008-08-27 23:52:12 +0000962 for (unsigned i = 0, e = SDL->SwitchCases.size(); i != e; ++i) {
Nate Begemanf15485a2006-03-27 01:32:24 +0000963 // Set the current basic block to the mbb we wish to insert the code into
Dan Gohman7c3234c2008-08-27 23:52:12 +0000964 BB = SDL->SwitchCases[i].ThisBB;
965 SDL->setCurrentBasicBlock(BB);
Chris Lattnerd5e93c02006-09-07 01:59:34 +0000966
Nate Begemanf15485a2006-03-27 01:32:24 +0000967 // Emit the code
Dan Gohman7c3234c2008-08-27 23:52:12 +0000968 SDL->visitSwitchCase(SDL->SwitchCases[i]);
969 CurDAG->setRoot(SDL->getRoot());
Dan Gohmanf350b272008-08-23 02:25:05 +0000970 CodeGenAndEmitDAG();
Dan Gohman7c3234c2008-08-27 23:52:12 +0000971 SDL->clear();
Chris Lattnerd5e93c02006-09-07 01:59:34 +0000972
973 // Handle any PHI nodes in successors of this chunk, as if we were coming
974 // from the original BB before switch expansion. Note that PHI nodes can
975 // occur multiple times in PHINodesToUpdate. We have to be very careful to
976 // handle them the right number of times.
Dan Gohman7c3234c2008-08-27 23:52:12 +0000977 while ((BB = SDL->SwitchCases[i].TrueBB)) { // Handle LHS and RHS.
Chris Lattnerd5e93c02006-09-07 01:59:34 +0000978 for (MachineBasicBlock::iterator Phi = BB->begin();
979 Phi != BB->end() && Phi->getOpcode() == TargetInstrInfo::PHI; ++Phi){
980 // This value for this PHI node is recorded in PHINodesToUpdate, get it.
981 for (unsigned pn = 0; ; ++pn) {
Dan Gohman7c3234c2008-08-27 23:52:12 +0000982 assert(pn != SDL->PHINodesToUpdate.size() &&
983 "Didn't find PHI entry!");
984 if (SDL->PHINodesToUpdate[pn].first == Phi) {
985 Phi->addOperand(MachineOperand::CreateReg(SDL->PHINodesToUpdate[pn].
Chris Lattner9ce2e9d2007-12-30 00:57:42 +0000986 second, false));
Dan Gohman7c3234c2008-08-27 23:52:12 +0000987 Phi->addOperand(MachineOperand::CreateMBB(SDL->SwitchCases[i].ThisBB));
Chris Lattnerd5e93c02006-09-07 01:59:34 +0000988 break;
989 }
990 }
Nate Begemanf15485a2006-03-27 01:32:24 +0000991 }
Chris Lattnerd5e93c02006-09-07 01:59:34 +0000992
993 // Don't process RHS if same block as LHS.
Dan Gohman7c3234c2008-08-27 23:52:12 +0000994 if (BB == SDL->SwitchCases[i].FalseBB)
995 SDL->SwitchCases[i].FalseBB = 0;
Chris Lattnerd5e93c02006-09-07 01:59:34 +0000996
997 // If we haven't handled the RHS, do so now. Otherwise, we're done.
Dan Gohman7c3234c2008-08-27 23:52:12 +0000998 SDL->SwitchCases[i].TrueBB = SDL->SwitchCases[i].FalseBB;
999 SDL->SwitchCases[i].FalseBB = 0;
Nate Begemanf15485a2006-03-27 01:32:24 +00001000 }
Dan Gohman7c3234c2008-08-27 23:52:12 +00001001 assert(SDL->SwitchCases[i].TrueBB == 0 && SDL->SwitchCases[i].FalseBB == 0);
Chris Lattnera33ef482005-03-30 01:10:47 +00001002 }
Dan Gohman7c3234c2008-08-27 23:52:12 +00001003 SDL->SwitchCases.clear();
1004
1005 SDL->PHINodesToUpdate.clear();
Chris Lattner1c08c712005-01-07 07:47:53 +00001006}
Evan Chenga9c20912006-01-21 02:32:06 +00001007
Jim Laskey13ec7022006-08-01 14:21:23 +00001008
Dan Gohman5e843682008-07-14 18:19:29 +00001009/// Schedule - Pick a safe ordering for instructions for each
Evan Chenga9c20912006-01-21 02:32:06 +00001010/// target node in the graph.
Dan Gohman5e843682008-07-14 18:19:29 +00001011///
Dan Gohmanf350b272008-08-23 02:25:05 +00001012ScheduleDAG *SelectionDAGISel::Schedule() {
Jim Laskeyeb577ba2006-08-02 12:30:23 +00001013 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault();
Jim Laskey13ec7022006-08-01 14:21:23 +00001014
1015 if (!Ctor) {
Jim Laskeyeb577ba2006-08-02 12:30:23 +00001016 Ctor = ISHeuristic;
Jim Laskey9373beb2006-08-01 19:14:14 +00001017 RegisterScheduler::setDefault(Ctor);
Evan Cheng4ef10862006-01-23 07:01:07 +00001018 }
Jim Laskey13ec7022006-08-01 14:21:23 +00001019
Dan Gohmanf350b272008-08-23 02:25:05 +00001020 ScheduleDAG *Scheduler = Ctor(this, CurDAG, BB, Fast);
Dan Gohman5e843682008-07-14 18:19:29 +00001021 Scheduler->Run();
Dan Gohman3e1a7ae2007-08-28 20:32:58 +00001022
Dan Gohman5e843682008-07-14 18:19:29 +00001023 return Scheduler;
Evan Chenga9c20912006-01-21 02:32:06 +00001024}
Chris Lattner0e43f2b2006-02-24 02:13:54 +00001025
Chris Lattner03fc53c2006-03-06 00:22:00 +00001026
Jim Laskey9ff542f2006-08-01 18:29:48 +00001027HazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() {
1028 return new HazardRecognizer();
1029}
1030
Chris Lattner75548062006-10-11 03:58:02 +00001031//===----------------------------------------------------------------------===//
1032// Helper functions used by the generated instruction selector.
1033//===----------------------------------------------------------------------===//
1034// Calls to these methods are generated by tblgen.
1035
1036/// CheckAndMask - The isel is trying to match something like (and X, 255). If
1037/// the dag combiner simplified the 255, we still want to match. RHS is the
1038/// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value
1039/// specified in the .td file (e.g. 255).
Dan Gohman475871a2008-07-27 21:46:04 +00001040bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS,
Dan Gohmandc9b3d02007-07-24 23:00:27 +00001041 int64_t DesiredMaskS) const {
Dan Gohman2e68b6f2008-02-25 21:11:39 +00001042 const APInt &ActualMask = RHS->getAPIntValue();
1043 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
Chris Lattner75548062006-10-11 03:58:02 +00001044
1045 // If the actual mask exactly matches, success!
1046 if (ActualMask == DesiredMask)
1047 return true;
1048
1049 // If the actual AND mask is allowing unallowed bits, this doesn't match.
Dan Gohman2e68b6f2008-02-25 21:11:39 +00001050 if (ActualMask.intersects(~DesiredMask))
Chris Lattner75548062006-10-11 03:58:02 +00001051 return false;
1052
1053 // Otherwise, the DAG Combiner may have proven that the value coming in is
1054 // either already zero or is not demanded. Check for known zero input bits.
Dan Gohman2e68b6f2008-02-25 21:11:39 +00001055 APInt NeededMask = DesiredMask & ~ActualMask;
Dan Gohmanea859be2007-06-22 14:59:07 +00001056 if (CurDAG->MaskedValueIsZero(LHS, NeededMask))
Chris Lattner75548062006-10-11 03:58:02 +00001057 return true;
1058
1059 // TODO: check to see if missing bits are just not demanded.
1060
1061 // Otherwise, this pattern doesn't match.
1062 return false;
1063}
1064
1065/// CheckOrMask - The isel is trying to match something like (or X, 255). If
1066/// the dag combiner simplified the 255, we still want to match. RHS is the
1067/// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value
1068/// specified in the .td file (e.g. 255).
Dan Gohman475871a2008-07-27 21:46:04 +00001069bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS,
Dan Gohman2e68b6f2008-02-25 21:11:39 +00001070 int64_t DesiredMaskS) const {
1071 const APInt &ActualMask = RHS->getAPIntValue();
1072 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
Chris Lattner75548062006-10-11 03:58:02 +00001073
1074 // If the actual mask exactly matches, success!
1075 if (ActualMask == DesiredMask)
1076 return true;
1077
1078 // If the actual AND mask is allowing unallowed bits, this doesn't match.
Dan Gohman2e68b6f2008-02-25 21:11:39 +00001079 if (ActualMask.intersects(~DesiredMask))
Chris Lattner75548062006-10-11 03:58:02 +00001080 return false;
1081
1082 // Otherwise, the DAG Combiner may have proven that the value coming in is
1083 // either already zero or is not demanded. Check for known zero input bits.
Dan Gohman2e68b6f2008-02-25 21:11:39 +00001084 APInt NeededMask = DesiredMask & ~ActualMask;
Chris Lattner75548062006-10-11 03:58:02 +00001085
Dan Gohman2e68b6f2008-02-25 21:11:39 +00001086 APInt KnownZero, KnownOne;
Dan Gohmanea859be2007-06-22 14:59:07 +00001087 CurDAG->ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne);
Chris Lattner75548062006-10-11 03:58:02 +00001088
1089 // If all the missing bits in the or are already known to be set, match!
1090 if ((NeededMask & KnownOne) == NeededMask)
1091 return true;
1092
1093 // TODO: check to see if missing bits are just not demanded.
1094
1095 // Otherwise, this pattern doesn't match.
1096 return false;
1097}
1098
Jim Laskey9ff542f2006-08-01 18:29:48 +00001099
Chris Lattner0e43f2b2006-02-24 02:13:54 +00001100/// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
1101/// by tblgen. Others should not call it.
1102void SelectionDAGISel::
Dan Gohmanf350b272008-08-23 02:25:05 +00001103SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) {
Dan Gohman475871a2008-07-27 21:46:04 +00001104 std::vector<SDValue> InOps;
Chris Lattner0e43f2b2006-02-24 02:13:54 +00001105 std::swap(InOps, Ops);
1106
1107 Ops.push_back(InOps[0]); // input chain.
1108 Ops.push_back(InOps[1]); // input asm string.
1109
Chris Lattner0e43f2b2006-02-24 02:13:54 +00001110 unsigned i = 2, e = InOps.size();
1111 if (InOps[e-1].getValueType() == MVT::Flag)
1112 --e; // Don't process a flag operand if it is here.
1113
1114 while (i != e) {
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +00001115 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue();
Dale Johannesen91aac102008-09-17 21:13:11 +00001116 if ((Flags & 7) != 4 /*MEM*/ &&
1117 (Flags & 7) != 7 /*MEM OVERLAPS EARLYCLOBBER*/) {
Chris Lattner0e43f2b2006-02-24 02:13:54 +00001118 // Just skip over this operand, copying the operands verbatim.
1119 Ops.insert(Ops.end(), InOps.begin()+i, InOps.begin()+i+(Flags >> 3) + 1);
1120 i += (Flags >> 3) + 1;
1121 } else {
1122 assert((Flags >> 3) == 1 && "Memory operand with multiple values?");
1123 // Otherwise, this is a memory operand. Ask the target to select it.
Dan Gohman475871a2008-07-27 21:46:04 +00001124 std::vector<SDValue> SelOps;
Dan Gohmanf350b272008-08-23 02:25:05 +00001125 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps)) {
Bill Wendling832171c2006-12-07 20:04:42 +00001126 cerr << "Could not match memory address. Inline asm failure!\n";
Chris Lattner0e43f2b2006-02-24 02:13:54 +00001127 exit(1);
1128 }
1129
1130 // Add this to the output node.
Dan Gohmanf350b272008-08-23 02:25:05 +00001131 MVT IntPtrTy = CurDAG->getTargetLoweringInfo().getPointerTy();
Dale Johannesen91aac102008-09-17 21:13:11 +00001132 Ops.push_back(CurDAG->getTargetConstant((Flags & 7) | (SelOps.size()<< 3),
Dan Gohmanf350b272008-08-23 02:25:05 +00001133 IntPtrTy));
Chris Lattner0e43f2b2006-02-24 02:13:54 +00001134 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end());
1135 i += 2;
1136 }
1137 }
1138
1139 // Add the flag input back if present.
1140 if (e != InOps.size())
1141 Ops.push_back(InOps.back());
1142}
Devang Patel794fd752007-05-01 21:15:47 +00001143
Devang Patel19974732007-05-03 01:11:54 +00001144char SelectionDAGISel::ID = 0;