blob: 136c9cb043abecf41b8033587f9fec9a1d4de7ce [file] [log] [blame]
Bill Wendlingc61b5062010-10-12 22:08:41 +00001;RUN: llc -mtriple=armv7-apple-darwin -mcpu=cortex-a8 -mattr=-neonfp -show-mc-encoding < %s | FileCheck %s
2
3
4; FIXME: Once the ARM integrated assembler is up and going, these sorts of tests
5; should run on .s source files rather than using llc to generate the
6; assembly.
7
8
Bill Wendling34c2b092010-10-12 22:55:35 +00009define double @f1(double %a, double %b) nounwind readnone {
Bill Wendlingc61b5062010-10-12 22:08:41 +000010entry:
11; CHECK: f1
Bill Wendling34c2b092010-10-12 22:55:35 +000012; CHECK: vadd.f64 d16, d17, d16 @ encoding: [0xa0,0x0b,0x71,0xee]
13 %add = fadd double %a, %b
14 ret double %add
15}
16
17define float @f2(float %a, float %b) nounwind readnone {
18entry:
19; CHECK: f2
Bill Wendlingc61b5062010-10-12 22:08:41 +000020; CHECK: vadd.f32 s0, s1, s0 @ encoding: [0x80,0x0a,0x30,0xee]
21 %add = fadd float %a, %b
22 ret float %add
23}
24
Bill Wendling34c2b092010-10-12 22:55:35 +000025define double @f3(double %a, double %b) nounwind readnone {
Bill Wendlingc61b5062010-10-12 22:08:41 +000026entry:
Bill Wendling34c2b092010-10-12 22:55:35 +000027; CHECK: f3
28; CHECK: vsub.f64 d16, d17, d16 @ encoding: [0xe0,0x0b,0x71,0xee]
29 %sub = fsub double %a, %b
30 ret double %sub
31}
32
33define float @f4(float %a, float %b) nounwind readnone {
34entry:
35; CHECK: f4
36; CHECK: vsub.f32 s0, s1, s0 @ encoding: [0xc0,0x0a,0x30,0xee]
37 %sub = fsub float %a, %b
38 ret float %sub
39}
40
Bill Wendlingda32e822010-10-12 23:22:27 +000041define double @f5(double %a, double %b) nounwind readnone {
Bill Wendling34c2b092010-10-12 22:55:35 +000042entry:
43; CHECK: f5
Bill Wendlingda32e822010-10-12 23:22:27 +000044; CHECK: vdiv.f64 d16, d17, d16 @ encoding: [0xa0,0x0b,0xc1,0xee]
45 %div = fdiv double %a, %b
46 ret double %div
47}
48
49define float @f6(float %a, float %b) nounwind readnone {
50entry:
51; CHECK: f6
52; CHECK: vdiv.f32 s0, s1, s0 @ encoding: [0x80,0x0a,0x80,0xee]
53 %div = fdiv float %a, %b
54 ret float %div
55}
56
57define double @f7(double %a, double %b) nounwind readnone {
58entry:
59; CHECK: f7
60; CHECK: vmul.f64 d16, d17, d16 @ encoding: [0xa0,0x0b,0x61,0xee]
61 %mul = fmul double %a, %b
62 ret double %mul
63}
64
65define float @f8(float %a, float %b) nounwind readnone {
66entry:
67; CHECK: f8
68; CHECK: vmul.f32 s0, s1, s0 @ encoding: [0x80,0x0a,0x20,0xee]
69 %mul = fmul float %a, %b
70 ret float %mul
71}
72
73define i1 @f100(double %a, double %b) nounwind readnone {
74entry:
75; CHECK: f100
Bill Wendling34c2b092010-10-12 22:55:35 +000076; CHECK: vcmpe.f64 d17, d16 @ encoding: [0xe0,0x1b,0xf4,0xee]
77 %cmp = fcmp oeq double %a, %b
78 ret i1 %cmp
79}
80
Bill Wendlingda32e822010-10-12 23:22:27 +000081define i1 @f101(float %a, float %b) nounwind readnone {
Bill Wendling34c2b092010-10-12 22:55:35 +000082entry:
Bill Wendlingda32e822010-10-12 23:22:27 +000083; CHECK: f101
Bill Wendling34c2b092010-10-12 22:55:35 +000084; CHECK: vcmpe.f32 s1, s0 @ encoding: [0xc0,0x0a,0xf4,0xee]
85 %cmp = fcmp oeq float %a, %b
86 ret i1 %cmp
Bill Wendlingc61b5062010-10-12 22:08:41 +000087}