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Akira Hatanaka4552c9a2011-04-15 21:51:11 +00001//===-- MipsISelLowering.cpp - Mips DAG Lowering Implementation -----------===//
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002//
3// The LLVM Compiler Infrastructure
4//
Chris Lattner4ee451d2007-12-29 20:36:04 +00005// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00007//
Akira Hatanaka4552c9a2011-04-15 21:51:11 +00008//===----------------------------------------------------------------------===//
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00009//
10// This file defines the interfaces that Mips uses to lower LLVM code into a
11// selection DAG.
12//
Akira Hatanaka4552c9a2011-04-15 21:51:11 +000013//===----------------------------------------------------------------------===//
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +000014
15#define DEBUG_TYPE "mips-lower"
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +000016#include "MipsISelLowering.h"
Bruno Cardoso Lopesa2b1bb52007-08-28 05:08:16 +000017#include "MipsMachineFunction.h"
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +000018#include "MipsTargetMachine.h"
Chris Lattnerb71b9092009-08-13 06:28:06 +000019#include "MipsTargetObjectFile.h"
Bruno Cardoso Lopes225ca9c2008-07-05 19:05:21 +000020#include "MipsSubtarget.h"
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +000021#include "llvm/DerivedTypes.h"
22#include "llvm/Function.h"
Bruno Cardoso Lopes91fd5322008-07-21 18:52:34 +000023#include "llvm/GlobalVariable.h"
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +000024#include "llvm/Intrinsics.h"
25#include "llvm/CallingConv.h"
Akira Hatanaka794bf172011-07-07 23:56:50 +000026#include "InstPrinter/MipsInstPrinter.h"
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +000027#include "llvm/CodeGen/CallingConvLower.h"
28#include "llvm/CodeGen/MachineFrameInfo.h"
29#include "llvm/CodeGen/MachineFunction.h"
30#include "llvm/CodeGen/MachineInstrBuilder.h"
Chris Lattner84bc5422007-12-31 04:13:23 +000031#include "llvm/CodeGen/MachineRegisterInfo.h"
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +000032#include "llvm/CodeGen/SelectionDAGISel.h"
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +000033#include "llvm/CodeGen/ValueTypes.h"
34#include "llvm/Support/Debug.h"
Torok Edwinc25e7582009-07-11 20:10:48 +000035#include "llvm/Support/ErrorHandling.h"
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +000036using namespace llvm;
37
Akira Hatanakadbe9a312011-08-18 20:07:42 +000038// If I is a shifted mask, set the size (Size) and the first bit of the
39// mask (Pos), and return true.
Akira Hatanaka854a7db2011-08-19 22:59:00 +000040// For example, if I is 0x003ff800, (Pos, Size) = (11, 11).
41static bool IsShiftedMask(uint64_t I, uint64_t &Pos, uint64_t &Size) {
42 if (!isUInt<32>(I) || !isShiftedMask_32(I))
43 return false;
Akira Hatanakabb15e112011-08-17 02:05:42 +000044
Akira Hatanaka854a7db2011-08-19 22:59:00 +000045 Size = CountPopulation_32(I);
46 Pos = CountTrailingZeros_32(I);
Akira Hatanakadbe9a312011-08-18 20:07:42 +000047 return true;
Akira Hatanakabb15e112011-08-17 02:05:42 +000048}
49
Chris Lattnerf0144122009-07-28 03:13:23 +000050const char *MipsTargetLowering::getTargetNodeName(unsigned Opcode) const {
51 switch (Opcode) {
Akira Hatanakabdd2ce92011-05-23 21:13:59 +000052 case MipsISD::JmpLink: return "MipsISD::JmpLink";
53 case MipsISD::Hi: return "MipsISD::Hi";
54 case MipsISD::Lo: return "MipsISD::Lo";
55 case MipsISD::GPRel: return "MipsISD::GPRel";
Bruno Cardoso Lopesd9796862011-05-31 02:53:58 +000056 case MipsISD::TlsGd: return "MipsISD::TlsGd";
57 case MipsISD::TprelHi: return "MipsISD::TprelHi";
58 case MipsISD::TprelLo: return "MipsISD::TprelLo";
59 case MipsISD::ThreadPointer: return "MipsISD::ThreadPointer";
Akira Hatanakabdd2ce92011-05-23 21:13:59 +000060 case MipsISD::Ret: return "MipsISD::Ret";
61 case MipsISD::FPBrcond: return "MipsISD::FPBrcond";
62 case MipsISD::FPCmp: return "MipsISD::FPCmp";
63 case MipsISD::CMovFP_T: return "MipsISD::CMovFP_T";
64 case MipsISD::CMovFP_F: return "MipsISD::CMovFP_F";
65 case MipsISD::FPRound: return "MipsISD::FPRound";
66 case MipsISD::MAdd: return "MipsISD::MAdd";
67 case MipsISD::MAddu: return "MipsISD::MAddu";
68 case MipsISD::MSub: return "MipsISD::MSub";
69 case MipsISD::MSubu: return "MipsISD::MSubu";
70 case MipsISD::DivRem: return "MipsISD::DivRem";
71 case MipsISD::DivRemU: return "MipsISD::DivRemU";
72 case MipsISD::BuildPairF64: return "MipsISD::BuildPairF64";
73 case MipsISD::ExtractElementF64: return "MipsISD::ExtractElementF64";
Akira Hatanaka342837d2011-05-28 01:07:07 +000074 case MipsISD::WrapperPIC: return "MipsISD::WrapperPIC";
Akira Hatanaka21afc632011-06-21 00:40:49 +000075 case MipsISD::DynAlloc: return "MipsISD::DynAlloc";
Akira Hatanakadb548262011-07-19 23:30:50 +000076 case MipsISD::Sync: return "MipsISD::Sync";
Akira Hatanakabb15e112011-08-17 02:05:42 +000077 case MipsISD::Ext: return "MipsISD::Ext";
78 case MipsISD::Ins: return "MipsISD::Ins";
Akira Hatanaka0f843822011-06-07 18:58:42 +000079 default: return NULL;
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +000080 }
81}
82
83MipsTargetLowering::
Chris Lattnerf0144122009-07-28 03:13:23 +000084MipsTargetLowering(MipsTargetMachine &TM)
Chris Lattnerb71b9092009-08-13 06:28:06 +000085 : TargetLowering(TM, new MipsTargetObjectFile()) {
Bruno Cardoso Lopes225ca9c2008-07-05 19:05:21 +000086 Subtarget = &TM.getSubtarget<MipsSubtarget>();
87
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +000088 // Mips does not have i1 type, so use i32 for
Wesley Peckbf17cfa2010-11-23 03:31:01 +000089 // setcc operations results (slt, sgt, ...).
Duncan Sands03228082008-11-23 15:47:28 +000090 setBooleanContents(ZeroOrOneBooleanContent);
Duncan Sands28b77e92011-09-06 19:07:46 +000091 setBooleanVectorContents(ZeroOrOneBooleanContent); // FIXME: Is this correct?
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +000092
93 // Set up the register classes
Owen Anderson825b72b2009-08-11 20:47:22 +000094 addRegisterClass(MVT::i32, Mips::CPURegsRegisterClass);
95 addRegisterClass(MVT::f32, Mips::FGR32RegisterClass);
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +000096
Bruno Cardoso Lopes225ca9c2008-07-05 19:05:21 +000097 // When dealing with single precision only, use libcalls
Bruno Cardoso Lopesbdfbb742009-03-21 00:05:07 +000098 if (!Subtarget->isSingleFloat())
Bruno Cardoso Lopes225ca9c2008-07-05 19:05:21 +000099 if (!Subtarget->isFP64bit())
Owen Anderson825b72b2009-08-11 20:47:22 +0000100 addRegisterClass(MVT::f64, Mips::AFGR64RegisterClass);
Bruno Cardoso Lopes225ca9c2008-07-05 19:05:21 +0000101
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000102 // Load extented operations for i1 types must be promoted
Owen Anderson825b72b2009-08-11 20:47:22 +0000103 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
104 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
105 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +0000106
Eli Friedman6055a6a2009-07-17 04:07:24 +0000107 // MIPS doesn't have extending float->double load/store
Owen Anderson825b72b2009-08-11 20:47:22 +0000108 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
109 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
Eli Friedman10a36592009-07-17 02:28:12 +0000110
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000111 // Used by legalize types to correctly generate the setcc result.
112 // Without this, every float setcc comes with a AND/OR with the result,
113 // we don't want this, since the fpcmp result goes to a flag register,
Bruno Cardoso Lopes77283772008-07-31 18:31:28 +0000114 // which is used implicitly by brcond and select operations.
Owen Anderson825b72b2009-08-11 20:47:22 +0000115 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32);
Bruno Cardoso Lopes77283772008-07-31 18:31:28 +0000116
Bruno Cardoso Lopes97c25372008-07-09 04:15:08 +0000117 // Mips Custom Operations
Owen Anderson825b72b2009-08-11 20:47:22 +0000118 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
Bruno Cardoso Lopesca8a2aa2011-03-04 20:01:52 +0000119 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
Owen Anderson825b72b2009-08-11 20:47:22 +0000120 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
121 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
122 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
123 setOperationAction(ISD::SELECT, MVT::f32, Custom);
124 setOperationAction(ISD::SELECT, MVT::f64, Custom);
125 setOperationAction(ISD::SELECT, MVT::i32, Custom);
Owen Anderson825b72b2009-08-11 20:47:22 +0000126 setOperationAction(ISD::BRCOND, MVT::Other, Custom);
127 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
Bruno Cardoso Lopes6059b852010-02-06 21:00:02 +0000128 setOperationAction(ISD::VASTART, MVT::Other, Custom);
129
Bruno Cardoso Lopes38b5e862011-03-04 21:03:24 +0000130 setOperationAction(ISD::SDIV, MVT::i32, Expand);
131 setOperationAction(ISD::SREM, MVT::i32, Expand);
132 setOperationAction(ISD::UDIV, MVT::i32, Expand);
133 setOperationAction(ISD::UREM, MVT::i32, Expand);
134
Bruno Cardoso Lopes97c25372008-07-09 04:15:08 +0000135 // Operations not directly supported by Mips.
Owen Anderson825b72b2009-08-11 20:47:22 +0000136 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
137 setOperationAction(ISD::BR_CC, MVT::Other, Expand);
138 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
139 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
140 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
141 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
142 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
143 setOperationAction(ISD::CTTZ, MVT::i32, Expand);
144 setOperationAction(ISD::ROTL, MVT::i32, Expand);
Bruno Cardoso Lopes908b6dd2010-12-09 17:32:30 +0000145
146 if (!Subtarget->isMips32r2())
147 setOperationAction(ISD::ROTR, MVT::i32, Expand);
148
Owen Anderson825b72b2009-08-11 20:47:22 +0000149 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
150 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
151 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
Akira Hatanaka9c3d57c2011-05-25 19:32:07 +0000152 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
153 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
Owen Anderson825b72b2009-08-11 20:47:22 +0000154 setOperationAction(ISD::FSIN, MVT::f32, Expand);
Bruno Cardoso Lopes5d6fb5d2011-03-04 18:54:14 +0000155 setOperationAction(ISD::FSIN, MVT::f64, Expand);
Owen Anderson825b72b2009-08-11 20:47:22 +0000156 setOperationAction(ISD::FCOS, MVT::f32, Expand);
Bruno Cardoso Lopes5d6fb5d2011-03-04 18:54:14 +0000157 setOperationAction(ISD::FCOS, MVT::f64, Expand);
Owen Anderson825b72b2009-08-11 20:47:22 +0000158 setOperationAction(ISD::FPOWI, MVT::f32, Expand);
159 setOperationAction(ISD::FPOW, MVT::f32, Expand);
Akira Hatanaka46da1362011-05-23 22:23:58 +0000160 setOperationAction(ISD::FPOW, MVT::f64, Expand);
Owen Anderson825b72b2009-08-11 20:47:22 +0000161 setOperationAction(ISD::FLOG, MVT::f32, Expand);
162 setOperationAction(ISD::FLOG2, MVT::f32, Expand);
163 setOperationAction(ISD::FLOG10, MVT::f32, Expand);
164 setOperationAction(ISD::FEXP, MVT::f32, Expand);
Cameron Zwarich33390842011-07-08 21:39:21 +0000165 setOperationAction(ISD::FMA, MVT::f32, Expand);
166 setOperationAction(ISD::FMA, MVT::f64, Expand);
Bruno Cardoso Lopes97c25372008-07-09 04:15:08 +0000167
Akira Hatanakacf0cd802011-05-26 18:59:03 +0000168 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
169 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
Eric Christopher471e4222011-06-08 23:55:35 +0000170
Bruno Cardoso Lopes954dac02011-03-09 19:22:22 +0000171 setOperationAction(ISD::VAARG, MVT::Other, Expand);
172 setOperationAction(ISD::VACOPY, MVT::Other, Expand);
173 setOperationAction(ISD::VAEND, MVT::Other, Expand);
174
Bruno Cardoso Lopes97c25372008-07-09 04:15:08 +0000175 // Use the default for now
Owen Anderson825b72b2009-08-11 20:47:22 +0000176 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
177 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
Eli Friedman14648462011-07-27 22:21:52 +0000178
Akira Hatanakadb548262011-07-19 23:30:50 +0000179 setOperationAction(ISD::MEMBARRIER, MVT::Other, Custom);
Eli Friedman14648462011-07-27 22:21:52 +0000180 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom);
Bruno Cardoso Lopes85e92122008-07-07 19:11:24 +0000181
Eli Friedman4db5aca2011-08-29 18:23:02 +0000182 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Expand);
183 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Expand);
184
Eli Friedman26689ac2011-08-03 21:06:02 +0000185 setInsertFencesForAtomic(true);
186
Bruno Cardoso Lopesea9d4d62008-08-04 06:44:31 +0000187 if (Subtarget->isSingleFloat())
Owen Anderson825b72b2009-08-11 20:47:22 +0000188 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand);
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +0000189
Bruno Cardoso Lopes7728f7e2008-07-09 05:32:22 +0000190 if (!Subtarget->hasSEInReg()) {
Owen Anderson825b72b2009-08-11 20:47:22 +0000191 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
192 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
Bruno Cardoso Lopes225ca9c2008-07-05 19:05:21 +0000193 }
194
Bruno Cardoso Lopes65ad4522008-08-08 06:16:31 +0000195 if (!Subtarget->hasBitCount())
Owen Anderson825b72b2009-08-11 20:47:22 +0000196 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
Bruno Cardoso Lopes65ad4522008-08-08 06:16:31 +0000197
Bruno Cardoso Lopes739e4412008-08-13 07:13:40 +0000198 if (!Subtarget->hasSwap())
Owen Anderson825b72b2009-08-11 20:47:22 +0000199 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
Bruno Cardoso Lopes739e4412008-08-13 07:13:40 +0000200
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000201 setTargetDAGCombine(ISD::ADDE);
202 setTargetDAGCombine(ISD::SUBE);
Bruno Cardoso Lopes38b5e862011-03-04 21:03:24 +0000203 setTargetDAGCombine(ISD::SDIVREM);
204 setTargetDAGCombine(ISD::UDIVREM);
Akira Hatanaka1d6b38d2011-03-31 18:26:17 +0000205 setTargetDAGCombine(ISD::SETCC);
Akira Hatanaka77b85b62011-08-17 17:45:08 +0000206 setTargetDAGCombine(ISD::AND);
207 setTargetDAGCombine(ISD::OR);
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000208
Eli Friedmanfc5d3052011-05-06 20:34:06 +0000209 setMinFunctionAlignment(2);
210
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +0000211 setStackPointerRegisterToSaveRestore(Mips::SP);
212 computeRegisterProperties();
Akira Hatanakacf0cd802011-05-26 18:59:03 +0000213
214 setExceptionPointerRegister(Mips::A0);
215 setExceptionSelectorRegister(Mips::A1);
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +0000216}
217
Akira Hatanaka5c21c9e2011-08-12 21:30:06 +0000218bool MipsTargetLowering::allowsUnalignedMemoryAccesses(EVT VT) const {
Akira Hatanaka511961a2011-08-17 18:49:18 +0000219 MVT::SimpleValueType SVT = VT.getSimpleVT().SimpleTy;
220 return SVT == MVT::i32 || SVT == MVT::i16;
Akira Hatanaka5c21c9e2011-08-12 21:30:06 +0000221}
222
Duncan Sands28b77e92011-09-06 19:07:46 +0000223EVT MipsTargetLowering::getSetCCResultType(EVT VT) const {
Owen Anderson825b72b2009-08-11 20:47:22 +0000224 return MVT::i32;
Scott Michel5b8f82e2008-03-10 15:42:14 +0000225}
226
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000227// SelectMadd -
228// Transforms a subgraph in CurDAG if the following pattern is found:
229// (addc multLo, Lo0), (adde multHi, Hi0),
230// where,
231// multHi/Lo: product of multiplication
Bruno Cardoso Lopes8e826e62011-02-10 18:05:10 +0000232// Lo0: initial value of Lo register
233// Hi0: initial value of Hi register
Akira Hatanaka81bd78b2011-03-30 21:15:35 +0000234// Return true if pattern matching was successful.
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000235static bool SelectMadd(SDNode* ADDENode, SelectionDAG* CurDAG) {
Bruno Cardoso Lopes8e826e62011-02-10 18:05:10 +0000236 // ADDENode's second operand must be a flag output of an ADDC node in order
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000237 // for the matching to be successful.
238 SDNode* ADDCNode = ADDENode->getOperand(2).getNode();
239
240 if (ADDCNode->getOpcode() != ISD::ADDC)
241 return false;
242
243 SDValue MultHi = ADDENode->getOperand(0);
244 SDValue MultLo = ADDCNode->getOperand(0);
Bruno Cardoso Lopes8e826e62011-02-10 18:05:10 +0000245 SDNode* MultNode = MultHi.getNode();
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000246 unsigned MultOpc = MultHi.getOpcode();
247
248 // MultHi and MultLo must be generated by the same node,
249 if (MultLo.getNode() != MultNode)
250 return false;
251
252 // and it must be a multiplication.
253 if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI)
254 return false;
Bruno Cardoso Lopes8e826e62011-02-10 18:05:10 +0000255
256 // MultLo amd MultHi must be the first and second output of MultNode
257 // respectively.
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000258 if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0)
259 return false;
260
Bruno Cardoso Lopes8e826e62011-02-10 18:05:10 +0000261 // Transform this to a MADD only if ADDENode and ADDCNode are the only users
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000262 // of the values of MultNode, in which case MultNode will be removed in later
263 // phases.
Akira Hatanaka4552c9a2011-04-15 21:51:11 +0000264 // If there exist users other than ADDENode or ADDCNode, this function returns
265 // here, which will result in MultNode being mapped to a single MULT
Bruno Cardoso Lopes8e826e62011-02-10 18:05:10 +0000266 // instruction node rather than a pair of MULT and MADD instructions being
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000267 // produced.
268 if (!MultHi.hasOneUse() || !MultLo.hasOneUse())
269 return false;
270
Bruno Cardoso Lopes8e826e62011-02-10 18:05:10 +0000271 SDValue Chain = CurDAG->getEntryNode();
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000272 DebugLoc dl = ADDENode->getDebugLoc();
273
274 // create MipsMAdd(u) node
275 MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MAddu : MipsISD::MAdd;
Bruno Cardoso Lopes8e826e62011-02-10 18:05:10 +0000276
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000277 SDValue MAdd = CurDAG->getNode(MultOpc, dl,
278 MVT::Glue,
279 MultNode->getOperand(0),// Factor 0
280 MultNode->getOperand(1),// Factor 1
Bruno Cardoso Lopes8e826e62011-02-10 18:05:10 +0000281 ADDCNode->getOperand(1),// Lo0
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000282 ADDENode->getOperand(1));// Hi0
283
284 // create CopyFromReg nodes
285 SDValue CopyFromLo = CurDAG->getCopyFromReg(Chain, dl, Mips::LO, MVT::i32,
286 MAdd);
Bruno Cardoso Lopes8e826e62011-02-10 18:05:10 +0000287 SDValue CopyFromHi = CurDAG->getCopyFromReg(CopyFromLo.getValue(1), dl,
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000288 Mips::HI, MVT::i32,
289 CopyFromLo.getValue(2));
290
291 // replace uses of adde and addc here
292 if (!SDValue(ADDCNode, 0).use_empty())
293 CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDCNode, 0), CopyFromLo);
294
295 if (!SDValue(ADDENode, 0).use_empty())
296 CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDENode, 0), CopyFromHi);
297
Bruno Cardoso Lopes8e826e62011-02-10 18:05:10 +0000298 return true;
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000299}
300
301// SelectMsub -
302// Transforms a subgraph in CurDAG if the following pattern is found:
303// (addc Lo0, multLo), (sube Hi0, multHi),
304// where,
305// multHi/Lo: product of multiplication
Bruno Cardoso Lopes8e826e62011-02-10 18:05:10 +0000306// Lo0: initial value of Lo register
307// Hi0: initial value of Hi register
Akira Hatanaka81bd78b2011-03-30 21:15:35 +0000308// Return true if pattern matching was successful.
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000309static bool SelectMsub(SDNode* SUBENode, SelectionDAG* CurDAG) {
Bruno Cardoso Lopes8e826e62011-02-10 18:05:10 +0000310 // SUBENode's second operand must be a flag output of an SUBC node in order
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000311 // for the matching to be successful.
312 SDNode* SUBCNode = SUBENode->getOperand(2).getNode();
313
314 if (SUBCNode->getOpcode() != ISD::SUBC)
315 return false;
316
317 SDValue MultHi = SUBENode->getOperand(1);
318 SDValue MultLo = SUBCNode->getOperand(1);
Bruno Cardoso Lopes8e826e62011-02-10 18:05:10 +0000319 SDNode* MultNode = MultHi.getNode();
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000320 unsigned MultOpc = MultHi.getOpcode();
321
322 // MultHi and MultLo must be generated by the same node,
323 if (MultLo.getNode() != MultNode)
324 return false;
325
326 // and it must be a multiplication.
327 if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI)
328 return false;
329
330 // MultLo amd MultHi must be the first and second output of MultNode
331 // respectively.
332 if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0)
333 return false;
334
335 // Transform this to a MSUB only if SUBENode and SUBCNode are the only users
336 // of the values of MultNode, in which case MultNode will be removed in later
337 // phases.
Akira Hatanaka4552c9a2011-04-15 21:51:11 +0000338 // If there exist users other than SUBENode or SUBCNode, this function returns
339 // here, which will result in MultNode being mapped to a single MULT
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000340 // instruction node rather than a pair of MULT and MSUB instructions being
341 // produced.
342 if (!MultHi.hasOneUse() || !MultLo.hasOneUse())
343 return false;
344
345 SDValue Chain = CurDAG->getEntryNode();
346 DebugLoc dl = SUBENode->getDebugLoc();
347
348 // create MipsSub(u) node
349 MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MSubu : MipsISD::MSub;
350
351 SDValue MSub = CurDAG->getNode(MultOpc, dl,
352 MVT::Glue,
353 MultNode->getOperand(0),// Factor 0
354 MultNode->getOperand(1),// Factor 1
355 SUBCNode->getOperand(0),// Lo0
356 SUBENode->getOperand(0));// Hi0
357
358 // create CopyFromReg nodes
359 SDValue CopyFromLo = CurDAG->getCopyFromReg(Chain, dl, Mips::LO, MVT::i32,
360 MSub);
361 SDValue CopyFromHi = CurDAG->getCopyFromReg(CopyFromLo.getValue(1), dl,
362 Mips::HI, MVT::i32,
363 CopyFromLo.getValue(2));
364
365 // replace uses of sube and subc here
366 if (!SDValue(SUBCNode, 0).use_empty())
367 CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBCNode, 0), CopyFromLo);
368
369 if (!SDValue(SUBENode, 0).use_empty())
370 CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBENode, 0), CopyFromHi);
371
372 return true;
373}
374
375static SDValue PerformADDECombine(SDNode *N, SelectionDAG& DAG,
376 TargetLowering::DAGCombinerInfo &DCI,
377 const MipsSubtarget* Subtarget) {
378 if (DCI.isBeforeLegalize())
379 return SDValue();
380
381 if (Subtarget->isMips32() && SelectMadd(N, &DAG))
382 return SDValue(N, 0);
Bruno Cardoso Lopes8e826e62011-02-10 18:05:10 +0000383
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000384 return SDValue();
Bruno Cardoso Lopes8e826e62011-02-10 18:05:10 +0000385}
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000386
387static SDValue PerformSUBECombine(SDNode *N, SelectionDAG& DAG,
388 TargetLowering::DAGCombinerInfo &DCI,
389 const MipsSubtarget* Subtarget) {
390 if (DCI.isBeforeLegalize())
391 return SDValue();
392
393 if (Subtarget->isMips32() && SelectMsub(N, &DAG))
394 return SDValue(N, 0);
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000395
Bruno Cardoso Lopes8e826e62011-02-10 18:05:10 +0000396 return SDValue();
397}
398
Bruno Cardoso Lopes38b5e862011-03-04 21:03:24 +0000399static SDValue PerformDivRemCombine(SDNode *N, SelectionDAG& DAG,
400 TargetLowering::DAGCombinerInfo &DCI,
401 const MipsSubtarget* Subtarget) {
402 if (DCI.isBeforeLegalizeOps())
403 return SDValue();
404
405 unsigned opc = N->getOpcode() == ISD::SDIVREM ? MipsISD::DivRem :
406 MipsISD::DivRemU;
407 DebugLoc dl = N->getDebugLoc();
408
409 SDValue DivRem = DAG.getNode(opc, dl, MVT::Glue,
410 N->getOperand(0), N->getOperand(1));
411 SDValue InChain = DAG.getEntryNode();
412 SDValue InGlue = DivRem;
413
414 // insert MFLO
415 if (N->hasAnyUseOfValue(0)) {
416 SDValue CopyFromLo = DAG.getCopyFromReg(InChain, dl, Mips::LO, MVT::i32,
417 InGlue);
418 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), CopyFromLo);
419 InChain = CopyFromLo.getValue(1);
420 InGlue = CopyFromLo.getValue(2);
421 }
422
423 // insert MFHI
424 if (N->hasAnyUseOfValue(1)) {
425 SDValue CopyFromHi = DAG.getCopyFromReg(InChain, dl,
Akira Hatanakabdd2ce92011-05-23 21:13:59 +0000426 Mips::HI, MVT::i32, InGlue);
Bruno Cardoso Lopes38b5e862011-03-04 21:03:24 +0000427 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), CopyFromHi);
428 }
429
430 return SDValue();
431}
432
Akira Hatanaka1d6b38d2011-03-31 18:26:17 +0000433static Mips::CondCode FPCondCCodeToFCC(ISD::CondCode CC) {
434 switch (CC) {
435 default: llvm_unreachable("Unknown fp condition code!");
436 case ISD::SETEQ:
437 case ISD::SETOEQ: return Mips::FCOND_OEQ;
438 case ISD::SETUNE: return Mips::FCOND_UNE;
439 case ISD::SETLT:
440 case ISD::SETOLT: return Mips::FCOND_OLT;
441 case ISD::SETGT:
442 case ISD::SETOGT: return Mips::FCOND_OGT;
443 case ISD::SETLE:
444 case ISD::SETOLE: return Mips::FCOND_OLE;
445 case ISD::SETGE:
446 case ISD::SETOGE: return Mips::FCOND_OGE;
447 case ISD::SETULT: return Mips::FCOND_ULT;
448 case ISD::SETULE: return Mips::FCOND_ULE;
449 case ISD::SETUGT: return Mips::FCOND_UGT;
450 case ISD::SETUGE: return Mips::FCOND_UGE;
451 case ISD::SETUO: return Mips::FCOND_UN;
452 case ISD::SETO: return Mips::FCOND_OR;
453 case ISD::SETNE:
454 case ISD::SETONE: return Mips::FCOND_ONE;
455 case ISD::SETUEQ: return Mips::FCOND_UEQ;
456 }
457}
458
459
460// Returns true if condition code has to be inverted.
461static bool InvertFPCondCode(Mips::CondCode CC) {
462 if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT)
463 return false;
464
465 if (CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT)
466 return true;
467
468 assert(false && "Illegal Condition Code");
469 return false;
470}
471
472// Creates and returns an FPCmp node from a setcc node.
473// Returns Op if setcc is not a floating point comparison.
474static SDValue CreateFPCmp(SelectionDAG& DAG, const SDValue& Op) {
475 // must be a SETCC node
476 if (Op.getOpcode() != ISD::SETCC)
477 return Op;
478
479 SDValue LHS = Op.getOperand(0);
480
481 if (!LHS.getValueType().isFloatingPoint())
482 return Op;
483
484 SDValue RHS = Op.getOperand(1);
485 DebugLoc dl = Op.getDebugLoc();
486
Akira Hatanaka0bf3dfb2011-04-15 21:00:26 +0000487 // Assume the 3rd operand is a CondCodeSDNode. Add code to check the type of
488 // node if necessary.
Akira Hatanaka1d6b38d2011-03-31 18:26:17 +0000489 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
490
491 return DAG.getNode(MipsISD::FPCmp, dl, MVT::Glue, LHS, RHS,
492 DAG.getConstant(FPCondCCodeToFCC(CC), MVT::i32));
493}
494
495// Creates and returns a CMovFPT/F node.
496static SDValue CreateCMovFP(SelectionDAG& DAG, SDValue Cond, SDValue True,
497 SDValue False, DebugLoc DL) {
498 bool invert = InvertFPCondCode((Mips::CondCode)
499 cast<ConstantSDNode>(Cond.getOperand(2))
500 ->getSExtValue());
501
502 return DAG.getNode((invert ? MipsISD::CMovFP_F : MipsISD::CMovFP_T), DL,
503 True.getValueType(), True, False, Cond);
504}
505
506static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG& DAG,
507 TargetLowering::DAGCombinerInfo &DCI,
508 const MipsSubtarget* Subtarget) {
509 if (DCI.isBeforeLegalizeOps())
510 return SDValue();
511
512 SDValue Cond = CreateFPCmp(DAG, SDValue(N, 0));
513
514 if (Cond.getOpcode() != MipsISD::FPCmp)
515 return SDValue();
516
517 SDValue True = DAG.getConstant(1, MVT::i32);
518 SDValue False = DAG.getConstant(0, MVT::i32);
519
520 return CreateCMovFP(DAG, Cond, True, False, N->getDebugLoc());
521}
522
Akira Hatanaka77b85b62011-08-17 17:45:08 +0000523static SDValue PerformANDCombine(SDNode *N, SelectionDAG& DAG,
524 TargetLowering::DAGCombinerInfo &DCI,
525 const MipsSubtarget* Subtarget) {
526 // Pattern match EXT.
527 // $dst = and ((sra or srl) $src , pos), (2**size - 1)
528 // => ext $dst, $src, size, pos
529 if (DCI.isBeforeLegalizeOps() || !Subtarget->isMips32r2())
530 return SDValue();
531
532 SDValue ShiftRight = N->getOperand(0), Mask = N->getOperand(1);
533
534 // Op's first operand must be a shift right.
535 if (ShiftRight.getOpcode() != ISD::SRA && ShiftRight.getOpcode() != ISD::SRL)
536 return SDValue();
537
538 // The second operand of the shift must be an immediate.
539 uint64_t Pos;
540 ConstantSDNode *CN;
541 if (!(CN = dyn_cast<ConstantSDNode>(ShiftRight.getOperand(1))))
542 return SDValue();
543
544 Pos = CN->getZExtValue();
545
546 uint64_t SMPos, SMSize;
547 // Op's second operand must be a shifted mask.
548 if (!(CN = dyn_cast<ConstantSDNode>(Mask)) ||
Akira Hatanaka854a7db2011-08-19 22:59:00 +0000549 !IsShiftedMask(CN->getZExtValue(), SMPos, SMSize))
Akira Hatanaka77b85b62011-08-17 17:45:08 +0000550 return SDValue();
551
552 // Return if the shifted mask does not start at bit 0 or the sum of its size
553 // and Pos exceeds the word's size.
554 if (SMPos != 0 || Pos + SMSize > 32)
555 return SDValue();
556
557 return DAG.getNode(MipsISD::Ext, N->getDebugLoc(), MVT::i32,
558 ShiftRight.getOperand(0),
Akira Hatanaka667645f2011-08-17 22:59:46 +0000559 DAG.getConstant(Pos, MVT::i32),
560 DAG.getConstant(SMSize, MVT::i32));
Akira Hatanaka77b85b62011-08-17 17:45:08 +0000561}
562
563static SDValue PerformORCombine(SDNode *N, SelectionDAG& DAG,
564 TargetLowering::DAGCombinerInfo &DCI,
565 const MipsSubtarget* Subtarget) {
566 // Pattern match INS.
567 // $dst = or (and $src1 , mask0), (and (shl $src, pos), mask1),
568 // where mask1 = (2**size - 1) << pos, mask0 = ~mask1
569 // => ins $dst, $src, size, pos, $src1
570 if (DCI.isBeforeLegalizeOps() || !Subtarget->isMips32r2())
571 return SDValue();
572
573 SDValue And0 = N->getOperand(0), And1 = N->getOperand(1);
574 uint64_t SMPos0, SMSize0, SMPos1, SMSize1;
575 ConstantSDNode *CN;
576
577 // See if Op's first operand matches (and $src1 , mask0).
578 if (And0.getOpcode() != ISD::AND)
579 return SDValue();
580
581 if (!(CN = dyn_cast<ConstantSDNode>(And0.getOperand(1))) ||
Akira Hatanaka854a7db2011-08-19 22:59:00 +0000582 !IsShiftedMask(~CN->getSExtValue(), SMPos0, SMSize0))
Akira Hatanaka77b85b62011-08-17 17:45:08 +0000583 return SDValue();
584
585 // See if Op's second operand matches (and (shl $src, pos), mask1).
586 if (And1.getOpcode() != ISD::AND)
587 return SDValue();
588
589 if (!(CN = dyn_cast<ConstantSDNode>(And1.getOperand(1))) ||
Akira Hatanaka854a7db2011-08-19 22:59:00 +0000590 !IsShiftedMask(CN->getZExtValue(), SMPos1, SMSize1))
Akira Hatanaka77b85b62011-08-17 17:45:08 +0000591 return SDValue();
592
593 // The shift masks must have the same position and size.
594 if (SMPos0 != SMPos1 || SMSize0 != SMSize1)
595 return SDValue();
596
597 SDValue Shl = And1.getOperand(0);
598 if (Shl.getOpcode() != ISD::SHL)
599 return SDValue();
600
601 if (!(CN = dyn_cast<ConstantSDNode>(Shl.getOperand(1))))
602 return SDValue();
603
604 unsigned Shamt = CN->getZExtValue();
605
606 // Return if the shift amount and the first bit position of mask are not the
607 // same.
608 if (Shamt != SMPos0)
609 return SDValue();
610
611 return DAG.getNode(MipsISD::Ins, N->getDebugLoc(), MVT::i32,
612 Shl.getOperand(0),
Akira Hatanaka77b85b62011-08-17 17:45:08 +0000613 DAG.getConstant(SMPos0, MVT::i32),
Akira Hatanaka667645f2011-08-17 22:59:46 +0000614 DAG.getConstant(SMSize0, MVT::i32),
Akira Hatanaka77b85b62011-08-17 17:45:08 +0000615 And0.getOperand(0));
616}
617
Bruno Cardoso Lopes8e826e62011-02-10 18:05:10 +0000618SDValue MipsTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI)
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000619 const {
620 SelectionDAG &DAG = DCI.DAG;
621 unsigned opc = N->getOpcode();
622
623 switch (opc) {
624 default: break;
625 case ISD::ADDE:
626 return PerformADDECombine(N, DAG, DCI, Subtarget);
627 case ISD::SUBE:
628 return PerformSUBECombine(N, DAG, DCI, Subtarget);
Bruno Cardoso Lopes38b5e862011-03-04 21:03:24 +0000629 case ISD::SDIVREM:
630 case ISD::UDIVREM:
631 return PerformDivRemCombine(N, DAG, DCI, Subtarget);
Akira Hatanaka1d6b38d2011-03-31 18:26:17 +0000632 case ISD::SETCC:
633 return PerformSETCCCombine(N, DAG, DCI, Subtarget);
Akira Hatanaka77b85b62011-08-17 17:45:08 +0000634 case ISD::AND:
635 return PerformANDCombine(N, DAG, DCI, Subtarget);
636 case ISD::OR:
637 return PerformORCombine(N, DAG, DCI, Subtarget);
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000638 }
639
640 return SDValue();
641}
642
Dan Gohman475871a2008-07-27 21:46:04 +0000643SDValue MipsTargetLowering::
Dan Gohmand858e902010-04-17 15:26:15 +0000644LowerOperation(SDValue Op, SelectionDAG &DAG) const
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +0000645{
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000646 switch (Op.getOpcode())
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +0000647 {
Bruno Cardoso Lopes7da151c2008-08-07 19:08:11 +0000648 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
Bruno Cardoso Lopes7da151c2008-08-07 19:08:11 +0000649 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
650 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
Bruno Cardoso Lopes7da151c2008-08-07 19:08:11 +0000651 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
Bruno Cardoso Lopesca8a2aa2011-03-04 20:01:52 +0000652 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
Bruno Cardoso Lopes7da151c2008-08-07 19:08:11 +0000653 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
654 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
Bruno Cardoso Lopes7da151c2008-08-07 19:08:11 +0000655 case ISD::SELECT: return LowerSELECT(Op, DAG);
Bruno Cardoso Lopes6059b852010-02-06 21:00:02 +0000656 case ISD::VASTART: return LowerVASTART(Op, DAG);
Akira Hatanaka9c3d57c2011-05-25 19:32:07 +0000657 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
Akira Hatanaka2e591472011-06-02 00:24:44 +0000658 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
Akira Hatanakadb548262011-07-19 23:30:50 +0000659 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op, DAG);
Eli Friedman14648462011-07-27 22:21:52 +0000660 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, DAG);
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +0000661 }
Dan Gohman475871a2008-07-27 21:46:04 +0000662 return SDValue();
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +0000663}
664
Akira Hatanaka4552c9a2011-04-15 21:51:11 +0000665//===----------------------------------------------------------------------===//
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +0000666// Lower helper functions
Akira Hatanaka4552c9a2011-04-15 21:51:11 +0000667//===----------------------------------------------------------------------===//
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +0000668
669// AddLiveIn - This helper function adds the specified physical register to the
670// MachineFunction as a live in value. It also creates a corresponding
671// virtual register for it.
672static unsigned
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000673AddLiveIn(MachineFunction &MF, unsigned PReg, TargetRegisterClass *RC)
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +0000674{
675 assert(RC->contains(PReg) && "Not the correct regclass!");
Chris Lattner84bc5422007-12-31 04:13:23 +0000676 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC);
677 MF.getRegInfo().addLiveIn(PReg, VReg);
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +0000678 return VReg;
679}
680
Bruno Cardoso Lopes85e31e32008-07-28 19:11:24 +0000681// Get fp branch code (not opcode) from condition code.
682static Mips::FPBranchCode GetFPBranchCodeFromCond(Mips::CondCode CC) {
683 if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT)
684 return Mips::BRANCH_T;
685
686 if (CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT)
687 return Mips::BRANCH_F;
688
689 return Mips::BRANCH_INVALID;
690}
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000691
Akira Hatanaka14487d42011-06-07 19:28:39 +0000692static MachineBasicBlock* ExpandCondMov(MachineInstr *MI, MachineBasicBlock *BB,
693 DebugLoc dl,
694 const MipsSubtarget* Subtarget,
695 const TargetInstrInfo *TII,
696 bool isFPCmp, unsigned Opc) {
697 // There is no need to expand CMov instructions if target has
698 // conditional moves.
699 if (Subtarget->hasCondMov())
700 return BB;
701
702 // To "insert" a SELECT_CC instruction, we actually have to insert the
703 // diamond control-flow pattern. The incoming instruction knows the
704 // destination vreg to set, the condition code register to branch on, the
705 // true/false values to select between, and a branch opcode to use.
706 const BasicBlock *LLVM_BB = BB->getBasicBlock();
707 MachineFunction::iterator It = BB;
708 ++It;
709
710 // thisMBB:
711 // ...
712 // TrueVal = ...
713 // setcc r1, r2, r3
714 // bNE r1, r0, copy1MBB
715 // fallthrough --> copy0MBB
716 MachineBasicBlock *thisMBB = BB;
717 MachineFunction *F = BB->getParent();
718 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
719 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
720 F->insert(It, copy0MBB);
721 F->insert(It, sinkMBB);
722
723 // Transfer the remainder of BB and its successor edges to sinkMBB.
724 sinkMBB->splice(sinkMBB->begin(), BB,
725 llvm::next(MachineBasicBlock::iterator(MI)),
726 BB->end());
727 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
728
729 // Next, add the true and fallthrough blocks as its successors.
730 BB->addSuccessor(copy0MBB);
731 BB->addSuccessor(sinkMBB);
732
733 // Emit the right instruction according to the type of the operands compared
734 if (isFPCmp)
735 BuildMI(BB, dl, TII->get(Opc)).addMBB(sinkMBB);
736 else
737 BuildMI(BB, dl, TII->get(Opc)).addReg(MI->getOperand(2).getReg())
738 .addReg(Mips::ZERO).addMBB(sinkMBB);
739
740 // copy0MBB:
741 // %FalseValue = ...
742 // # fallthrough to sinkMBB
743 BB = copy0MBB;
744
745 // Update machine-CFG edges
746 BB->addSuccessor(sinkMBB);
747
748 // sinkMBB:
749 // %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ]
750 // ...
751 BB = sinkMBB;
752
753 if (isFPCmp)
754 BuildMI(*BB, BB->begin(), dl,
755 TII->get(Mips::PHI), MI->getOperand(0).getReg())
756 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB)
757 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB);
758 else
759 BuildMI(*BB, BB->begin(), dl,
760 TII->get(Mips::PHI), MI->getOperand(0).getReg())
761 .addReg(MI->getOperand(3).getReg()).addMBB(thisMBB)
762 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB);
763
764 MI->eraseFromParent(); // The pseudo instruction is gone now.
765 return BB;
766}
767
Bruno Cardoso Lopes6d399bd2008-07-29 19:05:28 +0000768MachineBasicBlock *
769MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
Dan Gohmanaf1d8ca2010-05-01 00:01:06 +0000770 MachineBasicBlock *BB) const {
Bruno Cardoso Lopes6d399bd2008-07-29 19:05:28 +0000771 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
Dale Johannesen94817572009-02-13 02:34:39 +0000772 DebugLoc dl = MI->getDebugLoc();
Bruno Cardoso Lopes6d399bd2008-07-29 19:05:28 +0000773
774 switch (MI->getOpcode()) {
Akira Hatanaka14487d42011-06-07 19:28:39 +0000775 default:
776 assert(false && "Unexpected instr type to insert");
777 return NULL;
778 case Mips::MOVT:
779 case Mips::MOVT_S:
780 case Mips::MOVT_D:
781 return ExpandCondMov(MI, BB, dl, Subtarget, TII, true, Mips::BC1F);
782 case Mips::MOVF:
783 case Mips::MOVF_S:
784 case Mips::MOVF_D:
785 return ExpandCondMov(MI, BB, dl, Subtarget, TII, true, Mips::BC1T);
786 case Mips::MOVZ_I:
787 case Mips::MOVZ_S:
788 case Mips::MOVZ_D:
789 return ExpandCondMov(MI, BB, dl, Subtarget, TII, false, Mips::BNE);
790 case Mips::MOVN_I:
791 case Mips::MOVN_S:
792 case Mips::MOVN_D:
793 return ExpandCondMov(MI, BB, dl, Subtarget, TII, false, Mips::BEQ);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000794
795 case Mips::ATOMIC_LOAD_ADD_I8:
796 return EmitAtomicBinaryPartword(MI, BB, 1, Mips::ADDu);
797 case Mips::ATOMIC_LOAD_ADD_I16:
798 return EmitAtomicBinaryPartword(MI, BB, 2, Mips::ADDu);
799 case Mips::ATOMIC_LOAD_ADD_I32:
800 return EmitAtomicBinary(MI, BB, 4, Mips::ADDu);
801
802 case Mips::ATOMIC_LOAD_AND_I8:
803 return EmitAtomicBinaryPartword(MI, BB, 1, Mips::AND);
804 case Mips::ATOMIC_LOAD_AND_I16:
805 return EmitAtomicBinaryPartword(MI, BB, 2, Mips::AND);
806 case Mips::ATOMIC_LOAD_AND_I32:
807 return EmitAtomicBinary(MI, BB, 4, Mips::AND);
808
809 case Mips::ATOMIC_LOAD_OR_I8:
810 return EmitAtomicBinaryPartword(MI, BB, 1, Mips::OR);
811 case Mips::ATOMIC_LOAD_OR_I16:
812 return EmitAtomicBinaryPartword(MI, BB, 2, Mips::OR);
813 case Mips::ATOMIC_LOAD_OR_I32:
814 return EmitAtomicBinary(MI, BB, 4, Mips::OR);
815
816 case Mips::ATOMIC_LOAD_XOR_I8:
817 return EmitAtomicBinaryPartword(MI, BB, 1, Mips::XOR);
818 case Mips::ATOMIC_LOAD_XOR_I16:
819 return EmitAtomicBinaryPartword(MI, BB, 2, Mips::XOR);
820 case Mips::ATOMIC_LOAD_XOR_I32:
821 return EmitAtomicBinary(MI, BB, 4, Mips::XOR);
822
823 case Mips::ATOMIC_LOAD_NAND_I8:
824 return EmitAtomicBinaryPartword(MI, BB, 1, 0, true);
825 case Mips::ATOMIC_LOAD_NAND_I16:
826 return EmitAtomicBinaryPartword(MI, BB, 2, 0, true);
827 case Mips::ATOMIC_LOAD_NAND_I32:
828 return EmitAtomicBinary(MI, BB, 4, 0, true);
829
830 case Mips::ATOMIC_LOAD_SUB_I8:
831 return EmitAtomicBinaryPartword(MI, BB, 1, Mips::SUBu);
832 case Mips::ATOMIC_LOAD_SUB_I16:
833 return EmitAtomicBinaryPartword(MI, BB, 2, Mips::SUBu);
834 case Mips::ATOMIC_LOAD_SUB_I32:
835 return EmitAtomicBinary(MI, BB, 4, Mips::SUBu);
836
837 case Mips::ATOMIC_SWAP_I8:
838 return EmitAtomicBinaryPartword(MI, BB, 1, 0);
839 case Mips::ATOMIC_SWAP_I16:
840 return EmitAtomicBinaryPartword(MI, BB, 2, 0);
841 case Mips::ATOMIC_SWAP_I32:
842 return EmitAtomicBinary(MI, BB, 4, 0);
843
844 case Mips::ATOMIC_CMP_SWAP_I8:
845 return EmitAtomicCmpSwapPartword(MI, BB, 1);
846 case Mips::ATOMIC_CMP_SWAP_I16:
847 return EmitAtomicCmpSwapPartword(MI, BB, 2);
848 case Mips::ATOMIC_CMP_SWAP_I32:
849 return EmitAtomicCmpSwap(MI, BB, 4);
Akira Hatanaka1d6b38d2011-03-31 18:26:17 +0000850 }
Bruno Cardoso Lopes6d399bd2008-07-29 19:05:28 +0000851}
852
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000853// This function also handles Mips::ATOMIC_SWAP_I32 (when BinOpcode == 0), and
854// Mips::ATOMIC_LOAD_NAND_I32 (when Nand == true)
855MachineBasicBlock *
856MipsTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
Eric Christopher471e4222011-06-08 23:55:35 +0000857 unsigned Size, unsigned BinOpcode,
Akira Hatanaka0f843822011-06-07 18:58:42 +0000858 bool Nand) const {
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000859 assert(Size == 4 && "Unsupported size for EmitAtomicBinary.");
860
861 MachineFunction *MF = BB->getParent();
862 MachineRegisterInfo &RegInfo = MF->getRegInfo();
863 const TargetRegisterClass *RC = getRegClassFor(MVT::i32);
864 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
865 DebugLoc dl = MI->getDebugLoc();
866
Akira Hatanaka4061da12011-07-19 20:11:17 +0000867 unsigned OldVal = MI->getOperand(0).getReg();
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000868 unsigned Ptr = MI->getOperand(1).getReg();
869 unsigned Incr = MI->getOperand(2).getReg();
870
Akira Hatanaka4061da12011-07-19 20:11:17 +0000871 unsigned StoreVal = RegInfo.createVirtualRegister(RC);
872 unsigned AndRes = RegInfo.createVirtualRegister(RC);
873 unsigned Success = RegInfo.createVirtualRegister(RC);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000874
875 // insert new blocks after the current block
876 const BasicBlock *LLVM_BB = BB->getBasicBlock();
877 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
878 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
879 MachineFunction::iterator It = BB;
880 ++It;
881 MF->insert(It, loopMBB);
882 MF->insert(It, exitMBB);
883
884 // Transfer the remainder of BB and its successor edges to exitMBB.
885 exitMBB->splice(exitMBB->begin(), BB,
886 llvm::next(MachineBasicBlock::iterator(MI)),
887 BB->end());
888 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
889
890 // thisMBB:
891 // ...
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000892 // fallthrough --> loopMBB
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000893 BB->addSuccessor(loopMBB);
Akira Hatanaka81b44112011-07-19 17:09:53 +0000894 loopMBB->addSuccessor(loopMBB);
895 loopMBB->addSuccessor(exitMBB);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000896
897 // loopMBB:
898 // ll oldval, 0(ptr)
Akira Hatanaka4061da12011-07-19 20:11:17 +0000899 // <binop> storeval, oldval, incr
900 // sc success, storeval, 0(ptr)
901 // beq success, $0, loopMBB
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000902 BB = loopMBB;
Akira Hatanaka4061da12011-07-19 20:11:17 +0000903 BuildMI(BB, dl, TII->get(Mips::LL), OldVal).addReg(Ptr).addImm(0);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000904 if (Nand) {
Akira Hatanaka4061da12011-07-19 20:11:17 +0000905 // and andres, oldval, incr
906 // nor storeval, $0, andres
907 BuildMI(BB, dl, TII->get(Mips::AND), AndRes).addReg(OldVal).addReg(Incr);
908 BuildMI(BB, dl, TII->get(Mips::NOR), StoreVal)
909 .addReg(Mips::ZERO).addReg(AndRes);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000910 } else if (BinOpcode) {
Akira Hatanaka4061da12011-07-19 20:11:17 +0000911 // <binop> storeval, oldval, incr
912 BuildMI(BB, dl, TII->get(BinOpcode), StoreVal).addReg(OldVal).addReg(Incr);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000913 } else {
Akira Hatanaka4061da12011-07-19 20:11:17 +0000914 StoreVal = Incr;
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000915 }
Akira Hatanaka4061da12011-07-19 20:11:17 +0000916 BuildMI(BB, dl, TII->get(Mips::SC), Success)
917 .addReg(StoreVal).addReg(Ptr).addImm(0);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000918 BuildMI(BB, dl, TII->get(Mips::BEQ))
Akira Hatanaka4061da12011-07-19 20:11:17 +0000919 .addReg(Success).addReg(Mips::ZERO).addMBB(loopMBB);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000920
921 MI->eraseFromParent(); // The instruction is gone now.
922
Akira Hatanaka939ece12011-07-19 03:42:13 +0000923 return exitMBB;
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000924}
925
926MachineBasicBlock *
927MipsTargetLowering::EmitAtomicBinaryPartword(MachineInstr *MI,
Akira Hatanaka0f843822011-06-07 18:58:42 +0000928 MachineBasicBlock *BB,
929 unsigned Size, unsigned BinOpcode,
930 bool Nand) const {
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000931 assert((Size == 1 || Size == 2) &&
932 "Unsupported size for EmitAtomicBinaryPartial.");
933
934 MachineFunction *MF = BB->getParent();
935 MachineRegisterInfo &RegInfo = MF->getRegInfo();
936 const TargetRegisterClass *RC = getRegClassFor(MVT::i32);
937 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
938 DebugLoc dl = MI->getDebugLoc();
939
940 unsigned Dest = MI->getOperand(0).getReg();
941 unsigned Ptr = MI->getOperand(1).getReg();
942 unsigned Incr = MI->getOperand(2).getReg();
943
Akira Hatanaka4061da12011-07-19 20:11:17 +0000944 unsigned AlignedAddr = RegInfo.createVirtualRegister(RC);
945 unsigned ShiftAmt = RegInfo.createVirtualRegister(RC);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000946 unsigned Mask = RegInfo.createVirtualRegister(RC);
947 unsigned Mask2 = RegInfo.createVirtualRegister(RC);
Akira Hatanaka4061da12011-07-19 20:11:17 +0000948 unsigned NewVal = RegInfo.createVirtualRegister(RC);
949 unsigned OldVal = RegInfo.createVirtualRegister(RC);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000950 unsigned Incr2 = RegInfo.createVirtualRegister(RC);
Akira Hatanaka4061da12011-07-19 20:11:17 +0000951 unsigned MaskLSB2 = RegInfo.createVirtualRegister(RC);
952 unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC);
953 unsigned MaskUpper = RegInfo.createVirtualRegister(RC);
954 unsigned AndRes = RegInfo.createVirtualRegister(RC);
955 unsigned BinOpRes = RegInfo.createVirtualRegister(RC);
Akira Hatanakabdd83fe2011-07-19 20:56:53 +0000956 unsigned MaskedOldVal0 = RegInfo.createVirtualRegister(RC);
Akira Hatanaka4061da12011-07-19 20:11:17 +0000957 unsigned StoreVal = RegInfo.createVirtualRegister(RC);
958 unsigned MaskedOldVal1 = RegInfo.createVirtualRegister(RC);
959 unsigned SrlRes = RegInfo.createVirtualRegister(RC);
960 unsigned SllRes = RegInfo.createVirtualRegister(RC);
961 unsigned Success = RegInfo.createVirtualRegister(RC);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000962
963 // insert new blocks after the current block
964 const BasicBlock *LLVM_BB = BB->getBasicBlock();
965 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
Akira Hatanaka939ece12011-07-19 03:42:13 +0000966 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(LLVM_BB);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000967 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
968 MachineFunction::iterator It = BB;
969 ++It;
970 MF->insert(It, loopMBB);
Akira Hatanaka939ece12011-07-19 03:42:13 +0000971 MF->insert(It, sinkMBB);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000972 MF->insert(It, exitMBB);
973
974 // Transfer the remainder of BB and its successor edges to exitMBB.
975 exitMBB->splice(exitMBB->begin(), BB,
976 llvm::next(MachineBasicBlock::iterator(MI)),
977 BB->end());
978 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
979
Akira Hatanaka81b44112011-07-19 17:09:53 +0000980 BB->addSuccessor(loopMBB);
981 loopMBB->addSuccessor(loopMBB);
982 loopMBB->addSuccessor(sinkMBB);
983 sinkMBB->addSuccessor(exitMBB);
984
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000985 // thisMBB:
Akira Hatanaka4061da12011-07-19 20:11:17 +0000986 // addiu masklsb2,$0,-4 # 0xfffffffc
987 // and alignedaddr,ptr,masklsb2
988 // andi ptrlsb2,ptr,3
989 // sll shiftamt,ptrlsb2,3
990 // ori maskupper,$0,255 # 0xff
991 // sll mask,maskupper,shiftamt
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000992 // nor mask2,$0,mask
Akira Hatanaka4061da12011-07-19 20:11:17 +0000993 // sll incr2,incr,shiftamt
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000994
995 int64_t MaskImm = (Size == 1) ? 255 : 65535;
Akira Hatanaka4061da12011-07-19 20:11:17 +0000996 BuildMI(BB, dl, TII->get(Mips::ADDiu), MaskLSB2)
997 .addReg(Mips::ZERO).addImm(-4);
998 BuildMI(BB, dl, TII->get(Mips::AND), AlignedAddr)
999 .addReg(Ptr).addReg(MaskLSB2);
1000 BuildMI(BB, dl, TII->get(Mips::ANDi), PtrLSB2).addReg(Ptr).addImm(3);
1001 BuildMI(BB, dl, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3);
1002 BuildMI(BB, dl, TII->get(Mips::ORi), MaskUpper)
1003 .addReg(Mips::ZERO).addImm(MaskImm);
Akira Hatanakacc7ecc72011-07-19 20:34:00 +00001004 BuildMI(BB, dl, TII->get(Mips::SLLV), Mask)
1005 .addReg(ShiftAmt).addReg(MaskUpper);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001006 BuildMI(BB, dl, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask);
Akira Hatanakacc7ecc72011-07-19 20:34:00 +00001007 BuildMI(BB, dl, TII->get(Mips::SLLV), Incr2).addReg(ShiftAmt).addReg(Incr);
Bruno Cardoso Lopescada2d02011-05-31 20:25:26 +00001008
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001009
Akira Hatanaka0d7d0b52011-07-18 18:52:12 +00001010 // atomic.load.binop
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001011 // loopMBB:
Akira Hatanaka4061da12011-07-19 20:11:17 +00001012 // ll oldval,0(alignedaddr)
1013 // binop binopres,oldval,incr2
1014 // and newval,binopres,mask
1015 // and maskedoldval0,oldval,mask2
1016 // or storeval,maskedoldval0,newval
1017 // sc success,storeval,0(alignedaddr)
1018 // beq success,$0,loopMBB
1019
Akira Hatanaka0d7d0b52011-07-18 18:52:12 +00001020 // atomic.swap
1021 // loopMBB:
Akira Hatanaka4061da12011-07-19 20:11:17 +00001022 // ll oldval,0(alignedaddr)
Akira Hatanaka70564a92011-07-19 18:14:26 +00001023 // and newval,incr2,mask
Akira Hatanaka4061da12011-07-19 20:11:17 +00001024 // and maskedoldval0,oldval,mask2
1025 // or storeval,maskedoldval0,newval
1026 // sc success,storeval,0(alignedaddr)
1027 // beq success,$0,loopMBB
Akira Hatanaka0d7d0b52011-07-18 18:52:12 +00001028
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001029 BB = loopMBB;
Akira Hatanaka4061da12011-07-19 20:11:17 +00001030 BuildMI(BB, dl, TII->get(Mips::LL), OldVal).addReg(AlignedAddr).addImm(0);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001031 if (Nand) {
Akira Hatanaka4061da12011-07-19 20:11:17 +00001032 // and andres, oldval, incr2
1033 // nor binopres, $0, andres
1034 // and newval, binopres, mask
1035 BuildMI(BB, dl, TII->get(Mips::AND), AndRes).addReg(OldVal).addReg(Incr2);
1036 BuildMI(BB, dl, TII->get(Mips::NOR), BinOpRes)
1037 .addReg(Mips::ZERO).addReg(AndRes);
1038 BuildMI(BB, dl, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001039 } else if (BinOpcode) {
Akira Hatanaka4061da12011-07-19 20:11:17 +00001040 // <binop> binopres, oldval, incr2
1041 // and newval, binopres, mask
1042 BuildMI(BB, dl, TII->get(BinOpcode), BinOpRes).addReg(OldVal).addReg(Incr2);
1043 BuildMI(BB, dl, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask);
Akira Hatanaka70564a92011-07-19 18:14:26 +00001044 } else {// atomic.swap
Akira Hatanaka4061da12011-07-19 20:11:17 +00001045 // and newval, incr2, mask
Akira Hatanakacc7ecc72011-07-19 20:34:00 +00001046 BuildMI(BB, dl, TII->get(Mips::AND), NewVal).addReg(Incr2).addReg(Mask);
Akira Hatanaka70564a92011-07-19 18:14:26 +00001047 }
1048
Akira Hatanakabdd83fe2011-07-19 20:56:53 +00001049 BuildMI(BB, dl, TII->get(Mips::AND), MaskedOldVal0)
Akira Hatanaka4061da12011-07-19 20:11:17 +00001050 .addReg(OldVal).addReg(Mask2);
1051 BuildMI(BB, dl, TII->get(Mips::OR), StoreVal)
Akira Hatanakabdd83fe2011-07-19 20:56:53 +00001052 .addReg(MaskedOldVal0).addReg(NewVal);
Akira Hatanaka4061da12011-07-19 20:11:17 +00001053 BuildMI(BB, dl, TII->get(Mips::SC), Success)
1054 .addReg(StoreVal).addReg(AlignedAddr).addImm(0);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001055 BuildMI(BB, dl, TII->get(Mips::BEQ))
Akira Hatanaka4061da12011-07-19 20:11:17 +00001056 .addReg(Success).addReg(Mips::ZERO).addMBB(loopMBB);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001057
Akira Hatanaka939ece12011-07-19 03:42:13 +00001058 // sinkMBB:
Akira Hatanaka4061da12011-07-19 20:11:17 +00001059 // and maskedoldval1,oldval,mask
1060 // srl srlres,maskedoldval1,shiftamt
1061 // sll sllres,srlres,24
1062 // sra dest,sllres,24
Akira Hatanaka939ece12011-07-19 03:42:13 +00001063 BB = sinkMBB;
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001064 int64_t ShiftImm = (Size == 1) ? 24 : 16;
Akira Hatanakaa308c672011-07-19 03:14:58 +00001065
Akira Hatanaka4061da12011-07-19 20:11:17 +00001066 BuildMI(BB, dl, TII->get(Mips::AND), MaskedOldVal1)
1067 .addReg(OldVal).addReg(Mask);
Akira Hatanakacc7ecc72011-07-19 20:34:00 +00001068 BuildMI(BB, dl, TII->get(Mips::SRLV), SrlRes)
1069 .addReg(ShiftAmt).addReg(MaskedOldVal1);
Akira Hatanaka4061da12011-07-19 20:11:17 +00001070 BuildMI(BB, dl, TII->get(Mips::SLL), SllRes)
1071 .addReg(SrlRes).addImm(ShiftImm);
Akira Hatanaka939ece12011-07-19 03:42:13 +00001072 BuildMI(BB, dl, TII->get(Mips::SRA), Dest)
Akira Hatanaka4061da12011-07-19 20:11:17 +00001073 .addReg(SllRes).addImm(ShiftImm);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001074
1075 MI->eraseFromParent(); // The instruction is gone now.
1076
Akira Hatanaka939ece12011-07-19 03:42:13 +00001077 return exitMBB;
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001078}
1079
1080MachineBasicBlock *
1081MipsTargetLowering::EmitAtomicCmpSwap(MachineInstr *MI,
Akira Hatanaka0f843822011-06-07 18:58:42 +00001082 MachineBasicBlock *BB,
1083 unsigned Size) const {
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001084 assert(Size == 4 && "Unsupported size for EmitAtomicCmpSwap.");
1085
1086 MachineFunction *MF = BB->getParent();
1087 MachineRegisterInfo &RegInfo = MF->getRegInfo();
1088 const TargetRegisterClass *RC = getRegClassFor(MVT::i32);
1089 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
1090 DebugLoc dl = MI->getDebugLoc();
1091
1092 unsigned Dest = MI->getOperand(0).getReg();
1093 unsigned Ptr = MI->getOperand(1).getReg();
Akira Hatanaka4061da12011-07-19 20:11:17 +00001094 unsigned OldVal = MI->getOperand(2).getReg();
1095 unsigned NewVal = MI->getOperand(3).getReg();
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001096
Akira Hatanaka4061da12011-07-19 20:11:17 +00001097 unsigned Success = RegInfo.createVirtualRegister(RC);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001098
1099 // insert new blocks after the current block
1100 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1101 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB);
1102 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB);
1103 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1104 MachineFunction::iterator It = BB;
1105 ++It;
1106 MF->insert(It, loop1MBB);
1107 MF->insert(It, loop2MBB);
1108 MF->insert(It, exitMBB);
1109
1110 // Transfer the remainder of BB and its successor edges to exitMBB.
1111 exitMBB->splice(exitMBB->begin(), BB,
1112 llvm::next(MachineBasicBlock::iterator(MI)),
1113 BB->end());
1114 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
1115
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001116 // thisMBB:
1117 // ...
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001118 // fallthrough --> loop1MBB
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001119 BB->addSuccessor(loop1MBB);
Akira Hatanaka81b44112011-07-19 17:09:53 +00001120 loop1MBB->addSuccessor(exitMBB);
1121 loop1MBB->addSuccessor(loop2MBB);
1122 loop2MBB->addSuccessor(loop1MBB);
1123 loop2MBB->addSuccessor(exitMBB);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001124
1125 // loop1MBB:
1126 // ll dest, 0(ptr)
1127 // bne dest, oldval, exitMBB
1128 BB = loop1MBB;
Akira Hatanakad3ac47f2011-07-07 18:57:00 +00001129 BuildMI(BB, dl, TII->get(Mips::LL), Dest).addReg(Ptr).addImm(0);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001130 BuildMI(BB, dl, TII->get(Mips::BNE))
Akira Hatanaka4061da12011-07-19 20:11:17 +00001131 .addReg(Dest).addReg(OldVal).addMBB(exitMBB);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001132
1133 // loop2MBB:
Akira Hatanaka4061da12011-07-19 20:11:17 +00001134 // sc success, newval, 0(ptr)
1135 // beq success, $0, loop1MBB
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001136 BB = loop2MBB;
Akira Hatanaka4061da12011-07-19 20:11:17 +00001137 BuildMI(BB, dl, TII->get(Mips::SC), Success)
1138 .addReg(NewVal).addReg(Ptr).addImm(0);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001139 BuildMI(BB, dl, TII->get(Mips::BEQ))
Akira Hatanaka4061da12011-07-19 20:11:17 +00001140 .addReg(Success).addReg(Mips::ZERO).addMBB(loop1MBB);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001141
1142 MI->eraseFromParent(); // The instruction is gone now.
1143
Akira Hatanaka939ece12011-07-19 03:42:13 +00001144 return exitMBB;
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001145}
1146
1147MachineBasicBlock *
1148MipsTargetLowering::EmitAtomicCmpSwapPartword(MachineInstr *MI,
Akira Hatanaka0f843822011-06-07 18:58:42 +00001149 MachineBasicBlock *BB,
1150 unsigned Size) const {
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001151 assert((Size == 1 || Size == 2) &&
1152 "Unsupported size for EmitAtomicCmpSwapPartial.");
1153
1154 MachineFunction *MF = BB->getParent();
1155 MachineRegisterInfo &RegInfo = MF->getRegInfo();
1156 const TargetRegisterClass *RC = getRegClassFor(MVT::i32);
1157 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
1158 DebugLoc dl = MI->getDebugLoc();
1159
1160 unsigned Dest = MI->getOperand(0).getReg();
1161 unsigned Ptr = MI->getOperand(1).getReg();
Akira Hatanaka4061da12011-07-19 20:11:17 +00001162 unsigned CmpVal = MI->getOperand(2).getReg();
1163 unsigned NewVal = MI->getOperand(3).getReg();
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001164
Akira Hatanaka4061da12011-07-19 20:11:17 +00001165 unsigned AlignedAddr = RegInfo.createVirtualRegister(RC);
1166 unsigned ShiftAmt = RegInfo.createVirtualRegister(RC);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001167 unsigned Mask = RegInfo.createVirtualRegister(RC);
1168 unsigned Mask2 = RegInfo.createVirtualRegister(RC);
Akira Hatanaka4061da12011-07-19 20:11:17 +00001169 unsigned ShiftedCmpVal = RegInfo.createVirtualRegister(RC);
1170 unsigned OldVal = RegInfo.createVirtualRegister(RC);
1171 unsigned MaskedOldVal0 = RegInfo.createVirtualRegister(RC);
1172 unsigned ShiftedNewVal = RegInfo.createVirtualRegister(RC);
1173 unsigned MaskLSB2 = RegInfo.createVirtualRegister(RC);
1174 unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC);
1175 unsigned MaskUpper = RegInfo.createVirtualRegister(RC);
1176 unsigned MaskedCmpVal = RegInfo.createVirtualRegister(RC);
1177 unsigned MaskedNewVal = RegInfo.createVirtualRegister(RC);
1178 unsigned MaskedOldVal1 = RegInfo.createVirtualRegister(RC);
1179 unsigned StoreVal = RegInfo.createVirtualRegister(RC);
1180 unsigned SrlRes = RegInfo.createVirtualRegister(RC);
1181 unsigned SllRes = RegInfo.createVirtualRegister(RC);
1182 unsigned Success = RegInfo.createVirtualRegister(RC);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001183
1184 // insert new blocks after the current block
1185 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1186 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB);
1187 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB);
Akira Hatanaka939ece12011-07-19 03:42:13 +00001188 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(LLVM_BB);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001189 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1190 MachineFunction::iterator It = BB;
1191 ++It;
1192 MF->insert(It, loop1MBB);
1193 MF->insert(It, loop2MBB);
Akira Hatanaka939ece12011-07-19 03:42:13 +00001194 MF->insert(It, sinkMBB);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001195 MF->insert(It, exitMBB);
1196
1197 // Transfer the remainder of BB and its successor edges to exitMBB.
1198 exitMBB->splice(exitMBB->begin(), BB,
1199 llvm::next(MachineBasicBlock::iterator(MI)),
1200 BB->end());
1201 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
1202
Akira Hatanaka81b44112011-07-19 17:09:53 +00001203 BB->addSuccessor(loop1MBB);
1204 loop1MBB->addSuccessor(sinkMBB);
1205 loop1MBB->addSuccessor(loop2MBB);
1206 loop2MBB->addSuccessor(loop1MBB);
1207 loop2MBB->addSuccessor(sinkMBB);
1208 sinkMBB->addSuccessor(exitMBB);
1209
Akira Hatanaka70564a92011-07-19 18:14:26 +00001210 // FIXME: computation of newval2 can be moved to loop2MBB.
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001211 // thisMBB:
Akira Hatanaka4061da12011-07-19 20:11:17 +00001212 // addiu masklsb2,$0,-4 # 0xfffffffc
1213 // and alignedaddr,ptr,masklsb2
1214 // andi ptrlsb2,ptr,3
1215 // sll shiftamt,ptrlsb2,3
1216 // ori maskupper,$0,255 # 0xff
1217 // sll mask,maskupper,shiftamt
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001218 // nor mask2,$0,mask
Akira Hatanaka4061da12011-07-19 20:11:17 +00001219 // andi maskedcmpval,cmpval,255
1220 // sll shiftedcmpval,maskedcmpval,shiftamt
1221 // andi maskednewval,newval,255
1222 // sll shiftednewval,maskednewval,shiftamt
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001223 int64_t MaskImm = (Size == 1) ? 255 : 65535;
Akira Hatanaka4061da12011-07-19 20:11:17 +00001224 BuildMI(BB, dl, TII->get(Mips::ADDiu), MaskLSB2)
1225 .addReg(Mips::ZERO).addImm(-4);
1226 BuildMI(BB, dl, TII->get(Mips::AND), AlignedAddr)
1227 .addReg(Ptr).addReg(MaskLSB2);
1228 BuildMI(BB, dl, TII->get(Mips::ANDi), PtrLSB2).addReg(Ptr).addImm(3);
1229 BuildMI(BB, dl, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3);
1230 BuildMI(BB, dl, TII->get(Mips::ORi), MaskUpper)
1231 .addReg(Mips::ZERO).addImm(MaskImm);
Akira Hatanakacc7ecc72011-07-19 20:34:00 +00001232 BuildMI(BB, dl, TII->get(Mips::SLLV), Mask)
1233 .addReg(ShiftAmt).addReg(MaskUpper);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001234 BuildMI(BB, dl, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask);
Akira Hatanaka4061da12011-07-19 20:11:17 +00001235 BuildMI(BB, dl, TII->get(Mips::ANDi), MaskedCmpVal)
1236 .addReg(CmpVal).addImm(MaskImm);
Akira Hatanakacc7ecc72011-07-19 20:34:00 +00001237 BuildMI(BB, dl, TII->get(Mips::SLLV), ShiftedCmpVal)
1238 .addReg(ShiftAmt).addReg(MaskedCmpVal);
Akira Hatanaka4061da12011-07-19 20:11:17 +00001239 BuildMI(BB, dl, TII->get(Mips::ANDi), MaskedNewVal)
1240 .addReg(NewVal).addImm(MaskImm);
Akira Hatanakacc7ecc72011-07-19 20:34:00 +00001241 BuildMI(BB, dl, TII->get(Mips::SLLV), ShiftedNewVal)
1242 .addReg(ShiftAmt).addReg(MaskedNewVal);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001243
1244 // loop1MBB:
Akira Hatanaka4061da12011-07-19 20:11:17 +00001245 // ll oldval,0(alginedaddr)
1246 // and maskedoldval0,oldval,mask
1247 // bne maskedoldval0,shiftedcmpval,sinkMBB
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001248 BB = loop1MBB;
Akira Hatanaka4061da12011-07-19 20:11:17 +00001249 BuildMI(BB, dl, TII->get(Mips::LL), OldVal).addReg(AlignedAddr).addImm(0);
1250 BuildMI(BB, dl, TII->get(Mips::AND), MaskedOldVal0)
1251 .addReg(OldVal).addReg(Mask);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001252 BuildMI(BB, dl, TII->get(Mips::BNE))
Akira Hatanaka4061da12011-07-19 20:11:17 +00001253 .addReg(MaskedOldVal0).addReg(ShiftedCmpVal).addMBB(sinkMBB);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001254
1255 // loop2MBB:
Akira Hatanaka4061da12011-07-19 20:11:17 +00001256 // and maskedoldval1,oldval,mask2
1257 // or storeval,maskedoldval1,shiftednewval
1258 // sc success,storeval,0(alignedaddr)
1259 // beq success,$0,loop1MBB
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001260 BB = loop2MBB;
Akira Hatanaka4061da12011-07-19 20:11:17 +00001261 BuildMI(BB, dl, TII->get(Mips::AND), MaskedOldVal1)
1262 .addReg(OldVal).addReg(Mask2);
1263 BuildMI(BB, dl, TII->get(Mips::OR), StoreVal)
1264 .addReg(MaskedOldVal1).addReg(ShiftedNewVal);
1265 BuildMI(BB, dl, TII->get(Mips::SC), Success)
1266 .addReg(StoreVal).addReg(AlignedAddr).addImm(0);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001267 BuildMI(BB, dl, TII->get(Mips::BEQ))
Akira Hatanaka4061da12011-07-19 20:11:17 +00001268 .addReg(Success).addReg(Mips::ZERO).addMBB(loop1MBB);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001269
Akira Hatanaka939ece12011-07-19 03:42:13 +00001270 // sinkMBB:
Akira Hatanaka4061da12011-07-19 20:11:17 +00001271 // srl srlres,maskedoldval0,shiftamt
1272 // sll sllres,srlres,24
1273 // sra dest,sllres,24
Akira Hatanaka939ece12011-07-19 03:42:13 +00001274 BB = sinkMBB;
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001275 int64_t ShiftImm = (Size == 1) ? 24 : 16;
Akira Hatanakaa308c672011-07-19 03:14:58 +00001276
Akira Hatanakacc7ecc72011-07-19 20:34:00 +00001277 BuildMI(BB, dl, TII->get(Mips::SRLV), SrlRes)
1278 .addReg(ShiftAmt).addReg(MaskedOldVal0);
Akira Hatanaka4061da12011-07-19 20:11:17 +00001279 BuildMI(BB, dl, TII->get(Mips::SLL), SllRes)
1280 .addReg(SrlRes).addImm(ShiftImm);
Akira Hatanaka939ece12011-07-19 03:42:13 +00001281 BuildMI(BB, dl, TII->get(Mips::SRA), Dest)
Akira Hatanaka4061da12011-07-19 20:11:17 +00001282 .addReg(SllRes).addImm(ShiftImm);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001283
1284 MI->eraseFromParent(); // The instruction is gone now.
1285
Akira Hatanaka939ece12011-07-19 03:42:13 +00001286 return exitMBB;
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001287}
1288
Akira Hatanaka4552c9a2011-04-15 21:51:11 +00001289//===----------------------------------------------------------------------===//
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00001290// Misc Lower Operation implementation
Akira Hatanaka4552c9a2011-04-15 21:51:11 +00001291//===----------------------------------------------------------------------===//
Bruno Cardoso Lopesd3bdf192009-05-27 17:23:44 +00001292SDValue MipsTargetLowering::
Dan Gohmand858e902010-04-17 15:26:15 +00001293LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const
Bruno Cardoso Lopes7da151c2008-08-07 19:08:11 +00001294{
Akira Hatanaka21afc632011-06-21 00:40:49 +00001295 MachineFunction &MF = DAG.getMachineFunction();
1296 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
1297
1298 assert(getTargetMachine().getFrameLowering()->getStackAlignment() >=
Akira Hatanaka053546c2011-05-25 02:20:00 +00001299 cast<ConstantSDNode>(Op.getOperand(2).getNode())->getZExtValue() &&
1300 "Cannot lower if the alignment of the allocated space is larger than \
1301 that of the stack.");
1302
Bruno Cardoso Lopes7da151c2008-08-07 19:08:11 +00001303 SDValue Chain = Op.getOperand(0);
1304 SDValue Size = Op.getOperand(1);
Dale Johannesena05dca42009-02-04 23:02:30 +00001305 DebugLoc dl = Op.getDebugLoc();
Bruno Cardoso Lopes7da151c2008-08-07 19:08:11 +00001306
1307 // Get a reference from Mips stack pointer
Owen Anderson825b72b2009-08-11 20:47:22 +00001308 SDValue StackPointer = DAG.getCopyFromReg(Chain, dl, Mips::SP, MVT::i32);
Bruno Cardoso Lopes7da151c2008-08-07 19:08:11 +00001309
1310 // Subtract the dynamic size from the actual stack size to
1311 // obtain the new stack size.
Owen Anderson825b72b2009-08-11 20:47:22 +00001312 SDValue Sub = DAG.getNode(ISD::SUB, dl, MVT::i32, StackPointer, Size);
Bruno Cardoso Lopes7da151c2008-08-07 19:08:11 +00001313
Wesley Peckbf17cfa2010-11-23 03:31:01 +00001314 // The Sub result contains the new stack start address, so it
Bruno Cardoso Lopes7da151c2008-08-07 19:08:11 +00001315 // must be placed in the stack pointer register.
Akira Hatanaka053546c2011-05-25 02:20:00 +00001316 Chain = DAG.getCopyToReg(StackPointer.getValue(1), dl, Mips::SP, Sub,
1317 SDValue());
Wesley Peckbf17cfa2010-11-23 03:31:01 +00001318
1319 // This node always has two return values: a new stack pointer
Bruno Cardoso Lopes7da151c2008-08-07 19:08:11 +00001320 // value and a chain
Akira Hatanaka21afc632011-06-21 00:40:49 +00001321 SDVTList VTLs = DAG.getVTList(MVT::i32, MVT::Other);
1322 SDValue Ptr = DAG.getFrameIndex(MipsFI->getDynAllocFI(), getPointerTy());
1323 SDValue Ops[] = { Chain, Ptr, Chain.getValue(1) };
1324
1325 return DAG.getNode(MipsISD::DynAlloc, dl, VTLs, Ops, 3);
Bruno Cardoso Lopes7da151c2008-08-07 19:08:11 +00001326}
1327
1328SDValue MipsTargetLowering::
Dan Gohmand858e902010-04-17 15:26:15 +00001329LowerBRCOND(SDValue Op, SelectionDAG &DAG) const
Bruno Cardoso Lopes85e31e32008-07-28 19:11:24 +00001330{
Wesley Peckbf17cfa2010-11-23 03:31:01 +00001331 // The first operand is the chain, the second is the condition, the third is
Bruno Cardoso Lopes85e31e32008-07-28 19:11:24 +00001332 // the block to branch to if the condition is true.
1333 SDValue Chain = Op.getOperand(0);
1334 SDValue Dest = Op.getOperand(2);
Dale Johannesende064702009-02-06 21:50:26 +00001335 DebugLoc dl = Op.getDebugLoc();
Bruno Cardoso Lopes85e31e32008-07-28 19:11:24 +00001336
Akira Hatanaka1d6b38d2011-03-31 18:26:17 +00001337 SDValue CondRes = CreateFPCmp(DAG, Op.getOperand(1));
1338
Chris Lattner7a2bdde2011-04-15 05:18:47 +00001339 // Return if flag is not set by a floating point comparison.
Akira Hatanaka1d6b38d2011-03-31 18:26:17 +00001340 if (CondRes.getOpcode() != MipsISD::FPCmp)
Bruno Cardoso Lopes4b877ca2008-07-30 17:06:13 +00001341 return Op;
Wesley Peckbf17cfa2010-11-23 03:31:01 +00001342
Bruno Cardoso Lopes77283772008-07-31 18:31:28 +00001343 SDValue CCNode = CondRes.getOperand(2);
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +00001344 Mips::CondCode CC =
1345 (Mips::CondCode)cast<ConstantSDNode>(CCNode)->getZExtValue();
Wesley Peckbf17cfa2010-11-23 03:31:01 +00001346 SDValue BrCode = DAG.getConstant(GetFPBranchCodeFromCond(CC), MVT::i32);
Bruno Cardoso Lopes85e31e32008-07-28 19:11:24 +00001347
Wesley Peckbf17cfa2010-11-23 03:31:01 +00001348 return DAG.getNode(MipsISD::FPBrcond, dl, Op.getValueType(), Chain, BrCode,
Akira Hatanaka1d6b38d2011-03-31 18:26:17 +00001349 Dest, CondRes);
Bruno Cardoso Lopes85e31e32008-07-28 19:11:24 +00001350}
1351
1352SDValue MipsTargetLowering::
Dan Gohmand858e902010-04-17 15:26:15 +00001353LowerSELECT(SDValue Op, SelectionDAG &DAG) const
Bruno Cardoso Lopes6d399bd2008-07-29 19:05:28 +00001354{
Akira Hatanaka1d6b38d2011-03-31 18:26:17 +00001355 SDValue Cond = CreateFPCmp(DAG, Op.getOperand(0));
Bruno Cardoso Lopes6d399bd2008-07-29 19:05:28 +00001356
Chris Lattner7a2bdde2011-04-15 05:18:47 +00001357 // Return if flag is not set by a floating point comparison.
Akira Hatanaka1d6b38d2011-03-31 18:26:17 +00001358 if (Cond.getOpcode() != MipsISD::FPCmp)
1359 return Op;
Bruno Cardoso Lopes739e4412008-08-13 07:13:40 +00001360
Akira Hatanaka1d6b38d2011-03-31 18:26:17 +00001361 return CreateCMovFP(DAG, Cond, Op.getOperand(1), Op.getOperand(2),
1362 Op.getDebugLoc());
Bruno Cardoso Lopes6d399bd2008-07-29 19:05:28 +00001363}
1364
Dan Gohmand858e902010-04-17 15:26:15 +00001365SDValue MipsTargetLowering::LowerGlobalAddress(SDValue Op,
1366 SelectionDAG &DAG) const {
Dale Johannesende064702009-02-06 21:50:26 +00001367 // FIXME there isn't actually debug info here
Dale Johannesen33c960f2009-02-04 20:06:27 +00001368 DebugLoc dl = Op.getDebugLoc();
Dan Gohman46510a72010-04-15 01:51:59 +00001369 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
Bruno Cardoso Lopes97843cd2008-07-29 19:29:50 +00001370
Eli Friedmane2c74082009-08-03 02:22:28 +00001371 if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
Chris Lattnere3736f82009-08-13 05:41:27 +00001372 SDVTList VTs = DAG.getVTList(MVT::i32);
Wesley Peckbf17cfa2010-11-23 03:31:01 +00001373
Chris Lattnerb71b9092009-08-13 06:28:06 +00001374 MipsTargetObjectFile &TLOF = (MipsTargetObjectFile&)getObjFileLowering();
Wesley Peckbf17cfa2010-11-23 03:31:01 +00001375
Chris Lattnere3736f82009-08-13 05:41:27 +00001376 // %gp_rel relocation
Wesley Peckbf17cfa2010-11-23 03:31:01 +00001377 if (TLOF.IsGlobalInSmallSection(GV, getTargetMachine())) {
1378 SDValue GA = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0,
Bruno Cardoso Lopesc517cb02009-09-01 17:27:58 +00001379 MipsII::MO_GPREL);
Chris Lattnere3736f82009-08-13 05:41:27 +00001380 SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, dl, VTs, &GA, 1);
1381 SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(MVT::i32);
Wesley Peckbf17cfa2010-11-23 03:31:01 +00001382 return DAG.getNode(ISD::ADD, dl, MVT::i32, GOT, GPRelNode);
Chris Lattnere3736f82009-08-13 05:41:27 +00001383 }
Bruno Cardoso Lopes97843cd2008-07-29 19:29:50 +00001384 // %hi/%lo relocation
Akira Hatanakae2e436a2011-04-01 21:41:06 +00001385 SDValue GAHi = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0,
1386 MipsII::MO_ABS_HI);
1387 SDValue GALo = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0,
1388 MipsII::MO_ABS_LO);
1389 SDValue HiPart = DAG.getNode(MipsISD::Hi, dl, VTs, &GAHi, 1);
1390 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, GALo);
Owen Anderson825b72b2009-08-11 20:47:22 +00001391 return DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo);
Bruno Cardoso Lopes97843cd2008-07-29 19:29:50 +00001392 }
1393
Akira Hatanaka0f843822011-06-07 18:58:42 +00001394 SDValue GA = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0,
1395 MipsII::MO_GOT);
1396 GA = DAG.getNode(MipsISD::WrapperPIC, dl, MVT::i32, GA);
1397 SDValue ResNode = DAG.getLoad(MVT::i32, dl,
1398 DAG.getEntryNode(), GA, MachinePointerInfo(),
1399 false, false, 0);
1400 // On functions and global targets not internal linked only
1401 // a load from got/GP is necessary for PIC to work.
1402 if (!GV->hasInternalLinkage() &&
1403 (!GV->hasLocalLinkage() || isa<Function>(GV)))
1404 return ResNode;
1405 SDValue GALo = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0,
1406 MipsII::MO_ABS_LO);
1407 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, GALo);
1408 return DAG.getNode(ISD::ADD, dl, MVT::i32, ResNode, Lo);
Bruno Cardoso Lopes97843cd2008-07-29 19:29:50 +00001409}
1410
Bruno Cardoso Lopesca8a2aa2011-03-04 20:01:52 +00001411SDValue MipsTargetLowering::LowerBlockAddress(SDValue Op,
1412 SelectionDAG &DAG) const {
Akira Hatanakaf48eb532011-04-25 17:10:45 +00001413 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
1414 // FIXME there isn't actually debug info here
1415 DebugLoc dl = Op.getDebugLoc();
1416
Bruno Cardoso Lopesca8a2aa2011-03-04 20:01:52 +00001417 if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
Akira Hatanakaf48eb532011-04-25 17:10:45 +00001418 // %hi/%lo relocation
1419 SDValue BAHi = DAG.getBlockAddress(BA, MVT::i32, true,
1420 MipsII::MO_ABS_HI);
1421 SDValue BALo = DAG.getBlockAddress(BA, MVT::i32, true,
1422 MipsII::MO_ABS_LO);
1423 SDValue Hi = DAG.getNode(MipsISD::Hi, dl, MVT::i32, BAHi);
1424 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, BALo);
1425 return DAG.getNode(ISD::ADD, dl, MVT::i32, Hi, Lo);
Bruno Cardoso Lopesca8a2aa2011-03-04 20:01:52 +00001426 }
Akira Hatanakaf48eb532011-04-25 17:10:45 +00001427
1428 SDValue BAGOTOffset = DAG.getBlockAddress(BA, MVT::i32, true,
1429 MipsII::MO_GOT);
Akira Hatanaka342837d2011-05-28 01:07:07 +00001430 BAGOTOffset = DAG.getNode(MipsISD::WrapperPIC, dl, MVT::i32, BAGOTOffset);
Akira Hatanakaf48eb532011-04-25 17:10:45 +00001431 SDValue BALOOffset = DAG.getBlockAddress(BA, MVT::i32, true,
1432 MipsII::MO_ABS_LO);
1433 SDValue Load = DAG.getLoad(MVT::i32, dl,
1434 DAG.getEntryNode(), BAGOTOffset,
1435 MachinePointerInfo(), false, false, 0);
1436 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, BALOOffset);
1437 return DAG.getNode(ISD::ADD, dl, MVT::i32, Load, Lo);
Bruno Cardoso Lopesca8a2aa2011-03-04 20:01:52 +00001438}
1439
Bruno Cardoso Lopes97843cd2008-07-29 19:29:50 +00001440SDValue MipsTargetLowering::
Dan Gohmand858e902010-04-17 15:26:15 +00001441LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const
Bruno Cardoso Lopes97843cd2008-07-29 19:29:50 +00001442{
Bruno Cardoso Lopesd9796862011-05-31 02:53:58 +00001443 // If the relocation model is PIC, use the General Dynamic TLS Model,
1444 // otherwise use the Initial Exec or Local Exec TLS Model.
1445 // TODO: implement Local Dynamic TLS model
1446
1447 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
1448 DebugLoc dl = GA->getDebugLoc();
1449 const GlobalValue *GV = GA->getGlobal();
1450 EVT PtrVT = getPointerTy();
1451
1452 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) {
1453 // General Dynamic TLS Model
1454 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, MVT::i32,
Akira Hatanaka5f7451f2011-06-21 01:02:03 +00001455 0, MipsII::MO_TLSGD);
Bruno Cardoso Lopesd9796862011-05-31 02:53:58 +00001456 SDValue Tlsgd = DAG.getNode(MipsISD::TlsGd, dl, MVT::i32, TGA);
1457 SDValue GP = DAG.getRegister(Mips::GP, MVT::i32);
1458 SDValue Argument = DAG.getNode(ISD::ADD, dl, MVT::i32, GP, Tlsgd);
1459
1460 ArgListTy Args;
1461 ArgListEntry Entry;
1462 Entry.Node = Argument;
Chris Lattnerdb125cf2011-07-18 04:54:35 +00001463 Entry.Ty = (Type *) Type::getInt32Ty(*DAG.getContext());
Bruno Cardoso Lopesd9796862011-05-31 02:53:58 +00001464 Args.push_back(Entry);
1465 std::pair<SDValue, SDValue> CallResult =
1466 LowerCallTo(DAG.getEntryNode(),
Chris Lattnerdb125cf2011-07-18 04:54:35 +00001467 (Type *) Type::getInt32Ty(*DAG.getContext()),
Akira Hatanaka5f7451f2011-06-21 01:02:03 +00001468 false, false, false, false, 0, CallingConv::C, false, true,
1469 DAG.getExternalSymbol("__tls_get_addr", PtrVT), Args, DAG,
1470 dl);
Bruno Cardoso Lopesd9796862011-05-31 02:53:58 +00001471
1472 return CallResult.first;
Bruno Cardoso Lopesd9796862011-05-31 02:53:58 +00001473 }
Akira Hatanaka5f7451f2011-06-21 01:02:03 +00001474
1475 SDValue Offset;
1476 if (GV->isDeclaration()) {
1477 // Initial Exec TLS Model
1478 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0,
1479 MipsII::MO_GOTTPREL);
1480 Offset = DAG.getLoad(MVT::i32, dl,
1481 DAG.getEntryNode(), TGA, MachinePointerInfo(),
1482 false, false, 0);
1483 } else {
1484 // Local Exec TLS Model
1485 SDVTList VTs = DAG.getVTList(MVT::i32);
1486 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0,
1487 MipsII::MO_TPREL_HI);
1488 SDValue TGALo = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0,
1489 MipsII::MO_TPREL_LO);
1490 SDValue Hi = DAG.getNode(MipsISD::TprelHi, dl, VTs, &TGAHi, 1);
1491 SDValue Lo = DAG.getNode(MipsISD::TprelLo, dl, MVT::i32, TGALo);
1492 Offset = DAG.getNode(ISD::ADD, dl, MVT::i32, Hi, Lo);
1493 }
1494
1495 SDValue ThreadPointer = DAG.getNode(MipsISD::ThreadPointer, dl, PtrVT);
1496 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
Bruno Cardoso Lopes97843cd2008-07-29 19:29:50 +00001497}
1498
1499SDValue MipsTargetLowering::
Dan Gohmand858e902010-04-17 15:26:15 +00001500LowerJumpTable(SDValue Op, SelectionDAG &DAG) const
Bruno Cardoso Lopes753a9872007-11-12 19:49:57 +00001501{
Dan Gohman475871a2008-07-27 21:46:04 +00001502 SDValue ResNode;
Wesley Peckbf17cfa2010-11-23 03:31:01 +00001503 SDValue HiPart;
Dale Johannesende064702009-02-06 21:50:26 +00001504 // FIXME there isn't actually debug info here
Dale Johannesen33c960f2009-02-04 20:06:27 +00001505 DebugLoc dl = Op.getDebugLoc();
Bruno Cardoso Lopesc517cb02009-09-01 17:27:58 +00001506 bool IsPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_;
Akira Hatanakae2e436a2011-04-01 21:41:06 +00001507 unsigned char OpFlag = IsPIC ? MipsII::MO_GOT : MipsII::MO_ABS_HI;
Bruno Cardoso Lopes753a9872007-11-12 19:49:57 +00001508
Owen Andersone50ed302009-08-10 22:56:29 +00001509 EVT PtrVT = Op.getValueType();
Bruno Cardoso Lopes753a9872007-11-12 19:49:57 +00001510 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
Bruno Cardoso Lopes753a9872007-11-12 19:49:57 +00001511
Bruno Cardoso Lopesc517cb02009-09-01 17:27:58 +00001512 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, OpFlag);
1513
Bruno Cardoso Lopes46773792010-07-20 08:37:04 +00001514 if (!IsPIC) {
Dan Gohman475871a2008-07-27 21:46:04 +00001515 SDValue Ops[] = { JTI };
Bruno Cardoso Lopesc517cb02009-09-01 17:27:58 +00001516 HiPart = DAG.getNode(MipsISD::Hi, dl, DAG.getVTList(MVT::i32), Ops, 1);
Akira Hatanaka342837d2011-05-28 01:07:07 +00001517 } else {// Emit Load from Global Pointer
1518 JTI = DAG.getNode(MipsISD::WrapperPIC, dl, MVT::i32, JTI);
Chris Lattnerd1c24ed2010-09-21 06:44:06 +00001519 HiPart = DAG.getLoad(MVT::i32, dl, DAG.getEntryNode(), JTI,
1520 MachinePointerInfo(),
David Greenef6fa1862010-02-15 16:56:10 +00001521 false, false, 0);
Akira Hatanaka342837d2011-05-28 01:07:07 +00001522 }
Bruno Cardoso Lopes753a9872007-11-12 19:49:57 +00001523
Akira Hatanaka0bf3dfb2011-04-15 21:00:26 +00001524 SDValue JTILo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT,
1525 MipsII::MO_ABS_LO);
Akira Hatanakae2e436a2011-04-01 21:41:06 +00001526 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, JTILo);
Owen Anderson825b72b2009-08-11 20:47:22 +00001527 ResNode = DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo);
Bruno Cardoso Lopes753a9872007-11-12 19:49:57 +00001528
1529 return ResNode;
1530}
1531
Dan Gohman475871a2008-07-27 21:46:04 +00001532SDValue MipsTargetLowering::
Dan Gohmand858e902010-04-17 15:26:15 +00001533LowerConstantPool(SDValue Op, SelectionDAG &DAG) const
Bruno Cardoso Lopes97c25372008-07-09 04:15:08 +00001534{
Dan Gohman475871a2008-07-27 21:46:04 +00001535 SDValue ResNode;
Bruno Cardoso Lopes92e87f22008-07-23 16:01:50 +00001536 ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op);
Dan Gohman46510a72010-04-15 01:51:59 +00001537 const Constant *C = N->getConstVal();
Dale Johannesende064702009-02-06 21:50:26 +00001538 // FIXME there isn't actually debug info here
1539 DebugLoc dl = Op.getDebugLoc();
Bruno Cardoso Lopes92e87f22008-07-23 16:01:50 +00001540
1541 // gp_rel relocation
Wesley Peckbf17cfa2010-11-23 03:31:01 +00001542 // FIXME: we should reference the constant pool using small data sections,
Chris Lattner7a2bdde2011-04-15 05:18:47 +00001543 // but the asm printer currently doesn't support this feature without
Wesley Peckbf17cfa2010-11-23 03:31:01 +00001544 // hacking it. This feature should come soon so we can uncomment the
Bruno Cardoso Lopesf33bc432008-07-28 19:26:25 +00001545 // stuff below.
Eli Friedmane2c74082009-08-03 02:22:28 +00001546 //if (IsInSmallSection(C->getType())) {
Owen Anderson825b72b2009-08-11 20:47:22 +00001547 // SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, MVT::i32, CP);
1548 // SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(MVT::i32);
Wesley Peckbf17cfa2010-11-23 03:31:01 +00001549 // ResNode = DAG.getNode(ISD::ADD, MVT::i32, GOT, GPRelNode);
Bruno Cardoso Lopesd71cebf2009-11-25 12:17:58 +00001550
1551 if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
Akira Hatanakae2e436a2011-04-01 21:41:06 +00001552 SDValue CPHi = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment(),
Akira Hatanaka4552c9a2011-04-15 21:51:11 +00001553 N->getOffset(), MipsII::MO_ABS_HI);
Akira Hatanakae2e436a2011-04-01 21:41:06 +00001554 SDValue CPLo = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment(),
Akira Hatanaka4552c9a2011-04-15 21:51:11 +00001555 N->getOffset(), MipsII::MO_ABS_LO);
Akira Hatanakae2e436a2011-04-01 21:41:06 +00001556 SDValue HiPart = DAG.getNode(MipsISD::Hi, dl, MVT::i32, CPHi);
1557 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, CPLo);
Owen Anderson825b72b2009-08-11 20:47:22 +00001558 ResNode = DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo);
Bruno Cardoso Lopesd71cebf2009-11-25 12:17:58 +00001559 } else {
Wesley Peckbf17cfa2010-11-23 03:31:01 +00001560 SDValue CP = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment(),
Akira Hatanakae2e436a2011-04-01 21:41:06 +00001561 N->getOffset(), MipsII::MO_GOT);
Akira Hatanaka342837d2011-05-28 01:07:07 +00001562 CP = DAG.getNode(MipsISD::WrapperPIC, dl, MVT::i32, CP);
Wesley Peckbf17cfa2010-11-23 03:31:01 +00001563 SDValue Load = DAG.getLoad(MVT::i32, dl, DAG.getEntryNode(),
Chris Lattnerd1c24ed2010-09-21 06:44:06 +00001564 CP, MachinePointerInfo::getConstantPool(),
1565 false, false, 0);
Akira Hatanakae2e436a2011-04-01 21:41:06 +00001566 SDValue CPLo = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment(),
Akira Hatanaka4552c9a2011-04-15 21:51:11 +00001567 N->getOffset(), MipsII::MO_ABS_LO);
Akira Hatanakae2e436a2011-04-01 21:41:06 +00001568 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, CPLo);
Bruno Cardoso Lopesd71cebf2009-11-25 12:17:58 +00001569 ResNode = DAG.getNode(ISD::ADD, dl, MVT::i32, Load, Lo);
1570 }
Bruno Cardoso Lopes92e87f22008-07-23 16:01:50 +00001571
1572 return ResNode;
Bruno Cardoso Lopes97c25372008-07-09 04:15:08 +00001573}
1574
Dan Gohmand858e902010-04-17 15:26:15 +00001575SDValue MipsTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
Dan Gohman1e93df62010-04-17 14:41:14 +00001576 MachineFunction &MF = DAG.getMachineFunction();
1577 MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>();
1578
Bruno Cardoso Lopes6059b852010-02-06 21:00:02 +00001579 DebugLoc dl = Op.getDebugLoc();
Dan Gohman1e93df62010-04-17 14:41:14 +00001580 SDValue FI = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
1581 getPointerTy());
Bruno Cardoso Lopes6059b852010-02-06 21:00:02 +00001582
1583 // vastart just stores the address of the VarArgsFrameIndex slot into the
1584 // memory location argument.
1585 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
Chris Lattner8026a9d2010-09-21 17:50:43 +00001586 return DAG.getStore(Op.getOperand(0), dl, FI, Op.getOperand(1),
1587 MachinePointerInfo(SV),
David Greenef6fa1862010-02-15 16:56:10 +00001588 false, false, 0);
Bruno Cardoso Lopes6059b852010-02-06 21:00:02 +00001589}
1590
Akira Hatanaka9c3d57c2011-05-25 19:32:07 +00001591static SDValue LowerFCOPYSIGN32(SDValue Op, SelectionDAG &DAG) {
1592 // FIXME: Use ext/ins instructions if target architecture is Mips32r2.
1593 DebugLoc dl = Op.getDebugLoc();
1594 SDValue Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op.getOperand(0));
1595 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op.getOperand(1));
1596 SDValue And0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op0,
1597 DAG.getConstant(0x7fffffff, MVT::i32));
1598 SDValue And1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op1,
1599 DAG.getConstant(0x80000000, MVT::i32));
1600 SDValue Result = DAG.getNode(ISD::OR, dl, MVT::i32, And0, And1);
1601 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Result);
1602}
1603
1604static SDValue LowerFCOPYSIGN64(SDValue Op, SelectionDAG &DAG, bool isLittle) {
Eric Christopher471e4222011-06-08 23:55:35 +00001605 // FIXME:
Akira Hatanaka9c3d57c2011-05-25 19:32:07 +00001606 // Use ext/ins instructions if target architecture is Mips32r2.
1607 // Eliminate redundant mfc1 and mtc1 instructions.
1608 unsigned LoIdx = 0, HiIdx = 1;
Eric Christopher471e4222011-06-08 23:55:35 +00001609
Akira Hatanaka9c3d57c2011-05-25 19:32:07 +00001610 if (!isLittle)
1611 std::swap(LoIdx, HiIdx);
1612
1613 DebugLoc dl = Op.getDebugLoc();
1614 SDValue Word0 = DAG.getNode(MipsISD::ExtractElementF64, dl, MVT::i32,
1615 Op.getOperand(0),
1616 DAG.getConstant(LoIdx, MVT::i32));
1617 SDValue Hi0 = DAG.getNode(MipsISD::ExtractElementF64, dl, MVT::i32,
1618 Op.getOperand(0), DAG.getConstant(HiIdx, MVT::i32));
1619 SDValue Hi1 = DAG.getNode(MipsISD::ExtractElementF64, dl, MVT::i32,
1620 Op.getOperand(1), DAG.getConstant(HiIdx, MVT::i32));
1621 SDValue And0 = DAG.getNode(ISD::AND, dl, MVT::i32, Hi0,
1622 DAG.getConstant(0x7fffffff, MVT::i32));
1623 SDValue And1 = DAG.getNode(ISD::AND, dl, MVT::i32, Hi1,
1624 DAG.getConstant(0x80000000, MVT::i32));
1625 SDValue Word1 = DAG.getNode(ISD::OR, dl, MVT::i32, And0, And1);
1626
1627 if (!isLittle)
1628 std::swap(Word0, Word1);
1629
1630 return DAG.getNode(MipsISD::BuildPairF64, dl, MVT::f64, Word0, Word1);
1631}
1632
1633SDValue MipsTargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG)
1634 const {
1635 EVT Ty = Op.getValueType();
1636
1637 assert(Ty == MVT::f32 || Ty == MVT::f64);
1638
1639 if (Ty == MVT::f32)
1640 return LowerFCOPYSIGN32(Op, DAG);
1641 else
1642 return LowerFCOPYSIGN64(Op, DAG, Subtarget->isLittle());
1643}
1644
Akira Hatanaka2e591472011-06-02 00:24:44 +00001645SDValue MipsTargetLowering::
1646LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
Bruno Cardoso Lopese0b5cfc2011-06-16 00:40:02 +00001647 // check the depth
1648 assert((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) &&
Akira Hatanaka0f843822011-06-07 18:58:42 +00001649 "Frame address can only be determined for current frame.");
Akira Hatanaka2e591472011-06-02 00:24:44 +00001650
1651 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
1652 MFI->setFrameAddressIsTaken(true);
1653 EVT VT = Op.getValueType();
1654 DebugLoc dl = Op.getDebugLoc();
1655 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, Mips::FP, VT);
1656 return FrameAddr;
1657}
1658
Akira Hatanakadb548262011-07-19 23:30:50 +00001659// TODO: set SType according to the desired memory barrier behavior.
1660SDValue MipsTargetLowering::LowerMEMBARRIER(SDValue Op,
1661 SelectionDAG& DAG) const {
1662 unsigned SType = 0;
1663 DebugLoc dl = Op.getDebugLoc();
1664 return DAG.getNode(MipsISD::Sync, dl, MVT::Other, Op.getOperand(0),
1665 DAG.getConstant(SType, MVT::i32));
1666}
1667
Eli Friedman14648462011-07-27 22:21:52 +00001668SDValue MipsTargetLowering::LowerATOMIC_FENCE(SDValue Op,
1669 SelectionDAG& DAG) const {
1670 // FIXME: Need pseudo-fence for 'singlethread' fences
1671 // FIXME: Set SType for weaker fences where supported/appropriate.
1672 unsigned SType = 0;
1673 DebugLoc dl = Op.getDebugLoc();
1674 return DAG.getNode(MipsISD::Sync, dl, MVT::Other, Op.getOperand(0),
1675 DAG.getConstant(SType, MVT::i32));
1676}
1677
Akira Hatanaka4552c9a2011-04-15 21:51:11 +00001678//===----------------------------------------------------------------------===//
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00001679// Calling Convention Implementation
Akira Hatanaka4552c9a2011-04-15 21:51:11 +00001680//===----------------------------------------------------------------------===//
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00001681
1682#include "MipsGenCallingConv.inc"
1683
Akira Hatanaka4552c9a2011-04-15 21:51:11 +00001684//===----------------------------------------------------------------------===//
Wesley Peckbf17cfa2010-11-23 03:31:01 +00001685// TODO: Implement a generic logic using tblgen that can support this.
Bruno Cardoso Lopesb53db4f2009-03-19 02:12:28 +00001686// Mips O32 ABI rules:
1687// ---
1688// i32 - Passed in A0, A1, A2, A3 and stack
Wesley Peckbf17cfa2010-11-23 03:31:01 +00001689// f32 - Only passed in f32 registers if no int reg has been used yet to hold
Bruno Cardoso Lopesb53db4f2009-03-19 02:12:28 +00001690// an argument. Otherwise, passed in A1, A2, A3 and stack.
Wesley Peckbf17cfa2010-11-23 03:31:01 +00001691// f64 - Only passed in two aliased f32 registers if no int reg has been used
1692// yet to hold an argument. Otherwise, use A2, A3 and stack. If A1 is
Bruno Cardoso Lopesb53db4f2009-03-19 02:12:28 +00001693// not used, it must be shadowed. If only A3 is avaiable, shadow it and
1694// go to stack.
Akira Hatanaka95b8ae12011-05-19 18:06:05 +00001695//
1696// For vararg functions, all arguments are passed in A0, A1, A2, A3 and stack.
Akira Hatanaka4552c9a2011-04-15 21:51:11 +00001697//===----------------------------------------------------------------------===//
Bruno Cardoso Lopesb53db4f2009-03-19 02:12:28 +00001698
Duncan Sands1e96bab2010-11-04 10:49:57 +00001699static bool CC_MipsO32(unsigned ValNo, MVT ValVT,
Duncan Sands1440e8b2010-11-03 11:35:31 +00001700 MVT LocVT, CCValAssign::LocInfo LocInfo,
Bruno Cardoso Lopesb53db4f2009-03-19 02:12:28 +00001701 ISD::ArgFlagsTy ArgFlags, CCState &State) {
1702
Wesley Peckbf17cfa2010-11-23 03:31:01 +00001703 static const unsigned IntRegsSize=4, FloatRegsSize=2;
Bruno Cardoso Lopesb53db4f2009-03-19 02:12:28 +00001704
1705 static const unsigned IntRegs[] = {
1706 Mips::A0, Mips::A1, Mips::A2, Mips::A3
1707 };
1708 static const unsigned F32Regs[] = {
1709 Mips::F12, Mips::F14
1710 };
1711 static const unsigned F64Regs[] = {
1712 Mips::D6, Mips::D7
1713 };
1714
Akira Hatanaka4231c7e2011-05-24 19:18:33 +00001715 // ByVal Args
1716 if (ArgFlags.isByVal()) {
1717 State.HandleByVal(ValNo, ValVT, LocVT, LocInfo,
1718 1 /*MinSize*/, 4 /*MinAlign*/, ArgFlags);
1719 unsigned NextReg = (State.getNextStackOffset() + 3) / 4;
1720 for (unsigned r = State.getFirstUnallocated(IntRegs, IntRegsSize);
1721 r < std::min(IntRegsSize, NextReg); ++r)
1722 State.AllocateReg(IntRegs[r]);
1723 return false;
1724 }
1725
Bruno Cardoso Lopesb37a7422010-02-06 19:20:49 +00001726 // Promote i8 and i16
1727 if (LocVT == MVT::i8 || LocVT == MVT::i16) {
1728 LocVT = MVT::i32;
1729 if (ArgFlags.isSExt())
1730 LocInfo = CCValAssign::SExt;
1731 else if (ArgFlags.isZExt())
1732 LocInfo = CCValAssign::ZExt;
1733 else
1734 LocInfo = CCValAssign::AExt;
1735 }
1736
Bruno Cardoso Lopesc42fb5f2011-03-04 20:27:44 +00001737 unsigned Reg;
1738
Akira Hatanaka95b8ae12011-05-19 18:06:05 +00001739 // f32 and f64 are allocated in A0, A1, A2, A3 when either of the following
1740 // is true: function is vararg, argument is 3rd or higher, there is previous
1741 // argument which is not f32 or f64.
1742 bool AllocateFloatsInIntReg = State.isVarArg() || ValNo > 1
1743 || State.getFirstUnallocated(F32Regs, FloatRegsSize) != ValNo;
Akira Hatanakaa1a7ba82011-05-19 20:29:48 +00001744 unsigned OrigAlign = ArgFlags.getOrigAlign();
1745 bool isI64 = (ValVT == MVT::i32 && OrigAlign == 8);
Akira Hatanaka95b8ae12011-05-19 18:06:05 +00001746
1747 if (ValVT == MVT::i32 || (ValVT == MVT::f32 && AllocateFloatsInIntReg)) {
Bruno Cardoso Lopesc42fb5f2011-03-04 20:27:44 +00001748 Reg = State.AllocateReg(IntRegs, IntRegsSize);
Akira Hatanakaa1a7ba82011-05-19 20:29:48 +00001749 // If this is the first part of an i64 arg,
1750 // the allocated register must be either A0 or A2.
1751 if (isI64 && (Reg == Mips::A1 || Reg == Mips::A3))
1752 Reg = State.AllocateReg(IntRegs, IntRegsSize);
Bruno Cardoso Lopesc42fb5f2011-03-04 20:27:44 +00001753 LocVT = MVT::i32;
Akira Hatanaka95b8ae12011-05-19 18:06:05 +00001754 } else if (ValVT == MVT::f64 && AllocateFloatsInIntReg) {
1755 // Allocate int register and shadow next int register. If first
1756 // available register is Mips::A1 or Mips::A3, shadow it too.
Bruno Cardoso Lopesc42fb5f2011-03-04 20:27:44 +00001757 Reg = State.AllocateReg(IntRegs, IntRegsSize);
1758 if (Reg == Mips::A1 || Reg == Mips::A3)
1759 Reg = State.AllocateReg(IntRegs, IntRegsSize);
1760 State.AllocateReg(IntRegs, IntRegsSize);
1761 LocVT = MVT::i32;
Akira Hatanaka95b8ae12011-05-19 18:06:05 +00001762 } else if (ValVT.isFloatingPoint() && !AllocateFloatsInIntReg) {
1763 // we are guaranteed to find an available float register
1764 if (ValVT == MVT::f32) {
1765 Reg = State.AllocateReg(F32Regs, FloatRegsSize);
1766 // Shadow int register
1767 State.AllocateReg(IntRegs, IntRegsSize);
1768 } else {
1769 Reg = State.AllocateReg(F64Regs, FloatRegsSize);
1770 // Shadow int registers
1771 unsigned Reg2 = State.AllocateReg(IntRegs, IntRegsSize);
1772 if (Reg2 == Mips::A1 || Reg2 == Mips::A3)
1773 State.AllocateReg(IntRegs, IntRegsSize);
1774 State.AllocateReg(IntRegs, IntRegsSize);
1775 }
Bruno Cardoso Lopesc42fb5f2011-03-04 20:27:44 +00001776 } else
1777 llvm_unreachable("Cannot handle this ValVT.");
Bruno Cardoso Lopesb37a7422010-02-06 19:20:49 +00001778
Akira Hatanakad37776d2011-05-20 21:39:54 +00001779 unsigned SizeInBytes = ValVT.getSizeInBits() >> 3;
1780 unsigned Offset = State.AllocateStack(SizeInBytes, OrigAlign);
1781
1782 if (!Reg)
Bruno Cardoso Lopesc42fb5f2011-03-04 20:27:44 +00001783 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
Akira Hatanakad37776d2011-05-20 21:39:54 +00001784 else
Bruno Cardoso Lopesc42fb5f2011-03-04 20:27:44 +00001785 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
Bruno Cardoso Lopesb37a7422010-02-06 19:20:49 +00001786
Bruno Cardoso Lopesc42fb5f2011-03-04 20:27:44 +00001787 return false; // CC must always match
Bruno Cardoso Lopesb37a7422010-02-06 19:20:49 +00001788}
1789
Akira Hatanaka4552c9a2011-04-15 21:51:11 +00001790//===----------------------------------------------------------------------===//
Dan Gohman98ca4f22009-08-05 01:29:28 +00001791// Call Calling Convention Implementation
Akira Hatanaka4552c9a2011-04-15 21:51:11 +00001792//===----------------------------------------------------------------------===//
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00001793
Akira Hatanaka4231c7e2011-05-24 19:18:33 +00001794static const unsigned O32IntRegsSize = 4;
1795
1796static const unsigned O32IntRegs[] = {
1797 Mips::A0, Mips::A1, Mips::A2, Mips::A3
1798};
1799
1800// Write ByVal Arg to arg registers and stack.
1801static void
Akira Hatanakada7f5f12011-09-19 20:26:02 +00001802WriteByValArg(SDValue& ByValChain, SDValue Chain, DebugLoc dl,
Akira Hatanaka4231c7e2011-05-24 19:18:33 +00001803 SmallVector<std::pair<unsigned, SDValue>, 16>& RegsToPass,
1804 SmallVector<SDValue, 8>& MemOpChains, int& LastFI,
1805 MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg,
Akira Hatanakaedacba82011-05-25 17:32:06 +00001806 const CCValAssign &VA, const ISD::ArgFlagsTy& Flags,
Akira Hatanaka5ac85472011-08-18 23:39:37 +00001807 MVT PtrType, bool isLittle) {
1808 unsigned LocMemOffset = VA.getLocMemOffset();
1809 unsigned Offset = 0;
1810 uint32_t RemainingSize = Flags.getByValSize();
Akira Hatanaka5c21c9e2011-08-12 21:30:06 +00001811 unsigned ByValAlign = Flags.getByValAlign();
Akira Hatanaka4231c7e2011-05-24 19:18:33 +00001812
Akira Hatanaka5ac85472011-08-18 23:39:37 +00001813 // Copy the first 4 words of byval arg to registers A0 - A3.
1814 // FIXME: Use a stricter alignment if it enables better optimization in passes
1815 // run later.
1816 for (; RemainingSize >= 4 && LocMemOffset < 4 * 4;
1817 Offset += 4, RemainingSize -= 4, LocMemOffset += 4) {
Akira Hatanaka4231c7e2011-05-24 19:18:33 +00001818 SDValue LoadPtr = DAG.getNode(ISD::ADD, dl, MVT::i32, Arg,
Akira Hatanaka5ac85472011-08-18 23:39:37 +00001819 DAG.getConstant(Offset, MVT::i32));
Akira Hatanaka4231c7e2011-05-24 19:18:33 +00001820 SDValue LoadVal = DAG.getLoad(MVT::i32, dl, Chain, LoadPtr,
1821 MachinePointerInfo(),
Akira Hatanaka5c21c9e2011-08-12 21:30:06 +00001822 false, false, std::min(ByValAlign,
1823 (unsigned )4));
Akira Hatanaka4231c7e2011-05-24 19:18:33 +00001824 MemOpChains.push_back(LoadVal.getValue(1));
Akira Hatanaka5ac85472011-08-18 23:39:37 +00001825 unsigned DstReg = O32IntRegs[LocMemOffset / 4];
Akira Hatanaka4231c7e2011-05-24 19:18:33 +00001826 RegsToPass.push_back(std::make_pair(DstReg, LoadVal));
1827 }
1828
Akira Hatanaka5ac85472011-08-18 23:39:37 +00001829 if (RemainingSize == 0)
1830 return;
1831
1832 // If there still is a register available for argument passing, write the
1833 // remaining part of the structure to it using subword loads and shifts.
1834 if (LocMemOffset < 4 * 4) {
1835 assert(RemainingSize <= 3 && RemainingSize >= 1 &&
1836 "There must be one to three bytes remaining.");
1837 unsigned LoadSize = (RemainingSize == 3 ? 2 : RemainingSize);
1838 SDValue LoadPtr = DAG.getNode(ISD::ADD, dl, MVT::i32, Arg,
1839 DAG.getConstant(Offset, MVT::i32));
1840 unsigned Alignment = std::min(ByValAlign, (unsigned )4);
1841 SDValue LoadVal = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, Chain,
1842 LoadPtr, MachinePointerInfo(),
1843 MVT::getIntegerVT(LoadSize * 8), false,
1844 false, Alignment);
1845 MemOpChains.push_back(LoadVal.getValue(1));
1846
1847 // If target is big endian, shift it to the most significant half-word or
1848 // byte.
1849 if (!isLittle)
1850 LoadVal = DAG.getNode(ISD::SHL, dl, MVT::i32, LoadVal,
1851 DAG.getConstant(32 - LoadSize * 8, MVT::i32));
1852
1853 Offset += LoadSize;
1854 RemainingSize -= LoadSize;
1855
1856 // Read second subword if necessary.
1857 if (RemainingSize != 0) {
1858 assert(RemainingSize == 1 && "There must be one byte remaining.");
1859 LoadPtr = DAG.getNode(ISD::ADD, dl, MVT::i32, Arg,
1860 DAG.getConstant(Offset, MVT::i32));
1861 unsigned Alignment = std::min(ByValAlign, (unsigned )2);
1862 SDValue Subword = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, Chain,
1863 LoadPtr, MachinePointerInfo(),
1864 MVT::i8, false, false, Alignment);
1865 MemOpChains.push_back(Subword.getValue(1));
1866 // Insert the loaded byte to LoadVal.
1867 // FIXME: Use INS if supported by target.
1868 unsigned ShiftAmt = isLittle ? 16 : 8;
1869 SDValue Shift = DAG.getNode(ISD::SHL, dl, MVT::i32, Subword,
1870 DAG.getConstant(ShiftAmt, MVT::i32));
1871 LoadVal = DAG.getNode(ISD::OR, dl, MVT::i32, LoadVal, Shift);
1872 }
1873
1874 unsigned DstReg = O32IntRegs[LocMemOffset / 4];
1875 RegsToPass.push_back(std::make_pair(DstReg, LoadVal));
1876 return;
Akira Hatanaka4231c7e2011-05-24 19:18:33 +00001877 }
Akira Hatanaka5ac85472011-08-18 23:39:37 +00001878
1879 // Create a fixed object on stack at offset LocMemOffset and copy
1880 // remaining part of byval arg to it using memcpy.
1881 SDValue Src = DAG.getNode(ISD::ADD, dl, MVT::i32, Arg,
1882 DAG.getConstant(Offset, MVT::i32));
1883 LastFI = MFI->CreateFixedObject(RemainingSize, LocMemOffset, true);
1884 SDValue Dst = DAG.getFrameIndex(LastFI, PtrType);
Akira Hatanakada7f5f12011-09-19 20:26:02 +00001885 ByValChain = DAG.getMemcpy(ByValChain, dl, Dst, Src,
1886 DAG.getConstant(RemainingSize, MVT::i32),
1887 std::min(ByValAlign, (unsigned)4),
1888 /*isVolatile=*/false, /*AlwaysInline=*/false,
1889 MachinePointerInfo(0), MachinePointerInfo(0));
Akira Hatanaka4231c7e2011-05-24 19:18:33 +00001890}
1891
Dan Gohman98ca4f22009-08-05 01:29:28 +00001892/// LowerCall - functions arguments are copied from virtual regs to
Nate Begeman5bf4b752009-01-26 03:15:54 +00001893/// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
Bruno Cardoso Lopesb37a7422010-02-06 19:20:49 +00001894/// TODO: isTailCall.
Dan Gohman98ca4f22009-08-05 01:29:28 +00001895SDValue
Akira Hatanakada7f5f12011-09-19 20:26:02 +00001896MipsTargetLowering::LowerCall(SDValue InChain, SDValue Callee,
Sandeep Patel65c3c8f2009-09-02 08:44:58 +00001897 CallingConv::ID CallConv, bool isVarArg,
Evan Cheng0c439eb2010-01-27 00:07:07 +00001898 bool &isTailCall,
Dan Gohman98ca4f22009-08-05 01:29:28 +00001899 const SmallVectorImpl<ISD::OutputArg> &Outs,
Dan Gohmanc9403652010-07-07 15:54:55 +00001900 const SmallVectorImpl<SDValue> &OutVals,
Dan Gohman98ca4f22009-08-05 01:29:28 +00001901 const SmallVectorImpl<ISD::InputArg> &Ins,
1902 DebugLoc dl, SelectionDAG &DAG,
Dan Gohmand858e902010-04-17 15:26:15 +00001903 SmallVectorImpl<SDValue> &InVals) const {
Evan Cheng0c439eb2010-01-27 00:07:07 +00001904 // MIPs target does not yet support tail call optimization.
1905 isTailCall = false;
Dan Gohman98ca4f22009-08-05 01:29:28 +00001906
Bruno Cardoso Lopes2ab22d12007-07-11 23:16:16 +00001907 MachineFunction &MF = DAG.getMachineFunction();
Bruno Cardoso Lopes2ab22d12007-07-11 23:16:16 +00001908 MachineFrameInfo *MFI = MF.getFrameInfo();
Akira Hatanakad37776d2011-05-20 21:39:54 +00001909 const TargetFrameLowering *TFL = MF.getTarget().getFrameLowering();
Bruno Cardoso Lopesc517cb02009-09-01 17:27:58 +00001910 bool IsPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_;
Akira Hatanaka17a1e872011-05-20 18:39:33 +00001911 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00001912
1913 // Analyze operands of the call, assigning locations to each operand.
1914 SmallVector<CCValAssign, 16> ArgLocs;
Eric Christopher471e4222011-06-08 23:55:35 +00001915 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1916 getTargetMachine(), ArgLocs, *DAG.getContext());
Bruno Cardoso Lopes2ab22d12007-07-11 23:16:16 +00001917
Akira Hatanakabdd2ce92011-05-23 21:13:59 +00001918 if (Subtarget->isABI_O32())
Akira Hatanaka95b8ae12011-05-19 18:06:05 +00001919 CCInfo.AnalyzeCallOperands(Outs, CC_MipsO32);
Akira Hatanakabdd2ce92011-05-23 21:13:59 +00001920 else
Dan Gohman98ca4f22009-08-05 01:29:28 +00001921 CCInfo.AnalyzeCallOperands(Outs, CC_Mips);
Wesley Peckbf17cfa2010-11-23 03:31:01 +00001922
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00001923 // Get a count of how many bytes are to be pushed on the stack.
Akira Hatanaka3d21c242011-06-08 17:39:33 +00001924 unsigned NextStackOffset = CCInfo.getNextStackOffset();
1925
Akira Hatanakada7f5f12011-09-19 20:26:02 +00001926 // Chain is the output chain of the last Load/Store or CopyToReg node.
1927 // ByValChain is the output chain of the last Memcpy node created for copying
1928 // byval arguments to the stack.
1929 SDValue Chain, CallSeqStart, ByValChain;
1930 SDValue NextStackOffsetVal = DAG.getIntPtrConstant(NextStackOffset, true);
1931 Chain = CallSeqStart = DAG.getCALLSEQ_START(InChain, NextStackOffsetVal);
1932 ByValChain = InChain;
Akira Hatanaka3d21c242011-06-08 17:39:33 +00001933
1934 // If this is the first call, create a stack frame object that points to
1935 // a location to which .cprestore saves $gp.
1936 if (IsPIC && !MipsFI->getGPFI())
1937 MipsFI->setGPFI(MFI->CreateFixedObject(4, 0, true));
1938
Akira Hatanaka21afc632011-06-21 00:40:49 +00001939 // Get the frame index of the stack frame object that points to the location
1940 // of dynamically allocated area on the stack.
1941 int DynAllocFI = MipsFI->getDynAllocFI();
1942
Akira Hatanaka3d21c242011-06-08 17:39:33 +00001943 // Update size of the maximum argument space.
1944 // For O32, a minimum of four words (16 bytes) of argument space is
1945 // allocated.
1946 if (Subtarget->isABI_O32())
1947 NextStackOffset = std::max(NextStackOffset, (unsigned)16);
1948
1949 unsigned MaxCallFrameSize = MipsFI->getMaxCallFrameSize();
1950
1951 if (MaxCallFrameSize < NextStackOffset) {
1952 MipsFI->setMaxCallFrameSize(NextStackOffset);
1953
Akira Hatanaka21afc632011-06-21 00:40:49 +00001954 // Set the offsets relative to $sp of the $gp restore slot and dynamically
1955 // allocated stack space. These offsets must be aligned to a boundary
1956 // determined by the stack alignment of the ABI.
1957 unsigned StackAlignment = TFL->getStackAlignment();
1958 NextStackOffset = (NextStackOffset + StackAlignment - 1) /
1959 StackAlignment * StackAlignment;
1960
1961 if (IsPIC)
1962 MFI->setObjectOffset(MipsFI->getGPFI(), NextStackOffset);
1963
1964 MFI->setObjectOffset(DynAllocFI, NextStackOffset);
Akira Hatanaka3d21c242011-06-08 17:39:33 +00001965 }
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00001966
Bruno Cardoso Lopes225ca9c2008-07-05 19:05:21 +00001967 // With EABI is it possible to have 16 args on registers.
Dan Gohman475871a2008-07-27 21:46:04 +00001968 SmallVector<std::pair<unsigned, SDValue>, 16> RegsToPass;
1969 SmallVector<SDValue, 8> MemOpChains;
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00001970
Eric Christopher471e4222011-06-08 23:55:35 +00001971 int FirstFI = -MFI->getNumFixedObjects() - 1, LastFI = 0;
Akira Hatanaka43299772011-05-20 23:22:14 +00001972
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00001973 // Walk the register/memloc assignments, inserting copies/loads.
1974 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
Dan Gohmanc9403652010-07-07 15:54:55 +00001975 SDValue Arg = OutVals[i];
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00001976 CCValAssign &VA = ArgLocs[i];
1977
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00001978 // Promote the value if needed.
1979 switch (VA.getLocInfo()) {
Torok Edwinc23197a2009-07-14 16:55:14 +00001980 default: llvm_unreachable("Unknown loc info!");
Wesley Peckbf17cfa2010-11-23 03:31:01 +00001981 case CCValAssign::Full:
Bruno Cardoso Lopesb53db4f2009-03-19 02:12:28 +00001982 if (Subtarget->isABI_O32() && VA.isRegLoc()) {
Owen Anderson825b72b2009-08-11 20:47:22 +00001983 if (VA.getValVT() == MVT::f32 && VA.getLocVT() == MVT::i32)
Wesley Peckbf17cfa2010-11-23 03:31:01 +00001984 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg);
Owen Anderson825b72b2009-08-11 20:47:22 +00001985 if (VA.getValVT() == MVT::f64 && VA.getLocVT() == MVT::i32) {
Akira Hatanaka4552c9a2011-04-15 21:51:11 +00001986 SDValue Lo = DAG.getNode(MipsISD::ExtractElementF64, dl, MVT::i32,
1987 Arg, DAG.getConstant(0, MVT::i32));
Akira Hatanaka0bf3dfb2011-04-15 21:00:26 +00001988 SDValue Hi = DAG.getNode(MipsISD::ExtractElementF64, dl, MVT::i32,
1989 Arg, DAG.getConstant(1, MVT::i32));
Akira Hatanaka99a2e982011-04-15 19:52:08 +00001990 if (!Subtarget->isLittle())
1991 std::swap(Lo, Hi);
Bruno Cardoso Lopesb53db4f2009-03-19 02:12:28 +00001992 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Lo));
1993 RegsToPass.push_back(std::make_pair(VA.getLocReg()+1, Hi));
1994 continue;
Wesley Peckbf17cfa2010-11-23 03:31:01 +00001995 }
Bruno Cardoso Lopesb53db4f2009-03-19 02:12:28 +00001996 }
1997 break;
Chris Lattnere0b12152008-03-17 06:57:02 +00001998 case CCValAssign::SExt:
Dale Johannesen33c960f2009-02-04 20:06:27 +00001999 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
Chris Lattnere0b12152008-03-17 06:57:02 +00002000 break;
2001 case CCValAssign::ZExt:
Dale Johannesen33c960f2009-02-04 20:06:27 +00002002 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
Chris Lattnere0b12152008-03-17 06:57:02 +00002003 break;
2004 case CCValAssign::AExt:
Dale Johannesen33c960f2009-02-04 20:06:27 +00002005 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
Chris Lattnere0b12152008-03-17 06:57:02 +00002006 break;
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002007 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +00002008
2009 // Arguments that can be passed on register must be kept at
Bruno Cardoso Lopesc7db5612007-11-05 03:02:32 +00002010 // RegsToPass vector
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002011 if (VA.isRegLoc()) {
2012 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
Chris Lattnere0b12152008-03-17 06:57:02 +00002013 continue;
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002014 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +00002015
Bruno Cardoso Lopesb53db4f2009-03-19 02:12:28 +00002016 // Register can't get to this point...
Chris Lattnere0b12152008-03-17 06:57:02 +00002017 assert(VA.isMemLoc());
Wesley Peckbf17cfa2010-11-23 03:31:01 +00002018
Eric Christopher471e4222011-06-08 23:55:35 +00002019 // ByVal Arg.
Akira Hatanaka4231c7e2011-05-24 19:18:33 +00002020 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2021 if (Flags.isByVal()) {
2022 assert(Subtarget->isABI_O32() &&
2023 "No support for ByVal args by ABIs other than O32 yet.");
2024 assert(Flags.getByValSize() &&
2025 "ByVal args of size 0 should have been ignored by front-end.");
Akira Hatanakada7f5f12011-09-19 20:26:02 +00002026 WriteByValArg(ByValChain, Chain, dl, RegsToPass, MemOpChains, LastFI, MFI,
2027 DAG, Arg, VA, Flags, getPointerTy(), Subtarget->isLittle());
Akira Hatanaka4231c7e2011-05-24 19:18:33 +00002028 continue;
2029 }
2030
Chris Lattnere0b12152008-03-17 06:57:02 +00002031 // Create the frame index object for this incoming parameter
Eric Christopher471e4222011-06-08 23:55:35 +00002032 LastFI = MFI->CreateFixedObject(VA.getValVT().getSizeInBits()/8,
Akira Hatanakab4d8d312011-05-24 00:23:52 +00002033 VA.getLocMemOffset(), true);
Akira Hatanaka43299772011-05-20 23:22:14 +00002034 SDValue PtrOff = DAG.getFrameIndex(LastFI, getPointerTy());
Chris Lattnere0b12152008-03-17 06:57:02 +00002035
Wesley Peckbf17cfa2010-11-23 03:31:01 +00002036 // emit ISD::STORE whichs stores the
Chris Lattnere0b12152008-03-17 06:57:02 +00002037 // parameter value to a stack Location
Chris Lattner8026a9d2010-09-21 17:50:43 +00002038 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
2039 MachinePointerInfo(),
David Greenef6fa1862010-02-15 16:56:10 +00002040 false, false, 0));
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002041 }
2042
Akira Hatanaka3d21c242011-06-08 17:39:33 +00002043 // Extend range of indices of frame objects for outgoing arguments that were
2044 // created during this function call. Skip this step if no such objects were
2045 // created.
2046 if (LastFI)
2047 MipsFI->extendOutArgFIRange(FirstFI, LastFI);
2048
Akira Hatanakada7f5f12011-09-19 20:26:02 +00002049 // If a memcpy has been created to copy a byval arg to a stack, replace the
2050 // chain input of CallSeqStart with ByValChain.
2051 if (InChain != ByValChain)
2052 DAG.UpdateNodeOperands(CallSeqStart.getNode(), ByValChain,
2053 NextStackOffsetVal);
2054
Bruno Cardoso Lopes225ca9c2008-07-05 19:05:21 +00002055 // Transform all store nodes into one single node because all store
2056 // nodes are independent of each other.
Wesley Peckbf17cfa2010-11-23 03:31:01 +00002057 if (!MemOpChains.empty())
2058 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002059 &MemOpChains[0], MemOpChains.size());
2060
Bill Wendling056292f2008-09-16 21:48:12 +00002061 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
Wesley Peckbf17cfa2010-11-23 03:31:01 +00002062 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
2063 // node so that legalize doesn't hack it.
Bruno Cardoso Lopesc517cb02009-09-01 17:27:58 +00002064 unsigned char OpFlag = IsPIC ? MipsII::MO_GOT_CALL : MipsII::MO_NO_FLAG;
Akira Hatanakaf49fde22011-04-04 17:11:07 +00002065 bool LoadSymAddr = false;
Akira Hatanaka9777e7a2011-04-07 19:51:44 +00002066 SDValue CalleeLo;
Akira Hatanakaf49fde22011-04-04 17:11:07 +00002067
2068 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
Akira Hatanaka9777e7a2011-04-07 19:51:44 +00002069 if (IsPIC && G->getGlobal()->hasInternalLinkage()) {
2070 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl,
2071 getPointerTy(), 0,MipsII:: MO_GOT);
2072 CalleeLo = DAG.getTargetGlobalAddress(G->getGlobal(), dl, getPointerTy(),
2073 0, MipsII::MO_ABS_LO);
2074 } else {
2075 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl,
2076 getPointerTy(), 0, OpFlag);
2077 }
2078
Akira Hatanakaf49fde22011-04-04 17:11:07 +00002079 LoadSymAddr = true;
2080 }
2081 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
Wesley Peckbf17cfa2010-11-23 03:31:01 +00002082 Callee = DAG.getTargetExternalSymbol(S->getSymbol(),
Bruno Cardoso Lopesc517cb02009-09-01 17:27:58 +00002083 getPointerTy(), OpFlag);
Akira Hatanakaf49fde22011-04-04 17:11:07 +00002084 LoadSymAddr = true;
2085 }
2086
Akira Hatanakacd0f90f2011-05-20 02:30:51 +00002087 SDValue InFlag;
2088
Akira Hatanakaf49fde22011-04-04 17:11:07 +00002089 // Create nodes that load address of callee and copy it to T9
2090 if (IsPIC) {
2091 if (LoadSymAddr) {
Akira Hatanaka9777e7a2011-04-07 19:51:44 +00002092 // Load callee address
Akira Hatanaka342837d2011-05-28 01:07:07 +00002093 Callee = DAG.getNode(MipsISD::WrapperPIC, dl, MVT::i32, Callee);
Akira Hatanaka25eba392011-06-24 19:01:25 +00002094 SDValue LoadValue = DAG.getLoad(MVT::i32, dl, DAG.getEntryNode(), Callee,
Akira Hatanaka9777e7a2011-04-07 19:51:44 +00002095 MachinePointerInfo::getGOT(),
2096 false, false, 0);
2097
2098 // Use GOT+LO if callee has internal linkage.
2099 if (CalleeLo.getNode()) {
2100 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, CalleeLo);
2101 Callee = DAG.getNode(ISD::ADD, dl, MVT::i32, LoadValue, Lo);
2102 } else
2103 Callee = LoadValue;
Akira Hatanakaf49fde22011-04-04 17:11:07 +00002104 }
2105
2106 // copy to T9
2107 Chain = DAG.getCopyToReg(Chain, dl, Mips::T9, Callee, SDValue(0, 0));
2108 InFlag = Chain.getValue(1);
2109 Callee = DAG.getRegister(Mips::T9, MVT::i32);
2110 }
Bill Wendling056292f2008-09-16 21:48:12 +00002111
Akira Hatanakacd0f90f2011-05-20 02:30:51 +00002112 // Build a sequence of copy-to-reg nodes chained together with token
2113 // chain and flag operands which copy the outgoing args into registers.
2114 // The InFlag in necessary since all emitted instructions must be
2115 // stuck together.
2116 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2117 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2118 RegsToPass[i].second, InFlag);
2119 InFlag = Chain.getValue(1);
2120 }
2121
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002122 // MipsJmpLink = #chain, #target_address, #opt_in_flags...
Wesley Peckbf17cfa2010-11-23 03:31:01 +00002123 // = Chain, Callee, Reg#1, Reg#2, ...
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002124 //
2125 // Returns a chain & a flag for retval copy to use.
Chris Lattnerf1b4eaf2010-12-21 02:38:05 +00002126 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
Dan Gohman475871a2008-07-27 21:46:04 +00002127 SmallVector<SDValue, 8> Ops;
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002128 Ops.push_back(Chain);
2129 Ops.push_back(Callee);
2130
Wesley Peckbf17cfa2010-11-23 03:31:01 +00002131 // Add argument registers to the end of the list so that they are
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002132 // known live into the call.
2133 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2134 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2135 RegsToPass[i].second.getValueType()));
2136
Gabor Greifba36cb52008-08-28 21:40:38 +00002137 if (InFlag.getNode())
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002138 Ops.push_back(InFlag);
2139
Dale Johannesen33c960f2009-02-04 20:06:27 +00002140 Chain = DAG.getNode(MipsISD::JmpLink, dl, NodeTys, &Ops[0], Ops.size());
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002141 InFlag = Chain.getValue(1);
2142
Bruno Cardoso Lopes3ed6f872010-01-30 18:32:07 +00002143 // Create the CALLSEQ_END node.
Akira Hatanaka5f7451f2011-06-21 01:02:03 +00002144 Chain = DAG.getCALLSEQ_END(Chain,
2145 DAG.getIntPtrConstant(NextStackOffset, true),
Bruno Cardoso Lopes3ed6f872010-01-30 18:32:07 +00002146 DAG.getIntPtrConstant(0, true), InFlag);
2147 InFlag = Chain.getValue(1);
2148
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002149 // Handle result values, copying them out of physregs into vregs that we
2150 // return.
Dan Gohman98ca4f22009-08-05 01:29:28 +00002151 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
2152 Ins, dl, DAG, InVals);
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002153}
2154
Dan Gohman98ca4f22009-08-05 01:29:28 +00002155/// LowerCallResult - Lower the result values of a call into the
2156/// appropriate copies out of appropriate physical registers.
2157SDValue
2158MipsTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
Sandeep Patel65c3c8f2009-09-02 08:44:58 +00002159 CallingConv::ID CallConv, bool isVarArg,
Dan Gohman98ca4f22009-08-05 01:29:28 +00002160 const SmallVectorImpl<ISD::InputArg> &Ins,
2161 DebugLoc dl, SelectionDAG &DAG,
Dan Gohmand858e902010-04-17 15:26:15 +00002162 SmallVectorImpl<SDValue> &InVals) const {
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002163 // Assign locations to each value returned by this call.
2164 SmallVector<CCValAssign, 16> RVLocs;
Eric Christopher471e4222011-06-08 23:55:35 +00002165 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
2166 getTargetMachine(), RVLocs, *DAG.getContext());
Bruno Cardoso Lopes2ab22d12007-07-11 23:16:16 +00002167
Dan Gohman98ca4f22009-08-05 01:29:28 +00002168 CCInfo.AnalyzeCallResult(Ins, RetCC_Mips);
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002169
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002170 // Copy all of the result registers out of their specified physreg.
2171 for (unsigned i = 0; i != RVLocs.size(); ++i) {
Dale Johannesen33c960f2009-02-04 20:06:27 +00002172 Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(),
Dan Gohman98ca4f22009-08-05 01:29:28 +00002173 RVLocs[i].getValVT(), InFlag).getValue(1);
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002174 InFlag = Chain.getValue(2);
Dan Gohman98ca4f22009-08-05 01:29:28 +00002175 InVals.push_back(Chain.getValue(0));
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002176 }
Bruno Cardoso Lopesc7db5612007-11-05 03:02:32 +00002177
Dan Gohman98ca4f22009-08-05 01:29:28 +00002178 return Chain;
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002179}
2180
Akira Hatanaka4552c9a2011-04-15 21:51:11 +00002181//===----------------------------------------------------------------------===//
Dan Gohman98ca4f22009-08-05 01:29:28 +00002182// Formal Arguments Calling Convention Implementation
Akira Hatanaka4552c9a2011-04-15 21:51:11 +00002183//===----------------------------------------------------------------------===//
Akira Hatanaka4231c7e2011-05-24 19:18:33 +00002184static void ReadByValArg(MachineFunction &MF, SDValue Chain, DebugLoc dl,
2185 std::vector<SDValue>& OutChains,
2186 SelectionDAG &DAG, unsigned NumWords, SDValue FIN,
2187 const CCValAssign &VA, const ISD::ArgFlagsTy& Flags) {
2188 unsigned LocMem = VA.getLocMemOffset();
2189 unsigned FirstWord = LocMem / 4;
2190
2191 // copy register A0 - A3 to frame object
2192 for (unsigned i = 0; i < NumWords; ++i) {
2193 unsigned CurWord = FirstWord + i;
2194 if (CurWord >= O32IntRegsSize)
2195 break;
2196
2197 unsigned SrcReg = O32IntRegs[CurWord];
2198 unsigned Reg = AddLiveIn(MF, SrcReg, Mips::CPURegsRegisterClass);
2199 SDValue StorePtr = DAG.getNode(ISD::ADD, dl, MVT::i32, FIN,
2200 DAG.getConstant(i * 4, MVT::i32));
2201 SDValue Store = DAG.getStore(Chain, dl, DAG.getRegister(Reg, MVT::i32),
2202 StorePtr, MachinePointerInfo(), false,
2203 false, 0);
2204 OutChains.push_back(Store);
2205 }
2206}
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002207
Wesley Peckbf17cfa2010-11-23 03:31:01 +00002208/// LowerFormalArguments - transform physical registers into virtual registers
Bruno Cardoso Lopesb37a7422010-02-06 19:20:49 +00002209/// and generate load operations for arguments places on the stack.
Dan Gohman98ca4f22009-08-05 01:29:28 +00002210SDValue
2211MipsTargetLowering::LowerFormalArguments(SDValue Chain,
Akira Hatanaka0bf3dfb2011-04-15 21:00:26 +00002212 CallingConv::ID CallConv,
2213 bool isVarArg,
2214 const SmallVectorImpl<ISD::InputArg>
2215 &Ins,
2216 DebugLoc dl, SelectionDAG &DAG,
2217 SmallVectorImpl<SDValue> &InVals)
Akira Hatanaka4552c9a2011-04-15 21:51:11 +00002218 const {
Bruno Cardoso Lopesf7f3b502008-08-04 07:12:52 +00002219 MachineFunction &MF = DAG.getMachineFunction();
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002220 MachineFrameInfo *MFI = MF.getFrameInfo();
Bruno Cardoso Lopesa2b1bb52007-08-28 05:08:16 +00002221 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
Bruno Cardoso Lopes2ab22d12007-07-11 23:16:16 +00002222
Dan Gohman1e93df62010-04-17 14:41:14 +00002223 MipsFI->setVarArgsFrameIndex(0);
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002224
Bruno Cardoso Lopesb37a7422010-02-06 19:20:49 +00002225 // Used with vargs to acumulate store chains.
2226 std::vector<SDValue> OutChains;
2227
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002228 // Assign locations to all of the incoming arguments.
2229 SmallVector<CCValAssign, 16> ArgLocs;
Eric Christopher471e4222011-06-08 23:55:35 +00002230 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
2231 getTargetMachine(), ArgLocs, *DAG.getContext());
Bruno Cardoso Lopes2ab22d12007-07-11 23:16:16 +00002232
Bruno Cardoso Lopesb53db4f2009-03-19 02:12:28 +00002233 if (Subtarget->isABI_O32())
Akira Hatanaka95b8ae12011-05-19 18:06:05 +00002234 CCInfo.AnalyzeFormalArguments(Ins, CC_MipsO32);
Bruno Cardoso Lopesb53db4f2009-03-19 02:12:28 +00002235 else
Dan Gohman98ca4f22009-08-05 01:29:28 +00002236 CCInfo.AnalyzeFormalArguments(Ins, CC_Mips);
Bruno Cardoso Lopesb53db4f2009-03-19 02:12:28 +00002237
Akira Hatanaka43299772011-05-20 23:22:14 +00002238 int LastFI = 0;// MipsFI->LastInArgFI is 0 at the entry of this function.
Bruno Cardoso Lopes225ca9c2008-07-05 19:05:21 +00002239
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002240 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002241 CCValAssign &VA = ArgLocs[i];
2242
2243 // Arguments stored on registers
2244 if (VA.isRegLoc()) {
Owen Andersone50ed302009-08-10 22:56:29 +00002245 EVT RegVT = VA.getLocVT();
Akira Hatanakab4d8d312011-05-24 00:23:52 +00002246 unsigned ArgReg = VA.getLocReg();
Bill Wendling06b8c192008-07-09 05:55:53 +00002247 TargetRegisterClass *RC = 0;
Bruno Cardoso Lopesb53db4f2009-03-19 02:12:28 +00002248
Owen Anderson825b72b2009-08-11 20:47:22 +00002249 if (RegVT == MVT::i32)
Wesley Peckbf17cfa2010-11-23 03:31:01 +00002250 RC = Mips::CPURegsRegisterClass;
2251 else if (RegVT == MVT::f32)
Bruno Cardoso Lopesbdfbb742009-03-21 00:05:07 +00002252 RC = Mips::FGR32RegisterClass;
Owen Anderson825b72b2009-08-11 20:47:22 +00002253 else if (RegVT == MVT::f64) {
Wesley Peckbf17cfa2010-11-23 03:31:01 +00002254 if (!Subtarget->isSingleFloat())
Bruno Cardoso Lopes225ca9c2008-07-05 19:05:21 +00002255 RC = Mips::AFGR64RegisterClass;
Wesley Peckbf17cfa2010-11-23 03:31:01 +00002256 } else
Bruno Cardoso Lopesb37a7422010-02-06 19:20:49 +00002257 llvm_unreachable("RegVT not supported by FormalArguments Lowering");
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002258
Wesley Peckbf17cfa2010-11-23 03:31:01 +00002259 // Transform the arguments stored on
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002260 // physical registers into virtual ones
Akira Hatanakab4d8d312011-05-24 00:23:52 +00002261 unsigned Reg = AddLiveIn(DAG.getMachineFunction(), ArgReg, RC);
Dan Gohman98ca4f22009-08-05 01:29:28 +00002262 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
Wesley Peckbf17cfa2010-11-23 03:31:01 +00002263
2264 // If this is an 8 or 16-bit value, it has been passed promoted
2265 // to 32 bits. Insert an assert[sz]ext to capture this, then
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002266 // truncate to the right size.
Bruno Cardoso Lopesb53db4f2009-03-19 02:12:28 +00002267 if (VA.getLocInfo() != CCValAssign::Full) {
Chris Lattnerd4015072009-03-26 05:28:14 +00002268 unsigned Opcode = 0;
Bruno Cardoso Lopesb53db4f2009-03-19 02:12:28 +00002269 if (VA.getLocInfo() == CCValAssign::SExt)
2270 Opcode = ISD::AssertSext;
2271 else if (VA.getLocInfo() == CCValAssign::ZExt)
2272 Opcode = ISD::AssertZext;
Chris Lattnerd4015072009-03-26 05:28:14 +00002273 if (Opcode)
Wesley Peckbf17cfa2010-11-23 03:31:01 +00002274 ArgValue = DAG.getNode(Opcode, dl, RegVT, ArgValue,
Chris Lattnerd4015072009-03-26 05:28:14 +00002275 DAG.getValueType(VA.getValVT()));
Dale Johannesen33c960f2009-02-04 20:06:27 +00002276 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
Bruno Cardoso Lopesb53db4f2009-03-19 02:12:28 +00002277 }
2278
Wesley Peckbf17cfa2010-11-23 03:31:01 +00002279 // Handle O32 ABI cases: i32->f32 and (i32,i32)->f64
Bruno Cardoso Lopesb53db4f2009-03-19 02:12:28 +00002280 if (Subtarget->isABI_O32()) {
Wesley Peckbf17cfa2010-11-23 03:31:01 +00002281 if (RegVT == MVT::i32 && VA.getValVT() == MVT::f32)
2282 ArgValue = DAG.getNode(ISD::BITCAST, dl, MVT::f32, ArgValue);
Owen Anderson825b72b2009-08-11 20:47:22 +00002283 if (RegVT == MVT::i32 && VA.getValVT() == MVT::f64) {
Wesley Peckbf17cfa2010-11-23 03:31:01 +00002284 unsigned Reg2 = AddLiveIn(DAG.getMachineFunction(),
Bruno Cardoso Lopesb53db4f2009-03-19 02:12:28 +00002285 VA.getLocReg()+1, RC);
Dan Gohman98ca4f22009-08-05 01:29:28 +00002286 SDValue ArgValue2 = DAG.getCopyFromReg(Chain, dl, Reg2, RegVT);
Akira Hatanaka99a2e982011-04-15 19:52:08 +00002287 if (!Subtarget->isLittle())
2288 std::swap(ArgValue, ArgValue2);
2289 ArgValue = DAG.getNode(MipsISD::BuildPairF64, dl, MVT::f64,
2290 ArgValue, ArgValue2);
Bruno Cardoso Lopesb53db4f2009-03-19 02:12:28 +00002291 }
2292 }
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002293
Dan Gohman98ca4f22009-08-05 01:29:28 +00002294 InVals.push_back(ArgValue);
Bruno Cardoso Lopes225ca9c2008-07-05 19:05:21 +00002295 } else { // VA.isRegLoc()
2296
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002297 // sanity check
2298 assert(VA.isMemLoc());
Bruno Cardoso Lopesb37a7422010-02-06 19:20:49 +00002299
Akira Hatanaka4231c7e2011-05-24 19:18:33 +00002300 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2301
2302 if (Flags.isByVal()) {
2303 assert(Subtarget->isABI_O32() &&
2304 "No support for ByVal args by ABIs other than O32 yet.");
2305 assert(Flags.getByValSize() &&
2306 "ByVal args of size 0 should have been ignored by front-end.");
2307 unsigned NumWords = (Flags.getByValSize() + 3) / 4;
2308 LastFI = MFI->CreateFixedObject(NumWords * 4, VA.getLocMemOffset(),
2309 true);
2310 SDValue FIN = DAG.getFrameIndex(LastFI, getPointerTy());
2311 InVals.push_back(FIN);
2312 ReadByValArg(MF, Chain, dl, OutChains, DAG, NumWords, FIN, VA, Flags);
2313
2314 continue;
2315 }
2316
Wesley Peckbf17cfa2010-11-23 03:31:01 +00002317 // The stack pointer offset is relative to the caller stack frame.
Akira Hatanakab4d8d312011-05-24 00:23:52 +00002318 LastFI = MFI->CreateFixedObject(VA.getValVT().getSizeInBits()/8,
2319 VA.getLocMemOffset(), true);
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002320
2321 // Create load nodes to retrieve arguments from the stack
Akira Hatanaka43299772011-05-20 23:22:14 +00002322 SDValue FIN = DAG.getFrameIndex(LastFI, getPointerTy());
Chris Lattnerd1c24ed2010-09-21 06:44:06 +00002323 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
Akira Hatanaka43299772011-05-20 23:22:14 +00002324 MachinePointerInfo::getFixedStack(LastFI),
David Greenef6fa1862010-02-15 16:56:10 +00002325 false, false, 0));
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002326 }
2327 }
Bruno Cardoso Lopes225ca9c2008-07-05 19:05:21 +00002328
2329 // The mips ABIs for returning structs by value requires that we copy
2330 // the sret argument into $v0 for the return. Save the argument into
2331 // a virtual register so that we can access it from the return points.
2332 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
2333 unsigned Reg = MipsFI->getSRetReturnReg();
2334 if (!Reg) {
Owen Anderson825b72b2009-08-11 20:47:22 +00002335 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i32));
Bruno Cardoso Lopes225ca9c2008-07-05 19:05:21 +00002336 MipsFI->setSRetReturnReg(Reg);
2337 }
Dan Gohman98ca4f22009-08-05 01:29:28 +00002338 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
Owen Anderson825b72b2009-08-11 20:47:22 +00002339 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
Bruno Cardoso Lopes225ca9c2008-07-05 19:05:21 +00002340 }
2341
Bruno Cardoso Lopes954dac02011-03-09 19:22:22 +00002342 if (isVarArg && Subtarget->isABI_O32()) {
Akira Hatanakab4d8d312011-05-24 00:23:52 +00002343 // Record the frame index of the first variable argument
Eric Christopher471e4222011-06-08 23:55:35 +00002344 // which is a value necessary to VASTART.
Akira Hatanakab4d8d312011-05-24 00:23:52 +00002345 unsigned NextStackOffset = CCInfo.getNextStackOffset();
Akira Hatanaka4231c7e2011-05-24 19:18:33 +00002346 assert(NextStackOffset % 4 == 0 &&
2347 "NextStackOffset must be aligned to 4-byte boundaries.");
Akira Hatanakab4d8d312011-05-24 00:23:52 +00002348 LastFI = MFI->CreateFixedObject(4, NextStackOffset, true);
2349 MipsFI->setVarArgsFrameIndex(LastFI);
Akira Hatanakaedacba82011-05-25 17:32:06 +00002350
2351 // If NextStackOffset is smaller than o32's 16-byte reserved argument area,
2352 // copy the integer registers that have not been used for argument passing
2353 // to the caller's stack frame.
Akira Hatanakab4d8d312011-05-24 00:23:52 +00002354 for (; NextStackOffset < 16; NextStackOffset += 4) {
Bruno Cardoso Lopes954dac02011-03-09 19:22:22 +00002355 TargetRegisterClass *RC = Mips::CPURegsRegisterClass;
Akira Hatanakab4d8d312011-05-24 00:23:52 +00002356 unsigned Idx = NextStackOffset / 4;
2357 unsigned Reg = AddLiveIn(DAG.getMachineFunction(), O32IntRegs[Idx], RC);
2358 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, MVT::i32);
Akira Hatanaka69c19f72011-05-23 20:16:59 +00002359 LastFI = MFI->CreateFixedObject(4, NextStackOffset, true);
Akira Hatanakab4d8d312011-05-24 00:23:52 +00002360 SDValue PtrOff = DAG.getFrameIndex(LastFI, getPointerTy());
2361 OutChains.push_back(DAG.getStore(Chain, dl, ArgValue, PtrOff,
2362 MachinePointerInfo(),
2363 false, false, 0));
Bruno Cardoso Lopesb37a7422010-02-06 19:20:49 +00002364 }
2365 }
2366
Akira Hatanaka43299772011-05-20 23:22:14 +00002367 MipsFI->setLastInArgFI(LastFI);
2368
Wesley Peckbf17cfa2010-11-23 03:31:01 +00002369 // All stores are grouped in one node to allow the matching between
Bruno Cardoso Lopesb37a7422010-02-06 19:20:49 +00002370 // the size of Ins and InVals. This only happens when on varg functions
2371 if (!OutChains.empty()) {
2372 OutChains.push_back(Chain);
2373 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2374 &OutChains[0], OutChains.size());
2375 }
2376
Dan Gohman98ca4f22009-08-05 01:29:28 +00002377 return Chain;
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002378}
2379
Akira Hatanaka4552c9a2011-04-15 21:51:11 +00002380//===----------------------------------------------------------------------===//
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002381// Return Value Calling Convention Implementation
Akira Hatanaka4552c9a2011-04-15 21:51:11 +00002382//===----------------------------------------------------------------------===//
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002383
Dan Gohman98ca4f22009-08-05 01:29:28 +00002384SDValue
2385MipsTargetLowering::LowerReturn(SDValue Chain,
Sandeep Patel65c3c8f2009-09-02 08:44:58 +00002386 CallingConv::ID CallConv, bool isVarArg,
Dan Gohman98ca4f22009-08-05 01:29:28 +00002387 const SmallVectorImpl<ISD::OutputArg> &Outs,
Dan Gohmanc9403652010-07-07 15:54:55 +00002388 const SmallVectorImpl<SDValue> &OutVals,
Dan Gohmand858e902010-04-17 15:26:15 +00002389 DebugLoc dl, SelectionDAG &DAG) const {
Dan Gohman98ca4f22009-08-05 01:29:28 +00002390
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002391 // CCValAssign - represent the assignment of
2392 // the return value to a location
2393 SmallVector<CCValAssign, 16> RVLocs;
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002394
2395 // CCState - Info about the registers and stack slot.
Eric Christopher471e4222011-06-08 23:55:35 +00002396 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
2397 getTargetMachine(), RVLocs, *DAG.getContext());
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002398
Dan Gohman98ca4f22009-08-05 01:29:28 +00002399 // Analize return values.
2400 CCInfo.AnalyzeReturn(Outs, RetCC_Mips);
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002401
Wesley Peckbf17cfa2010-11-23 03:31:01 +00002402 // If this is the first return lowered for this function, add
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002403 // the regs to the liveout set for the function.
Chris Lattner84bc5422007-12-31 04:13:23 +00002404 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002405 for (unsigned i = 0; i != RVLocs.size(); ++i)
Bruno Cardoso Lopes2ab22d12007-07-11 23:16:16 +00002406 if (RVLocs[i].isRegLoc())
Akira Hatanaka4552c9a2011-04-15 21:51:11 +00002407 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002408 }
2409
Dan Gohman475871a2008-07-27 21:46:04 +00002410 SDValue Flag;
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002411
2412 // Copy the result values into the output registers.
2413 for (unsigned i = 0; i != RVLocs.size(); ++i) {
2414 CCValAssign &VA = RVLocs[i];
2415 assert(VA.isRegLoc() && "Can only return in registers!");
2416
Wesley Peckbf17cfa2010-11-23 03:31:01 +00002417 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
Dan Gohmanc9403652010-07-07 15:54:55 +00002418 OutVals[i], Flag);
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002419
2420 // guarantee that all emitted copies are
2421 // stuck together, avoiding something bad
2422 Flag = Chain.getValue(1);
2423 }
2424
Bruno Cardoso Lopes225ca9c2008-07-05 19:05:21 +00002425 // The mips ABIs for returning structs by value requires that we copy
2426 // the sret argument into $v0 for the return. We saved the argument into
2427 // a virtual register in the entry block, so now we copy the value out
2428 // and into $v0.
2429 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
2430 MachineFunction &MF = DAG.getMachineFunction();
2431 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
2432 unsigned Reg = MipsFI->getSRetReturnReg();
2433
Wesley Peckbf17cfa2010-11-23 03:31:01 +00002434 if (!Reg)
Torok Edwinc23197a2009-07-14 16:55:14 +00002435 llvm_unreachable("sret virtual register not created in the entry block");
Dale Johannesena05dca42009-02-04 23:02:30 +00002436 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
Bruno Cardoso Lopes225ca9c2008-07-05 19:05:21 +00002437
Dale Johannesena05dca42009-02-04 23:02:30 +00002438 Chain = DAG.getCopyToReg(Chain, dl, Mips::V0, Val, Flag);
Bruno Cardoso Lopes225ca9c2008-07-05 19:05:21 +00002439 Flag = Chain.getValue(1);
2440 }
2441
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002442 // Return on Mips is always a "jr $ra"
Gabor Greifba36cb52008-08-28 21:40:38 +00002443 if (Flag.getNode())
Wesley Peckbf17cfa2010-11-23 03:31:01 +00002444 return DAG.getNode(MipsISD::Ret, dl, MVT::Other,
Owen Anderson825b72b2009-08-11 20:47:22 +00002445 Chain, DAG.getRegister(Mips::RA, MVT::i32), Flag);
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002446 else // Return Void
Wesley Peckbf17cfa2010-11-23 03:31:01 +00002447 return DAG.getNode(MipsISD::Ret, dl, MVT::Other,
Owen Anderson825b72b2009-08-11 20:47:22 +00002448 Chain, DAG.getRegister(Mips::RA, MVT::i32));
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002449}
Bruno Cardoso Lopes84f47c52007-08-21 16:09:25 +00002450
Akira Hatanaka4552c9a2011-04-15 21:51:11 +00002451//===----------------------------------------------------------------------===//
Bruno Cardoso Lopes84f47c52007-08-21 16:09:25 +00002452// Mips Inline Assembly Support
Akira Hatanaka4552c9a2011-04-15 21:51:11 +00002453//===----------------------------------------------------------------------===//
Bruno Cardoso Lopes84f47c52007-08-21 16:09:25 +00002454
2455/// getConstraintType - Given a constraint letter, return the type of
2456/// constraint it is for this target.
2457MipsTargetLowering::ConstraintType MipsTargetLowering::
Wesley Peckbf17cfa2010-11-23 03:31:01 +00002458getConstraintType(const std::string &Constraint) const
Bruno Cardoso Lopes84f47c52007-08-21 16:09:25 +00002459{
Wesley Peckbf17cfa2010-11-23 03:31:01 +00002460 // Mips specific constrainy
Bruno Cardoso Lopes225ca9c2008-07-05 19:05:21 +00002461 // GCC config/mips/constraints.md
2462 //
Wesley Peckbf17cfa2010-11-23 03:31:01 +00002463 // 'd' : An address register. Equivalent to r
2464 // unless generating MIPS16 code.
2465 // 'y' : Equivalent to r; retained for
2466 // backwards compatibility.
2467 // 'f' : Floating Point registers.
Bruno Cardoso Lopes84f47c52007-08-21 16:09:25 +00002468 if (Constraint.size() == 1) {
Bruno Cardoso Lopes84f47c52007-08-21 16:09:25 +00002469 switch (Constraint[0]) {
2470 default : break;
Wesley Peckbf17cfa2010-11-23 03:31:01 +00002471 case 'd':
2472 case 'y':
Bruno Cardoso Lopes225ca9c2008-07-05 19:05:21 +00002473 case 'f':
Bruno Cardoso Lopes84f47c52007-08-21 16:09:25 +00002474 return C_RegisterClass;
2475 break;
2476 }
2477 }
2478 return TargetLowering::getConstraintType(Constraint);
2479}
2480
John Thompson44ab89e2010-10-29 17:29:13 +00002481/// Examine constraint type and operand type and determine a weight value.
2482/// This object must already have been set up with the operand type
2483/// and the current alternative constraint selected.
2484TargetLowering::ConstraintWeight
2485MipsTargetLowering::getSingleConstraintMatchWeight(
2486 AsmOperandInfo &info, const char *constraint) const {
2487 ConstraintWeight weight = CW_Invalid;
2488 Value *CallOperandVal = info.CallOperandVal;
2489 // If we don't have a value, we can't do a match,
2490 // but allow it at the lowest weight.
2491 if (CallOperandVal == NULL)
2492 return CW_Default;
Chris Lattnerdb125cf2011-07-18 04:54:35 +00002493 Type *type = CallOperandVal->getType();
John Thompson44ab89e2010-10-29 17:29:13 +00002494 // Look at the constraint type.
2495 switch (*constraint) {
2496 default:
2497 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
2498 break;
Wesley Peckbf17cfa2010-11-23 03:31:01 +00002499 case 'd':
2500 case 'y':
John Thompson44ab89e2010-10-29 17:29:13 +00002501 if (type->isIntegerTy())
2502 weight = CW_Register;
2503 break;
2504 case 'f':
2505 if (type->isFloatTy())
2506 weight = CW_Register;
2507 break;
2508 }
2509 return weight;
2510}
2511
Eric Christopher38d64262011-06-29 19:33:04 +00002512/// Given a register class constraint, like 'r', if this corresponds directly
2513/// to an LLVM register class, return a register of 0 and the register class
2514/// pointer.
Bruno Cardoso Lopes84f47c52007-08-21 16:09:25 +00002515std::pair<unsigned, const TargetRegisterClass*> MipsTargetLowering::
Owen Andersone50ed302009-08-10 22:56:29 +00002516getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const
Bruno Cardoso Lopes84f47c52007-08-21 16:09:25 +00002517{
2518 if (Constraint.size() == 1) {
2519 switch (Constraint[0]) {
Eric Christopher314aff12011-06-29 19:04:31 +00002520 case 'd': // Address register. Same as 'r' unless generating MIPS16 code.
2521 case 'y': // Same as 'r'. Exists for compatibility.
Bruno Cardoso Lopes84f47c52007-08-21 16:09:25 +00002522 case 'r':
2523 return std::make_pair(0U, Mips::CPURegsRegisterClass);
Bruno Cardoso Lopes225ca9c2008-07-05 19:05:21 +00002524 case 'f':
Owen Anderson825b72b2009-08-11 20:47:22 +00002525 if (VT == MVT::f32)
Bruno Cardoso Lopesbdfbb742009-03-21 00:05:07 +00002526 return std::make_pair(0U, Mips::FGR32RegisterClass);
Wesley Peckbf17cfa2010-11-23 03:31:01 +00002527 if (VT == MVT::f64)
Bruno Cardoso Lopes225ca9c2008-07-05 19:05:21 +00002528 if ((!Subtarget->isSingleFloat()) && (!Subtarget->isFP64bit()))
2529 return std::make_pair(0U, Mips::AFGR64RegisterClass);
Eric Christopher314aff12011-06-29 19:04:31 +00002530 break;
Bruno Cardoso Lopes84f47c52007-08-21 16:09:25 +00002531 }
2532 }
2533 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
2534}
2535
Dan Gohman6520e202008-10-18 02:06:02 +00002536bool
2537MipsTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
2538 // The Mips target isn't yet aware of offsets.
2539 return false;
2540}
Evan Chengeb2f9692009-10-27 19:56:55 +00002541
Evan Chenga1eaa3c2009-10-28 01:43:28 +00002542bool MipsTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
2543 if (VT != MVT::f32 && VT != MVT::f64)
2544 return false;
Bruno Cardoso Lopes6b902822011-01-18 19:41:41 +00002545 if (Imm.isNegZero())
2546 return false;
Evan Chengeb2f9692009-10-27 19:56:55 +00002547 return Imm.isZero();
2548}