Evan Cheng | 3f32d65 | 2008-06-04 09:18:41 +0000 | [diff] [blame] | 1 | //===-- LiveStackAnalysis.cpp - Live Stack Slot Analysis ------------------===// |
| 2 | // |
| 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
| 5 | // This file is distributed under the University of Illinois Open Source |
| 6 | // License. See LICENSE.TXT for details. |
| 7 | // |
| 8 | //===----------------------------------------------------------------------===// |
| 9 | // |
| 10 | // This file implements the live stack slot analysis pass. It is analogous to |
| 11 | // live interval analysis except it's analyzing liveness of stack slots rather |
| 12 | // than registers. |
| 13 | // |
| 14 | //===----------------------------------------------------------------------===// |
| 15 | |
Evan Cheng | 3f32d65 | 2008-06-04 09:18:41 +0000 | [diff] [blame] | 16 | #include "llvm/CodeGen/LiveStackAnalysis.h" |
Chandler Carruth | d04a8d4 | 2012-12-03 16:50:05 +0000 | [diff] [blame] | 17 | #include "llvm/ADT/Statistic.h" |
Lang Hames | f41538d | 2009-06-02 16:53:25 +0000 | [diff] [blame] | 18 | #include "llvm/CodeGen/LiveIntervalAnalysis.h" |
Evan Cheng | 3f32d65 | 2008-06-04 09:18:41 +0000 | [diff] [blame] | 19 | #include "llvm/CodeGen/Passes.h" |
Evan Cheng | 3f32d65 | 2008-06-04 09:18:41 +0000 | [diff] [blame] | 20 | #include "llvm/Support/Debug.h" |
Chris Lattner | c02497f | 2009-08-23 03:47:42 +0000 | [diff] [blame] | 21 | #include "llvm/Support/raw_ostream.h" |
Chandler Carruth | d04a8d4 | 2012-12-03 16:50:05 +0000 | [diff] [blame] | 22 | #include "llvm/Target/TargetRegisterInfo.h" |
Lang Hames | f41538d | 2009-06-02 16:53:25 +0000 | [diff] [blame] | 23 | #include <limits> |
Evan Cheng | 3f32d65 | 2008-06-04 09:18:41 +0000 | [diff] [blame] | 24 | using namespace llvm; |
| 25 | |
Stephen Hines | dce4a40 | 2014-05-29 02:49:00 -0700 | [diff] [blame^] | 26 | #define DEBUG_TYPE "livestacks" |
| 27 | |
Evan Cheng | 3f32d65 | 2008-06-04 09:18:41 +0000 | [diff] [blame] | 28 | char LiveStacks::ID = 0; |
Evan Cheng | bb36a43 | 2012-09-21 20:04:28 +0000 | [diff] [blame] | 29 | INITIALIZE_PASS_BEGIN(LiveStacks, "livestacks", |
| 30 | "Live Stack Slot Analysis", false, false) |
| 31 | INITIALIZE_PASS_DEPENDENCY(SlotIndexes) |
| 32 | INITIALIZE_PASS_END(LiveStacks, "livestacks", |
Owen Anderson | ce665bd | 2010-10-07 22:25:06 +0000 | [diff] [blame] | 33 | "Live Stack Slot Analysis", false, false) |
Evan Cheng | 3f32d65 | 2008-06-04 09:18:41 +0000 | [diff] [blame] | 34 | |
Jakob Stoklund Olesen | 2d17293 | 2010-10-26 00:11:33 +0000 | [diff] [blame] | 35 | char &llvm::LiveStacksID = LiveStacks::ID; |
| 36 | |
Evan Cheng | 3f32d65 | 2008-06-04 09:18:41 +0000 | [diff] [blame] | 37 | void LiveStacks::getAnalysisUsage(AnalysisUsage &AU) const { |
Evan Cheng | ef901c5 | 2008-09-22 22:26:15 +0000 | [diff] [blame] | 38 | AU.setPreservesAll(); |
Lang Hames | 233a60e | 2009-11-03 23:52:08 +0000 | [diff] [blame] | 39 | AU.addPreserved<SlotIndexes>(); |
| 40 | AU.addRequiredTransitive<SlotIndexes>(); |
Evan Cheng | bbeeb2a | 2008-09-22 20:58:04 +0000 | [diff] [blame] | 41 | MachineFunctionPass::getAnalysisUsage(AU); |
Evan Cheng | 3f32d65 | 2008-06-04 09:18:41 +0000 | [diff] [blame] | 42 | } |
| 43 | |
| 44 | void LiveStacks::releaseMemory() { |
Benjamin Kramer | ce9a20b | 2010-06-26 11:30:59 +0000 | [diff] [blame] | 45 | // Release VNInfo memory regions, VNInfo objects don't need to be dtor'd. |
| 46 | VNInfoAllocator.Reset(); |
Evan Cheng | c781a24 | 2009-05-03 18:32:42 +0000 | [diff] [blame] | 47 | S2IMap.clear(); |
| 48 | S2RCMap.clear(); |
Evan Cheng | 3f32d65 | 2008-06-04 09:18:41 +0000 | [diff] [blame] | 49 | } |
| 50 | |
Jakob Stoklund Olesen | e27e1ca | 2011-09-30 22:18:51 +0000 | [diff] [blame] | 51 | bool LiveStacks::runOnMachineFunction(MachineFunction &MF) { |
| 52 | TRI = MF.getTarget().getRegisterInfo(); |
Evan Cheng | 3f32d65 | 2008-06-04 09:18:41 +0000 | [diff] [blame] | 53 | // FIXME: No analysis is being done right now. We are relying on the |
| 54 | // register allocators to provide the information. |
| 55 | return false; |
| 56 | } |
| 57 | |
Jakob Stoklund Olesen | be97e90 | 2011-01-09 21:17:37 +0000 | [diff] [blame] | 58 | LiveInterval & |
| 59 | LiveStacks::getOrCreateInterval(int Slot, const TargetRegisterClass *RC) { |
| 60 | assert(Slot >= 0 && "Spill slot indice must be >= 0"); |
| 61 | SS2IntervalMap::iterator I = S2IMap.find(Slot); |
| 62 | if (I == S2IMap.end()) { |
| 63 | I = S2IMap.insert(I, std::make_pair(Slot, |
| 64 | LiveInterval(TargetRegisterInfo::index2StackSlot(Slot), 0.0F))); |
| 65 | S2RCMap.insert(std::make_pair(Slot, RC)); |
| 66 | } else { |
| 67 | // Use the largest common subclass register class. |
| 68 | const TargetRegisterClass *OldRC = S2RCMap[Slot]; |
Jakob Stoklund Olesen | e27e1ca | 2011-09-30 22:18:51 +0000 | [diff] [blame] | 69 | S2RCMap[Slot] = TRI->getCommonSubClass(OldRC, RC); |
Jakob Stoklund Olesen | be97e90 | 2011-01-09 21:17:37 +0000 | [diff] [blame] | 70 | } |
| 71 | return I->second; |
| 72 | } |
| 73 | |
Evan Cheng | 3f32d65 | 2008-06-04 09:18:41 +0000 | [diff] [blame] | 74 | /// print - Implement the dump method. |
Chris Lattner | 45cfe54 | 2009-08-23 06:03:38 +0000 | [diff] [blame] | 75 | void LiveStacks::print(raw_ostream &OS, const Module*) const { |
Chris Lattner | c02497f | 2009-08-23 03:47:42 +0000 | [diff] [blame] | 76 | |
| 77 | OS << "********** INTERVALS **********\n"; |
Evan Cheng | 3f32d65 | 2008-06-04 09:18:41 +0000 | [diff] [blame] | 78 | for (const_iterator I = begin(), E = end(); I != E; ++I) { |
Chris Lattner | c02497f | 2009-08-23 03:47:42 +0000 | [diff] [blame] | 79 | I->second.print(OS); |
Evan Cheng | c781a24 | 2009-05-03 18:32:42 +0000 | [diff] [blame] | 80 | int Slot = I->first; |
| 81 | const TargetRegisterClass *RC = getIntervalRegClass(Slot); |
| 82 | if (RC) |
Chris Lattner | c02497f | 2009-08-23 03:47:42 +0000 | [diff] [blame] | 83 | OS << " [" << RC->getName() << "]\n"; |
Evan Cheng | c781a24 | 2009-05-03 18:32:42 +0000 | [diff] [blame] | 84 | else |
Chris Lattner | c02497f | 2009-08-23 03:47:42 +0000 | [diff] [blame] | 85 | OS << " [Unknown]\n"; |
Evan Cheng | 3f32d65 | 2008-06-04 09:18:41 +0000 | [diff] [blame] | 86 | } |
| 87 | } |