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Tom Stellardf98f2ce2012-12-11 21:25:42 +00001//===-- AMDGPUSubtarget.cpp - AMDGPU Subtarget Information ----------------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10/// \file
11/// \brief Implements the AMDGPU specific subclass of TargetSubtarget.
12//
13//===----------------------------------------------------------------------===//
14
15#include "AMDGPUSubtarget.h"
16
17using namespace llvm;
18
19#define GET_SUBTARGETINFO_ENUM
20#define GET_SUBTARGETINFO_TARGET_DESC
21#define GET_SUBTARGETINFO_CTOR
22#include "AMDGPUGenSubtargetInfo.inc"
23
24AMDGPUSubtarget::AMDGPUSubtarget(StringRef TT, StringRef CPU, StringRef FS) :
25 AMDGPUGenSubtargetInfo(TT, CPU, FS), DumpCode(false) {
26 InstrItins = getInstrItineraryForCPU(CPU);
27
Tom Stellardf98f2ce2012-12-11 21:25:42 +000028 // Default card
29 StringRef GPU = CPU;
30 Is64bit = false;
31 DefaultSize[0] = 64;
32 DefaultSize[1] = 1;
33 DefaultSize[2] = 1;
Vincent Lejeune631591e2013-04-30 00:13:39 +000034 HasVertexCache = false;
Tom Stellardce961472013-06-07 20:28:55 +000035 TexVTXClauseSize = 0;
Tom Stellard3ff0abf2013-06-07 20:37:48 +000036 Gen = AMDGPUSubtarget::R600;
37 FP64 = false;
38 CaymanISA = false;
Tom Stellardde28bda2013-10-10 17:11:12 +000039 EnableIRStructurizer = false;
Tom Stellardf98f2ce2012-12-11 21:25:42 +000040 ParseSubtargetFeatures(GPU, FS);
41 DevName = GPU;
Tom Stellardf98f2ce2012-12-11 21:25:42 +000042}
43
Tom Stellardf98f2ce2012-12-11 21:25:42 +000044bool
45AMDGPUSubtarget::is64bit() const {
46 return Is64bit;
47}
48bool
Vincent Lejeune631591e2013-04-30 00:13:39 +000049AMDGPUSubtarget::hasVertexCache() const {
50 return HasVertexCache;
51}
Vincent Lejeunedcfcf1d2013-05-17 16:49:55 +000052short
53AMDGPUSubtarget::getTexVTXClauseSize() const {
54 return TexVTXClauseSize;
55}
Tom Stellard3ff0abf2013-06-07 20:37:48 +000056enum AMDGPUSubtarget::Generation
57AMDGPUSubtarget::getGeneration() const {
58 return Gen;
59}
60bool
61AMDGPUSubtarget::hasHWFP64() const {
62 return FP64;
63}
64bool
65AMDGPUSubtarget::hasCaymanISA() const {
66 return CaymanISA;
67}
Vincent Lejeune631591e2013-04-30 00:13:39 +000068bool
Tom Stellardde28bda2013-10-10 17:11:12 +000069AMDGPUSubtarget::IsIRStructurizerEnabled() const {
70 return EnableIRStructurizer;
71}
72bool
Tom Stellardf98f2ce2012-12-11 21:25:42 +000073AMDGPUSubtarget::isTargetELF() const {
74 return false;
75}
76size_t
77AMDGPUSubtarget::getDefaultSize(uint32_t dim) const {
78 if (dim > 3) {
79 return 1;
80 } else {
81 return DefaultSize[dim];
82 }
83}
84
85std::string
86AMDGPUSubtarget::getDataLayout() const {
Tom Stellard3ff0abf2013-06-07 20:37:48 +000087 std::string DataLayout = std::string(
88 "e"
89 "-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32"
90 "-v16:16:16-v24:32:32-v32:32:32-v48:64:64-v64:64:64-v96:128:128-v128:128:128"
91 "-v192:256:256-v256:256:256-v512:512:512-v1024:1024:1024-v2048:2048:2048"
92 "-n32:64"
93 );
94
95 if (hasHWFP64()) {
96 DataLayout.append("-f64:64:64");
97 }
98
99 if (is64bit()) {
100 DataLayout.append("-p:64:64:64");
101 } else {
102 DataLayout.append("-p:32:32:32");
103 }
104
Tom Stellardda25cd32013-08-26 15:05:36 +0000105 if (Gen >= AMDGPUSubtarget::SOUTHERN_ISLANDS) {
106 DataLayout.append("-p3:32:32:32");
107 }
108
Tom Stellard3ff0abf2013-06-07 20:37:48 +0000109 return DataLayout;
Tom Stellardf98f2ce2012-12-11 21:25:42 +0000110}
111
112std::string
113AMDGPUSubtarget::getDeviceName() const {
114 return DevName;
115}