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Shih-wei Liaoe264f622010-02-10 11:10:31 -08001//===-- PPCCodeEmitter.cpp - JIT Code Emitter for PowerPC32 -------*- C++ -*-=//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the PowerPC 32-bit CodeEmitter and associated machinery to
11// JIT-compile bitcode to native PowerPC.
12//
13//===----------------------------------------------------------------------===//
14
15#include "PPCTargetMachine.h"
16#include "PPCRelocations.h"
17#include "PPC.h"
18#include "llvm/Module.h"
19#include "llvm/PassManager.h"
20#include "llvm/CodeGen/JITCodeEmitter.h"
21#include "llvm/CodeGen/MachineFunctionPass.h"
22#include "llvm/CodeGen/MachineInstrBuilder.h"
23#include "llvm/CodeGen/MachineModuleInfo.h"
24#include "llvm/Support/ErrorHandling.h"
25#include "llvm/Support/raw_ostream.h"
26#include "llvm/Target/TargetOptions.h"
27using namespace llvm;
28
29namespace {
30 class PPCCodeEmitter : public MachineFunctionPass {
31 TargetMachine &TM;
32 JITCodeEmitter &MCE;
33
34 void getAnalysisUsage(AnalysisUsage &AU) const {
35 AU.addRequired<MachineModuleInfo>();
36 MachineFunctionPass::getAnalysisUsage(AU);
37 }
38
39 static char ID;
40
41 /// MovePCtoLROffset - When/if we see a MovePCtoLR instruction, we record
42 /// its address in the function into this pointer.
43 void *MovePCtoLROffset;
44 public:
45
46 PPCCodeEmitter(TargetMachine &tm, JITCodeEmitter &mce)
47 : MachineFunctionPass(&ID), TM(tm), MCE(mce) {}
48
49 /// getBinaryCodeForInstr - This function, generated by the
50 /// CodeEmitterGenerator using TableGen, produces the binary encoding for
51 /// machine instructions.
52
53 unsigned getBinaryCodeForInstr(const MachineInstr &MI);
54
55 /// getMachineOpValue - evaluates the MachineOperand of a given MachineInstr
56
57 unsigned getMachineOpValue(const MachineInstr &MI,
58 const MachineOperand &MO);
59
60 const char *getPassName() const { return "PowerPC Machine Code Emitter"; }
61
62 /// runOnMachineFunction - emits the given MachineFunction to memory
63 ///
64 bool runOnMachineFunction(MachineFunction &MF);
65
66 /// emitBasicBlock - emits the given MachineBasicBlock to memory
67 ///
68 void emitBasicBlock(MachineBasicBlock &MBB);
69
70 /// getValueBit - return the particular bit of Val
71 ///
72 unsigned getValueBit(int64_t Val, unsigned bit) { return (Val >> bit) & 1; }
73 };
74}
75
76char PPCCodeEmitter::ID = 0;
77
78/// createPPCCodeEmitterPass - Return a pass that emits the collected PPC code
79/// to the specified MCE object.
80FunctionPass *llvm::createPPCJITCodeEmitterPass(PPCTargetMachine &TM,
81 JITCodeEmitter &JCE) {
82 return new PPCCodeEmitter(TM, JCE);
83}
84
85bool PPCCodeEmitter::runOnMachineFunction(MachineFunction &MF) {
86 assert((MF.getTarget().getRelocationModel() != Reloc::Default ||
87 MF.getTarget().getRelocationModel() != Reloc::Static) &&
88 "JIT relocation model must be set to static or default!");
89
90 MCE.setModuleInfo(&getAnalysis<MachineModuleInfo>());
91 do {
92 MovePCtoLROffset = 0;
93 MCE.startFunction(MF);
94 for (MachineFunction::iterator BB = MF.begin(), E = MF.end(); BB != E; ++BB)
95 emitBasicBlock(*BB);
96 } while (MCE.finishFunction(MF));
97
98 return false;
99}
100
101void PPCCodeEmitter::emitBasicBlock(MachineBasicBlock &MBB) {
102 MCE.StartMachineBasicBlock(&MBB);
103
104 for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end(); I != E; ++I){
105 const MachineInstr &MI = *I;
106 MCE.processDebugLoc(MI.getDebugLoc(), true);
107 switch (MI.getOpcode()) {
108 default:
109 MCE.emitWordBE(getBinaryCodeForInstr(MI));
110 break;
111 case TargetOpcode::DBG_LABEL:
112 case TargetOpcode::EH_LABEL:
113 MCE.emitLabel(MI.getOperand(0).getImm());
114 break;
115 case TargetOpcode::IMPLICIT_DEF:
116 case TargetOpcode::KILL:
117 break; // pseudo opcode, no side effects
118 case PPC::MovePCtoLR:
119 case PPC::MovePCtoLR8:
120 assert(TM.getRelocationModel() == Reloc::PIC_);
121 MovePCtoLROffset = (void*)MCE.getCurrentPCValue();
122 MCE.emitWordBE(0x48000005); // bl 1
123 break;
124 }
125 MCE.processDebugLoc(MI.getDebugLoc(), false);
126 }
127}
128
129unsigned PPCCodeEmitter::getMachineOpValue(const MachineInstr &MI,
130 const MachineOperand &MO) {
131
132 unsigned rv = 0; // Return value; defaults to 0 for unhandled cases
133 // or things that get fixed up later by the JIT.
134 if (MO.isReg()) {
135 rv = PPCRegisterInfo::getRegisterNumbering(MO.getReg());
136
137 // Special encoding for MTCRF and MFOCRF, which uses a bit mask for the
138 // register, not the register number directly.
139 if ((MI.getOpcode() == PPC::MTCRF || MI.getOpcode() == PPC::MFOCRF) &&
140 (MO.getReg() >= PPC::CR0 && MO.getReg() <= PPC::CR7)) {
141 rv = 0x80 >> rv;
142 }
143 } else if (MO.isImm()) {
144 rv = MO.getImm();
145 } else if (MO.isGlobal() || MO.isSymbol() ||
146 MO.isCPI() || MO.isJTI()) {
147 unsigned Reloc = 0;
148 if (MI.getOpcode() == PPC::BL_Darwin || MI.getOpcode() == PPC::BL8_Darwin ||
149 MI.getOpcode() == PPC::BL_SVR4 || MI.getOpcode() == PPC::BL8_ELF ||
150 MI.getOpcode() == PPC::TAILB || MI.getOpcode() == PPC::TAILB8)
151 Reloc = PPC::reloc_pcrel_bx;
152 else {
153 if (TM.getRelocationModel() == Reloc::PIC_) {
154 assert(MovePCtoLROffset && "MovePCtoLR not seen yet?");
155 }
156 switch (MI.getOpcode()) {
157 default: MI.dump(); llvm_unreachable("Unknown instruction for relocation!");
158 case PPC::LIS:
159 case PPC::LIS8:
160 case PPC::ADDIS:
161 case PPC::ADDIS8:
162 Reloc = PPC::reloc_absolute_high; // Pointer to symbol
163 break;
164 case PPC::LI:
165 case PPC::LI8:
166 case PPC::LA:
167 // Loads.
168 case PPC::LBZ:
169 case PPC::LBZ8:
170 case PPC::LHA:
171 case PPC::LHA8:
172 case PPC::LHZ:
173 case PPC::LHZ8:
174 case PPC::LWZ:
175 case PPC::LWZ8:
176 case PPC::LFS:
177 case PPC::LFD:
178
179 // Stores.
180 case PPC::STB:
181 case PPC::STB8:
182 case PPC::STH:
183 case PPC::STH8:
184 case PPC::STW:
185 case PPC::STW8:
186 case PPC::STFS:
187 case PPC::STFD:
188 Reloc = PPC::reloc_absolute_low;
189 break;
190
191 case PPC::LWA:
192 case PPC::LD:
193 case PPC::STD:
194 case PPC::STD_32:
195 Reloc = PPC::reloc_absolute_low_ix;
196 break;
197 }
198 }
199
200 MachineRelocation R;
201 if (MO.isGlobal()) {
202 R = MachineRelocation::getGV(MCE.getCurrentPCOffset(), Reloc,
203 MO.getGlobal(), 0,
204 isa<Function>(MO.getGlobal()));
205 } else if (MO.isSymbol()) {
206 R = MachineRelocation::getExtSym(MCE.getCurrentPCOffset(),
207 Reloc, MO.getSymbolName(), 0);
208 } else if (MO.isCPI()) {
209 R = MachineRelocation::getConstPool(MCE.getCurrentPCOffset(),
210 Reloc, MO.getIndex(), 0);
211 } else {
212 assert(MO.isJTI());
213 R = MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(),
214 Reloc, MO.getIndex(), 0);
215 }
216
217 // If in PIC mode, we need to encode the negated address of the
218 // 'movepctolr' into the unrelocated field. After relocation, we'll have
219 // &gv-&movepctolr-4 in the imm field. Once &movepctolr is added to the imm
220 // field, we get &gv. This doesn't happen for branch relocations, which are
221 // always implicitly pc relative.
222 if (TM.getRelocationModel() == Reloc::PIC_ && Reloc != PPC::reloc_pcrel_bx){
223 assert(MovePCtoLROffset && "MovePCtoLR not seen yet?");
224 R.setConstantVal(-(intptr_t)MovePCtoLROffset - 4);
225 }
226 MCE.addRelocation(R);
227
228 } else if (MO.isMBB()) {
229 unsigned Reloc = 0;
230 unsigned Opcode = MI.getOpcode();
231 if (Opcode == PPC::B || Opcode == PPC::BL_Darwin ||
232 Opcode == PPC::BLA_Darwin|| Opcode == PPC::BL_SVR4 ||
233 Opcode == PPC::BLA_SVR4)
234 Reloc = PPC::reloc_pcrel_bx;
235 else // BCC instruction
236 Reloc = PPC::reloc_pcrel_bcx;
237
238 MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(),
239 Reloc, MO.getMBB()));
240 } else {
241#ifndef NDEBUG
242 errs() << "ERROR: Unknown type of MachineOperand: " << MO << "\n";
243#endif
244 llvm_unreachable(0);
245 }
246
247 return rv;
248}
249
250#include "PPCGenCodeEmitter.inc"