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Jia Liubb481f82012-02-28 07:46:26 +00001//===-- MipsISelLowering.cpp - Mips DAG Lowering Implementation -----------===//
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002//
3// The LLVM Compiler Infrastructure
4//
Chris Lattner4ee451d2007-12-29 20:36:04 +00005// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00007//
Akira Hatanaka4552c9a2011-04-15 21:51:11 +00008//===----------------------------------------------------------------------===//
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00009//
10// This file defines the interfaces that Mips uses to lower LLVM code into a
11// selection DAG.
12//
Akira Hatanaka4552c9a2011-04-15 21:51:11 +000013//===----------------------------------------------------------------------===//
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +000014
15#define DEBUG_TYPE "mips-lower"
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +000016#include "MipsISelLowering.h"
Bruno Cardoso Lopesa2b1bb52007-08-28 05:08:16 +000017#include "MipsMachineFunction.h"
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +000018#include "MipsTargetMachine.h"
Chris Lattnerb71b9092009-08-13 06:28:06 +000019#include "MipsTargetObjectFile.h"
Bruno Cardoso Lopes225ca9c2008-07-05 19:05:21 +000020#include "MipsSubtarget.h"
Craig Topper79aa3412012-03-17 18:46:09 +000021#include "InstPrinter/MipsInstPrinter.h"
22#include "MCTargetDesc/MipsBaseInfo.h"
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +000023#include "llvm/DerivedTypes.h"
24#include "llvm/Function.h"
Bruno Cardoso Lopes91fd5322008-07-21 18:52:34 +000025#include "llvm/GlobalVariable.h"
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +000026#include "llvm/Intrinsics.h"
27#include "llvm/CallingConv.h"
28#include "llvm/CodeGen/CallingConvLower.h"
29#include "llvm/CodeGen/MachineFrameInfo.h"
30#include "llvm/CodeGen/MachineFunction.h"
31#include "llvm/CodeGen/MachineInstrBuilder.h"
Chris Lattner84bc5422007-12-31 04:13:23 +000032#include "llvm/CodeGen/MachineRegisterInfo.h"
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +000033#include "llvm/CodeGen/SelectionDAGISel.h"
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +000034#include "llvm/CodeGen/ValueTypes.h"
35#include "llvm/Support/Debug.h"
Torok Edwinc25e7582009-07-11 20:10:48 +000036#include "llvm/Support/ErrorHandling.h"
NAKAMURA Takumi89593932012-04-21 15:31:45 +000037#include "llvm/Support/raw_ostream.h"
38
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +000039using namespace llvm;
40
Jia Liubb481f82012-02-28 07:46:26 +000041// If I is a shifted mask, set the size (Size) and the first bit of the
Akira Hatanakadbe9a312011-08-18 20:07:42 +000042// mask (Pos), and return true.
Jia Liubb481f82012-02-28 07:46:26 +000043// For example, if I is 0x003ff800, (Pos, Size) = (11, 11).
Akira Hatanaka854a7db2011-08-19 22:59:00 +000044static bool IsShiftedMask(uint64_t I, uint64_t &Pos, uint64_t &Size) {
Akira Hatanakad6bc5232011-12-05 21:26:34 +000045 if (!isShiftedMask_64(I))
Akira Hatanaka854a7db2011-08-19 22:59:00 +000046 return false;
Akira Hatanakabb15e112011-08-17 02:05:42 +000047
Akira Hatanakad6bc5232011-12-05 21:26:34 +000048 Size = CountPopulation_64(I);
49 Pos = CountTrailingZeros_64(I);
Akira Hatanakadbe9a312011-08-18 20:07:42 +000050 return true;
Akira Hatanakabb15e112011-08-17 02:05:42 +000051}
52
Akira Hatanaka648f00c2012-02-24 22:34:47 +000053static SDValue GetGlobalReg(SelectionDAG &DAG, EVT Ty) {
54 MipsFunctionInfo *FI = DAG.getMachineFunction().getInfo<MipsFunctionInfo>();
55 return DAG.getRegister(FI->getGlobalBaseReg(), Ty);
56}
57
Chris Lattnerf0144122009-07-28 03:13:23 +000058const char *MipsTargetLowering::getTargetNodeName(unsigned Opcode) const {
59 switch (Opcode) {
Akira Hatanakabdd2ce92011-05-23 21:13:59 +000060 case MipsISD::JmpLink: return "MipsISD::JmpLink";
61 case MipsISD::Hi: return "MipsISD::Hi";
62 case MipsISD::Lo: return "MipsISD::Lo";
63 case MipsISD::GPRel: return "MipsISD::GPRel";
Bruno Cardoso Lopesd9796862011-05-31 02:53:58 +000064 case MipsISD::ThreadPointer: return "MipsISD::ThreadPointer";
Akira Hatanakabdd2ce92011-05-23 21:13:59 +000065 case MipsISD::Ret: return "MipsISD::Ret";
66 case MipsISD::FPBrcond: return "MipsISD::FPBrcond";
67 case MipsISD::FPCmp: return "MipsISD::FPCmp";
68 case MipsISD::CMovFP_T: return "MipsISD::CMovFP_T";
69 case MipsISD::CMovFP_F: return "MipsISD::CMovFP_F";
70 case MipsISD::FPRound: return "MipsISD::FPRound";
71 case MipsISD::MAdd: return "MipsISD::MAdd";
72 case MipsISD::MAddu: return "MipsISD::MAddu";
73 case MipsISD::MSub: return "MipsISD::MSub";
74 case MipsISD::MSubu: return "MipsISD::MSubu";
75 case MipsISD::DivRem: return "MipsISD::DivRem";
76 case MipsISD::DivRemU: return "MipsISD::DivRemU";
77 case MipsISD::BuildPairF64: return "MipsISD::BuildPairF64";
78 case MipsISD::ExtractElementF64: return "MipsISD::ExtractElementF64";
Akira Hatanakabfcb83f2011-12-12 22:38:19 +000079 case MipsISD::Wrapper: return "MipsISD::Wrapper";
Akira Hatanaka21afc632011-06-21 00:40:49 +000080 case MipsISD::DynAlloc: return "MipsISD::DynAlloc";
Akira Hatanakadb548262011-07-19 23:30:50 +000081 case MipsISD::Sync: return "MipsISD::Sync";
Akira Hatanakabb15e112011-08-17 02:05:42 +000082 case MipsISD::Ext: return "MipsISD::Ext";
83 case MipsISD::Ins: return "MipsISD::Ins";
Akira Hatanakab6f1dc22012-06-02 00:03:12 +000084 case MipsISD::LWL: return "MipsISD::LWL";
85 case MipsISD::LWR: return "MipsISD::LWR";
86 case MipsISD::SWL: return "MipsISD::SWL";
87 case MipsISD::SWR: return "MipsISD::SWR";
88 case MipsISD::LDL: return "MipsISD::LDL";
89 case MipsISD::LDR: return "MipsISD::LDR";
90 case MipsISD::SDL: return "MipsISD::SDL";
91 case MipsISD::SDR: return "MipsISD::SDR";
Akira Hatanaka0f843822011-06-07 18:58:42 +000092 default: return NULL;
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +000093 }
94}
95
96MipsTargetLowering::
Chris Lattnerf0144122009-07-28 03:13:23 +000097MipsTargetLowering(MipsTargetMachine &TM)
Akira Hatanaka8b4198d2011-09-26 21:47:02 +000098 : TargetLowering(TM, new MipsTargetObjectFile()),
99 Subtarget(&TM.getSubtarget<MipsSubtarget>()),
Akira Hatanaka2ec69fa2011-10-28 18:47:24 +0000100 HasMips64(Subtarget->hasMips64()), IsN64(Subtarget->isABI_N64()),
101 IsO32(Subtarget->isABI_O32()) {
Bruno Cardoso Lopes225ca9c2008-07-05 19:05:21 +0000102
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +0000103 // Mips does not have i1 type, so use i32 for
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000104 // setcc operations results (slt, sgt, ...).
Duncan Sands03228082008-11-23 15:47:28 +0000105 setBooleanContents(ZeroOrOneBooleanContent);
Duncan Sands28b77e92011-09-06 19:07:46 +0000106 setBooleanVectorContents(ZeroOrOneBooleanContent); // FIXME: Is this correct?
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +0000107
108 // Set up the register classes
Craig Topper420761a2012-04-20 07:30:17 +0000109 addRegisterClass(MVT::i32, &Mips::CPURegsRegClass);
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +0000110
Akira Hatanaka95934842011-09-24 01:34:44 +0000111 if (HasMips64)
Craig Topper420761a2012-04-20 07:30:17 +0000112 addRegisterClass(MVT::i64, &Mips::CPU64RegsRegClass);
Akira Hatanaka95934842011-09-24 01:34:44 +0000113
Akira Hatanaka28ee4fd2012-05-31 02:59:44 +0000114 if (Subtarget->inMips16Mode()) {
115 addRegisterClass(MVT::i32, &Mips::CPU16RegsRegClass);
116 addRegisterClass(MVT::i32, &Mips::CPURARegRegClass);
117 }
118
Akira Hatanakab0e7af72012-01-04 19:29:11 +0000119 if (!TM.Options.UseSoftFloat) {
Craig Topper420761a2012-04-20 07:30:17 +0000120 addRegisterClass(MVT::f32, &Mips::FGR32RegClass);
Akira Hatanakab0e7af72012-01-04 19:29:11 +0000121
122 // When dealing with single precision only, use libcalls
123 if (!Subtarget->isSingleFloat()) {
124 if (HasMips64)
Craig Topper420761a2012-04-20 07:30:17 +0000125 addRegisterClass(MVT::f64, &Mips::FGR64RegClass);
Akira Hatanakab0e7af72012-01-04 19:29:11 +0000126 else
Craig Topper420761a2012-04-20 07:30:17 +0000127 addRegisterClass(MVT::f64, &Mips::AFGR64RegClass);
Akira Hatanakab0e7af72012-01-04 19:29:11 +0000128 }
Akira Hatanaka792016b2011-09-23 18:28:39 +0000129 }
Bruno Cardoso Lopes225ca9c2008-07-05 19:05:21 +0000130
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000131 // Load extented operations for i1 types must be promoted
Owen Anderson825b72b2009-08-11 20:47:22 +0000132 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
133 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
134 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +0000135
Eli Friedman6055a6a2009-07-17 04:07:24 +0000136 // MIPS doesn't have extending float->double load/store
Owen Anderson825b72b2009-08-11 20:47:22 +0000137 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
138 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
Eli Friedman10a36592009-07-17 02:28:12 +0000139
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000140 // Used by legalize types to correctly generate the setcc result.
141 // Without this, every float setcc comes with a AND/OR with the result,
142 // we don't want this, since the fpcmp result goes to a flag register,
Bruno Cardoso Lopes77283772008-07-31 18:31:28 +0000143 // which is used implicitly by brcond and select operations.
Owen Anderson825b72b2009-08-11 20:47:22 +0000144 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32);
Bruno Cardoso Lopes77283772008-07-31 18:31:28 +0000145
Bruno Cardoso Lopes97c25372008-07-09 04:15:08 +0000146 // Mips Custom Operations
Owen Anderson825b72b2009-08-11 20:47:22 +0000147 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
Bruno Cardoso Lopesca8a2aa2011-03-04 20:01:52 +0000148 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
Owen Anderson825b72b2009-08-11 20:47:22 +0000149 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
150 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
151 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
152 setOperationAction(ISD::SELECT, MVT::f32, Custom);
153 setOperationAction(ISD::SELECT, MVT::f64, Custom);
154 setOperationAction(ISD::SELECT, MVT::i32, Custom);
Akira Hatanaka3fef29d2012-07-11 19:32:27 +0000155 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
156 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
Akira Hatanaka0a40c232012-03-09 23:46:03 +0000157 setOperationAction(ISD::SETCC, MVT::f32, Custom);
158 setOperationAction(ISD::SETCC, MVT::f64, Custom);
Owen Anderson825b72b2009-08-11 20:47:22 +0000159 setOperationAction(ISD::BRCOND, MVT::Other, Custom);
160 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
Bruno Cardoso Lopes6059b852010-02-06 21:00:02 +0000161 setOperationAction(ISD::VASTART, MVT::Other, Custom);
Akira Hatanakad229b7b2012-03-10 00:03:50 +0000162 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
163 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
164 setOperationAction(ISD::MEMBARRIER, MVT::Other, Custom);
165 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom);
Akira Hatanaka7664f052012-06-02 00:04:42 +0000166 setOperationAction(ISD::LOAD, MVT::i32, Custom);
167 setOperationAction(ISD::STORE, MVT::i32, Custom);
Akira Hatanakad229b7b2012-03-10 00:03:50 +0000168
Akira Hatanakac12a6e62012-04-11 22:49:04 +0000169 if (!TM.Options.NoNaNsFPMath) {
170 setOperationAction(ISD::FABS, MVT::f32, Custom);
171 setOperationAction(ISD::FABS, MVT::f64, Custom);
172 }
173
Akira Hatanakad229b7b2012-03-10 00:03:50 +0000174 if (HasMips64) {
175 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
176 setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
177 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
178 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
179 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
180 setOperationAction(ISD::SELECT, MVT::i64, Custom);
181 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Custom);
Akira Hatanaka7664f052012-06-02 00:04:42 +0000182 setOperationAction(ISD::LOAD, MVT::i64, Custom);
183 setOperationAction(ISD::STORE, MVT::i64, Custom);
Akira Hatanakad229b7b2012-03-10 00:03:50 +0000184 }
Bruno Cardoso Lopes6059b852010-02-06 21:00:02 +0000185
Akira Hatanakaa284acb2012-05-09 00:55:21 +0000186 if (!HasMips64) {
187 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
188 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
189 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
190 }
191
Bruno Cardoso Lopes38b5e862011-03-04 21:03:24 +0000192 setOperationAction(ISD::SDIV, MVT::i32, Expand);
193 setOperationAction(ISD::SREM, MVT::i32, Expand);
194 setOperationAction(ISD::UDIV, MVT::i32, Expand);
195 setOperationAction(ISD::UREM, MVT::i32, Expand);
Akira Hatanakadda4a072011-10-03 21:06:13 +0000196 setOperationAction(ISD::SDIV, MVT::i64, Expand);
197 setOperationAction(ISD::SREM, MVT::i64, Expand);
198 setOperationAction(ISD::UDIV, MVT::i64, Expand);
199 setOperationAction(ISD::UREM, MVT::i64, Expand);
Bruno Cardoso Lopes38b5e862011-03-04 21:03:24 +0000200
Bruno Cardoso Lopes97c25372008-07-09 04:15:08 +0000201 // Operations not directly supported by Mips.
Owen Anderson825b72b2009-08-11 20:47:22 +0000202 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
203 setOperationAction(ISD::BR_CC, MVT::Other, Expand);
204 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
205 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
Akira Hatanakae1bcd6b2011-12-20 23:40:56 +0000206 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
Owen Anderson825b72b2009-08-11 20:47:22 +0000207 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
Akira Hatanakae1bcd6b2011-12-20 23:40:56 +0000208 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
Owen Anderson825b72b2009-08-11 20:47:22 +0000209 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
210 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
Akira Hatanaka7f162742011-12-21 00:14:05 +0000211 setOperationAction(ISD::CTPOP, MVT::i64, Expand);
Owen Anderson825b72b2009-08-11 20:47:22 +0000212 setOperationAction(ISD::CTTZ, MVT::i32, Expand);
Akira Hatanaka7f162742011-12-21 00:14:05 +0000213 setOperationAction(ISD::CTTZ, MVT::i64, Expand);
Chandler Carruth63974b22011-12-13 01:56:10 +0000214 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
215 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
216 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
217 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
Owen Anderson825b72b2009-08-11 20:47:22 +0000218 setOperationAction(ISD::ROTL, MVT::i32, Expand);
Akira Hatanakac7bafe92011-09-30 18:51:46 +0000219 setOperationAction(ISD::ROTL, MVT::i64, Expand);
Bruno Cardoso Lopes908b6dd2010-12-09 17:32:30 +0000220
Akira Hatanaka56633442011-09-20 23:53:09 +0000221 if (!Subtarget->hasMips32r2())
Bruno Cardoso Lopes908b6dd2010-12-09 17:32:30 +0000222 setOperationAction(ISD::ROTR, MVT::i32, Expand);
223
Akira Hatanakac7bafe92011-09-30 18:51:46 +0000224 if (!Subtarget->hasMips64r2())
225 setOperationAction(ISD::ROTR, MVT::i64, Expand);
226
Owen Anderson825b72b2009-08-11 20:47:22 +0000227 setOperationAction(ISD::FSIN, MVT::f32, Expand);
Bruno Cardoso Lopes5d6fb5d2011-03-04 18:54:14 +0000228 setOperationAction(ISD::FSIN, MVT::f64, Expand);
Owen Anderson825b72b2009-08-11 20:47:22 +0000229 setOperationAction(ISD::FCOS, MVT::f32, Expand);
Bruno Cardoso Lopes5d6fb5d2011-03-04 18:54:14 +0000230 setOperationAction(ISD::FCOS, MVT::f64, Expand);
Owen Anderson825b72b2009-08-11 20:47:22 +0000231 setOperationAction(ISD::FPOWI, MVT::f32, Expand);
232 setOperationAction(ISD::FPOW, MVT::f32, Expand);
Akira Hatanaka46da1362011-05-23 22:23:58 +0000233 setOperationAction(ISD::FPOW, MVT::f64, Expand);
Owen Anderson825b72b2009-08-11 20:47:22 +0000234 setOperationAction(ISD::FLOG, MVT::f32, Expand);
235 setOperationAction(ISD::FLOG2, MVT::f32, Expand);
236 setOperationAction(ISD::FLOG10, MVT::f32, Expand);
237 setOperationAction(ISD::FEXP, MVT::f32, Expand);
Cameron Zwarich33390842011-07-08 21:39:21 +0000238 setOperationAction(ISD::FMA, MVT::f32, Expand);
239 setOperationAction(ISD::FMA, MVT::f64, Expand);
Akira Hatanaka21ecc2f2012-03-29 18:43:11 +0000240 setOperationAction(ISD::FREM, MVT::f32, Expand);
241 setOperationAction(ISD::FREM, MVT::f64, Expand);
Bruno Cardoso Lopes97c25372008-07-09 04:15:08 +0000242
Akira Hatanaka1cc63332012-04-11 22:59:08 +0000243 if (!TM.Options.NoNaNsFPMath) {
244 setOperationAction(ISD::FNEG, MVT::f32, Expand);
245 setOperationAction(ISD::FNEG, MVT::f64, Expand);
246 }
247
Akira Hatanakacf0cd802011-05-26 18:59:03 +0000248 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
Akira Hatanaka590baca2012-02-02 03:13:40 +0000249 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
Akira Hatanakacf0cd802011-05-26 18:59:03 +0000250 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
Akira Hatanaka590baca2012-02-02 03:13:40 +0000251 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
Eric Christopher471e4222011-06-08 23:55:35 +0000252
Bruno Cardoso Lopes954dac02011-03-09 19:22:22 +0000253 setOperationAction(ISD::VAARG, MVT::Other, Expand);
254 setOperationAction(ISD::VACOPY, MVT::Other, Expand);
255 setOperationAction(ISD::VAEND, MVT::Other, Expand);
256
Bruno Cardoso Lopes97c25372008-07-09 04:15:08 +0000257 // Use the default for now
Owen Anderson825b72b2009-08-11 20:47:22 +0000258 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
259 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
Eli Friedman14648462011-07-27 22:21:52 +0000260
Jia Liubb481f82012-02-28 07:46:26 +0000261 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Expand);
262 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand);
263 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Expand);
264 setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand);
Eli Friedman4db5aca2011-08-29 18:23:02 +0000265
Eli Friedman26689ac2011-08-03 21:06:02 +0000266 setInsertFencesForAtomic(true);
267
Bruno Cardoso Lopes7728f7e2008-07-09 05:32:22 +0000268 if (!Subtarget->hasSEInReg()) {
Owen Anderson825b72b2009-08-11 20:47:22 +0000269 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
270 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
Bruno Cardoso Lopes225ca9c2008-07-05 19:05:21 +0000271 }
272
Akira Hatanakac79507a2011-12-21 00:20:27 +0000273 if (!Subtarget->hasBitCount()) {
Owen Anderson825b72b2009-08-11 20:47:22 +0000274 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
Akira Hatanakac79507a2011-12-21 00:20:27 +0000275 setOperationAction(ISD::CTLZ, MVT::i64, Expand);
276 }
Bruno Cardoso Lopes65ad4522008-08-08 06:16:31 +0000277
Akira Hatanakac0ea0432011-12-20 23:56:43 +0000278 if (!Subtarget->hasSwap()) {
Owen Anderson825b72b2009-08-11 20:47:22 +0000279 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
Akira Hatanakac0ea0432011-12-20 23:56:43 +0000280 setOperationAction(ISD::BSWAP, MVT::i64, Expand);
281 }
Bruno Cardoso Lopes739e4412008-08-13 07:13:40 +0000282
Akira Hatanaka7664f052012-06-02 00:04:42 +0000283 if (HasMips64) {
284 setLoadExtAction(ISD::SEXTLOAD, MVT::i32, Custom);
285 setLoadExtAction(ISD::ZEXTLOAD, MVT::i32, Custom);
286 setLoadExtAction(ISD::EXTLOAD, MVT::i32, Custom);
287 setTruncStoreAction(MVT::i64, MVT::i32, Custom);
288 }
289
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000290 setTargetDAGCombine(ISD::ADDE);
291 setTargetDAGCombine(ISD::SUBE);
Bruno Cardoso Lopes38b5e862011-03-04 21:03:24 +0000292 setTargetDAGCombine(ISD::SDIVREM);
293 setTargetDAGCombine(ISD::UDIVREM);
Akira Hatanakaee8c3b02012-03-08 03:26:37 +0000294 setTargetDAGCombine(ISD::SELECT);
Akira Hatanaka77b85b62011-08-17 17:45:08 +0000295 setTargetDAGCombine(ISD::AND);
296 setTargetDAGCombine(ISD::OR);
Akira Hatanaka87827072012-06-13 20:33:18 +0000297 setTargetDAGCombine(ISD::ADD);
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000298
Akira Hatanaka5fdf5002012-03-08 01:59:33 +0000299 setMinFunctionAlignment(HasMips64 ? 3 : 2);
Eli Friedmanfc5d3052011-05-06 20:34:06 +0000300
Akira Hatanaka3f5b1072012-02-02 03:17:04 +0000301 setStackPointerRegisterToSaveRestore(IsN64 ? Mips::SP_64 : Mips::SP);
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +0000302 computeRegisterProperties();
Akira Hatanakacf0cd802011-05-26 18:59:03 +0000303
Akira Hatanaka590baca2012-02-02 03:13:40 +0000304 setExceptionPointerRegister(IsN64 ? Mips::A0_64 : Mips::A0);
305 setExceptionSelectorRegister(IsN64 ? Mips::A1_64 : Mips::A1);
Akira Hatanakae193b322012-06-13 19:33:32 +0000306
307 maxStoresPerMemcpy = 16;
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +0000308}
309
Akira Hatanaka5c21c9e2011-08-12 21:30:06 +0000310bool MipsTargetLowering::allowsUnalignedMemoryAccesses(EVT VT) const {
Akira Hatanaka511961a2011-08-17 18:49:18 +0000311 MVT::SimpleValueType SVT = VT.getSimpleVT().SimpleTy;
Jia Liubb481f82012-02-28 07:46:26 +0000312
Akira Hatanaka44b6c712012-02-28 02:55:02 +0000313 switch (SVT) {
314 case MVT::i64:
315 case MVT::i32:
Akira Hatanaka44b6c712012-02-28 02:55:02 +0000316 return true;
Akira Hatanaka44b6c712012-02-28 02:55:02 +0000317 default:
318 return false;
319 }
Akira Hatanaka5c21c9e2011-08-12 21:30:06 +0000320}
321
Duncan Sands28b77e92011-09-06 19:07:46 +0000322EVT MipsTargetLowering::getSetCCResultType(EVT VT) const {
Owen Anderson825b72b2009-08-11 20:47:22 +0000323 return MVT::i32;
Scott Michel5b8f82e2008-03-10 15:42:14 +0000324}
325
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000326// SelectMadd -
327// Transforms a subgraph in CurDAG if the following pattern is found:
328// (addc multLo, Lo0), (adde multHi, Hi0),
329// where,
330// multHi/Lo: product of multiplication
Bruno Cardoso Lopes8e826e62011-02-10 18:05:10 +0000331// Lo0: initial value of Lo register
332// Hi0: initial value of Hi register
Akira Hatanaka81bd78b2011-03-30 21:15:35 +0000333// Return true if pattern matching was successful.
Akira Hatanaka864f6602012-06-14 21:10:56 +0000334static bool SelectMadd(SDNode *ADDENode, SelectionDAG *CurDAG) {
Bruno Cardoso Lopes8e826e62011-02-10 18:05:10 +0000335 // ADDENode's second operand must be a flag output of an ADDC node in order
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000336 // for the matching to be successful.
Akira Hatanaka864f6602012-06-14 21:10:56 +0000337 SDNode *ADDCNode = ADDENode->getOperand(2).getNode();
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000338
339 if (ADDCNode->getOpcode() != ISD::ADDC)
340 return false;
341
342 SDValue MultHi = ADDENode->getOperand(0);
343 SDValue MultLo = ADDCNode->getOperand(0);
Akira Hatanaka864f6602012-06-14 21:10:56 +0000344 SDNode *MultNode = MultHi.getNode();
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000345 unsigned MultOpc = MultHi.getOpcode();
346
347 // MultHi and MultLo must be generated by the same node,
348 if (MultLo.getNode() != MultNode)
349 return false;
350
351 // and it must be a multiplication.
352 if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI)
353 return false;
Bruno Cardoso Lopes8e826e62011-02-10 18:05:10 +0000354
355 // MultLo amd MultHi must be the first and second output of MultNode
356 // respectively.
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000357 if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0)
358 return false;
359
Bruno Cardoso Lopes8e826e62011-02-10 18:05:10 +0000360 // Transform this to a MADD only if ADDENode and ADDCNode are the only users
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000361 // of the values of MultNode, in which case MultNode will be removed in later
362 // phases.
Akira Hatanaka4552c9a2011-04-15 21:51:11 +0000363 // If there exist users other than ADDENode or ADDCNode, this function returns
364 // here, which will result in MultNode being mapped to a single MULT
Bruno Cardoso Lopes8e826e62011-02-10 18:05:10 +0000365 // instruction node rather than a pair of MULT and MADD instructions being
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000366 // produced.
367 if (!MultHi.hasOneUse() || !MultLo.hasOneUse())
368 return false;
369
Bruno Cardoso Lopes8e826e62011-02-10 18:05:10 +0000370 SDValue Chain = CurDAG->getEntryNode();
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000371 DebugLoc dl = ADDENode->getDebugLoc();
372
373 // create MipsMAdd(u) node
374 MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MAddu : MipsISD::MAdd;
Bruno Cardoso Lopes8e826e62011-02-10 18:05:10 +0000375
Akira Hatanaka82099682011-12-19 19:52:25 +0000376 SDValue MAdd = CurDAG->getNode(MultOpc, dl, MVT::Glue,
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000377 MultNode->getOperand(0),// Factor 0
378 MultNode->getOperand(1),// Factor 1
Bruno Cardoso Lopes8e826e62011-02-10 18:05:10 +0000379 ADDCNode->getOperand(1),// Lo0
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000380 ADDENode->getOperand(1));// Hi0
381
382 // create CopyFromReg nodes
383 SDValue CopyFromLo = CurDAG->getCopyFromReg(Chain, dl, Mips::LO, MVT::i32,
384 MAdd);
Bruno Cardoso Lopes8e826e62011-02-10 18:05:10 +0000385 SDValue CopyFromHi = CurDAG->getCopyFromReg(CopyFromLo.getValue(1), dl,
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000386 Mips::HI, MVT::i32,
387 CopyFromLo.getValue(2));
388
389 // replace uses of adde and addc here
390 if (!SDValue(ADDCNode, 0).use_empty())
391 CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDCNode, 0), CopyFromLo);
392
393 if (!SDValue(ADDENode, 0).use_empty())
394 CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDENode, 0), CopyFromHi);
395
Bruno Cardoso Lopes8e826e62011-02-10 18:05:10 +0000396 return true;
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000397}
398
399// SelectMsub -
400// Transforms a subgraph in CurDAG if the following pattern is found:
401// (addc Lo0, multLo), (sube Hi0, multHi),
402// where,
403// multHi/Lo: product of multiplication
Bruno Cardoso Lopes8e826e62011-02-10 18:05:10 +0000404// Lo0: initial value of Lo register
405// Hi0: initial value of Hi register
Akira Hatanaka81bd78b2011-03-30 21:15:35 +0000406// Return true if pattern matching was successful.
Akira Hatanaka864f6602012-06-14 21:10:56 +0000407static bool SelectMsub(SDNode *SUBENode, SelectionDAG *CurDAG) {
Bruno Cardoso Lopes8e826e62011-02-10 18:05:10 +0000408 // SUBENode's second operand must be a flag output of an SUBC node in order
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000409 // for the matching to be successful.
Akira Hatanaka864f6602012-06-14 21:10:56 +0000410 SDNode *SUBCNode = SUBENode->getOperand(2).getNode();
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000411
412 if (SUBCNode->getOpcode() != ISD::SUBC)
413 return false;
414
415 SDValue MultHi = SUBENode->getOperand(1);
416 SDValue MultLo = SUBCNode->getOperand(1);
Akira Hatanaka864f6602012-06-14 21:10:56 +0000417 SDNode *MultNode = MultHi.getNode();
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000418 unsigned MultOpc = MultHi.getOpcode();
419
420 // MultHi and MultLo must be generated by the same node,
421 if (MultLo.getNode() != MultNode)
422 return false;
423
424 // and it must be a multiplication.
425 if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI)
426 return false;
427
428 // MultLo amd MultHi must be the first and second output of MultNode
429 // respectively.
430 if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0)
431 return false;
432
433 // Transform this to a MSUB only if SUBENode and SUBCNode are the only users
434 // of the values of MultNode, in which case MultNode will be removed in later
435 // phases.
Akira Hatanaka4552c9a2011-04-15 21:51:11 +0000436 // If there exist users other than SUBENode or SUBCNode, this function returns
437 // here, which will result in MultNode being mapped to a single MULT
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000438 // instruction node rather than a pair of MULT and MSUB instructions being
439 // produced.
440 if (!MultHi.hasOneUse() || !MultLo.hasOneUse())
441 return false;
442
443 SDValue Chain = CurDAG->getEntryNode();
444 DebugLoc dl = SUBENode->getDebugLoc();
445
446 // create MipsSub(u) node
447 MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MSubu : MipsISD::MSub;
448
Akira Hatanaka82099682011-12-19 19:52:25 +0000449 SDValue MSub = CurDAG->getNode(MultOpc, dl, MVT::Glue,
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000450 MultNode->getOperand(0),// Factor 0
451 MultNode->getOperand(1),// Factor 1
452 SUBCNode->getOperand(0),// Lo0
453 SUBENode->getOperand(0));// Hi0
454
455 // create CopyFromReg nodes
456 SDValue CopyFromLo = CurDAG->getCopyFromReg(Chain, dl, Mips::LO, MVT::i32,
457 MSub);
458 SDValue CopyFromHi = CurDAG->getCopyFromReg(CopyFromLo.getValue(1), dl,
459 Mips::HI, MVT::i32,
460 CopyFromLo.getValue(2));
461
462 // replace uses of sube and subc here
463 if (!SDValue(SUBCNode, 0).use_empty())
464 CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBCNode, 0), CopyFromLo);
465
466 if (!SDValue(SUBENode, 0).use_empty())
467 CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBENode, 0), CopyFromHi);
468
469 return true;
470}
471
Akira Hatanaka864f6602012-06-14 21:10:56 +0000472static SDValue PerformADDECombine(SDNode *N, SelectionDAG &DAG,
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000473 TargetLowering::DAGCombinerInfo &DCI,
Akira Hatanaka864f6602012-06-14 21:10:56 +0000474 const MipsSubtarget *Subtarget) {
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000475 if (DCI.isBeforeLegalize())
476 return SDValue();
477
Akira Hatanakae184fec2011-11-11 04:18:21 +0000478 if (Subtarget->hasMips32() && N->getValueType(0) == MVT::i32 &&
479 SelectMadd(N, &DAG))
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000480 return SDValue(N, 0);
Bruno Cardoso Lopes8e826e62011-02-10 18:05:10 +0000481
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000482 return SDValue();
Bruno Cardoso Lopes8e826e62011-02-10 18:05:10 +0000483}
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000484
Akira Hatanaka864f6602012-06-14 21:10:56 +0000485static SDValue PerformSUBECombine(SDNode *N, SelectionDAG &DAG,
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000486 TargetLowering::DAGCombinerInfo &DCI,
Akira Hatanaka864f6602012-06-14 21:10:56 +0000487 const MipsSubtarget *Subtarget) {
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000488 if (DCI.isBeforeLegalize())
489 return SDValue();
490
Akira Hatanakae184fec2011-11-11 04:18:21 +0000491 if (Subtarget->hasMips32() && N->getValueType(0) == MVT::i32 &&
492 SelectMsub(N, &DAG))
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000493 return SDValue(N, 0);
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000494
Bruno Cardoso Lopes8e826e62011-02-10 18:05:10 +0000495 return SDValue();
496}
497
Akira Hatanaka864f6602012-06-14 21:10:56 +0000498static SDValue PerformDivRemCombine(SDNode *N, SelectionDAG &DAG,
Bruno Cardoso Lopes38b5e862011-03-04 21:03:24 +0000499 TargetLowering::DAGCombinerInfo &DCI,
Akira Hatanaka864f6602012-06-14 21:10:56 +0000500 const MipsSubtarget *Subtarget) {
Bruno Cardoso Lopes38b5e862011-03-04 21:03:24 +0000501 if (DCI.isBeforeLegalizeOps())
502 return SDValue();
503
Akira Hatanakadda4a072011-10-03 21:06:13 +0000504 EVT Ty = N->getValueType(0);
Jia Liubb481f82012-02-28 07:46:26 +0000505 unsigned LO = (Ty == MVT::i32) ? Mips::LO : Mips::LO64;
506 unsigned HI = (Ty == MVT::i32) ? Mips::HI : Mips::HI64;
Bruno Cardoso Lopes38b5e862011-03-04 21:03:24 +0000507 unsigned opc = N->getOpcode() == ISD::SDIVREM ? MipsISD::DivRem :
508 MipsISD::DivRemU;
509 DebugLoc dl = N->getDebugLoc();
510
511 SDValue DivRem = DAG.getNode(opc, dl, MVT::Glue,
512 N->getOperand(0), N->getOperand(1));
513 SDValue InChain = DAG.getEntryNode();
514 SDValue InGlue = DivRem;
515
516 // insert MFLO
517 if (N->hasAnyUseOfValue(0)) {
Akira Hatanakadda4a072011-10-03 21:06:13 +0000518 SDValue CopyFromLo = DAG.getCopyFromReg(InChain, dl, LO, Ty,
Bruno Cardoso Lopes38b5e862011-03-04 21:03:24 +0000519 InGlue);
520 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), CopyFromLo);
521 InChain = CopyFromLo.getValue(1);
522 InGlue = CopyFromLo.getValue(2);
523 }
524
525 // insert MFHI
526 if (N->hasAnyUseOfValue(1)) {
527 SDValue CopyFromHi = DAG.getCopyFromReg(InChain, dl,
Akira Hatanakadda4a072011-10-03 21:06:13 +0000528 HI, Ty, InGlue);
Bruno Cardoso Lopes38b5e862011-03-04 21:03:24 +0000529 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), CopyFromHi);
530 }
531
532 return SDValue();
533}
534
Akira Hatanaka1d6b38d2011-03-31 18:26:17 +0000535static Mips::CondCode FPCondCCodeToFCC(ISD::CondCode CC) {
536 switch (CC) {
537 default: llvm_unreachable("Unknown fp condition code!");
538 case ISD::SETEQ:
539 case ISD::SETOEQ: return Mips::FCOND_OEQ;
540 case ISD::SETUNE: return Mips::FCOND_UNE;
541 case ISD::SETLT:
542 case ISD::SETOLT: return Mips::FCOND_OLT;
543 case ISD::SETGT:
544 case ISD::SETOGT: return Mips::FCOND_OGT;
545 case ISD::SETLE:
546 case ISD::SETOLE: return Mips::FCOND_OLE;
547 case ISD::SETGE:
548 case ISD::SETOGE: return Mips::FCOND_OGE;
549 case ISD::SETULT: return Mips::FCOND_ULT;
550 case ISD::SETULE: return Mips::FCOND_ULE;
551 case ISD::SETUGT: return Mips::FCOND_UGT;
552 case ISD::SETUGE: return Mips::FCOND_UGE;
553 case ISD::SETUO: return Mips::FCOND_UN;
554 case ISD::SETO: return Mips::FCOND_OR;
555 case ISD::SETNE:
556 case ISD::SETONE: return Mips::FCOND_ONE;
557 case ISD::SETUEQ: return Mips::FCOND_UEQ;
558 }
559}
560
561
562// Returns true if condition code has to be inverted.
563static bool InvertFPCondCode(Mips::CondCode CC) {
564 if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT)
565 return false;
566
Akira Hatanaka82099682011-12-19 19:52:25 +0000567 assert((CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT) &&
568 "Illegal Condition Code");
Akira Hatanaka1d6b38d2011-03-31 18:26:17 +0000569
Akira Hatanaka82099682011-12-19 19:52:25 +0000570 return true;
Akira Hatanaka1d6b38d2011-03-31 18:26:17 +0000571}
572
573// Creates and returns an FPCmp node from a setcc node.
574// Returns Op if setcc is not a floating point comparison.
Akira Hatanaka864f6602012-06-14 21:10:56 +0000575static SDValue CreateFPCmp(SelectionDAG &DAG, const SDValue &Op) {
Akira Hatanaka1d6b38d2011-03-31 18:26:17 +0000576 // must be a SETCC node
577 if (Op.getOpcode() != ISD::SETCC)
578 return Op;
579
580 SDValue LHS = Op.getOperand(0);
581
582 if (!LHS.getValueType().isFloatingPoint())
583 return Op;
584
585 SDValue RHS = Op.getOperand(1);
586 DebugLoc dl = Op.getDebugLoc();
587
Akira Hatanaka0bf3dfb2011-04-15 21:00:26 +0000588 // Assume the 3rd operand is a CondCodeSDNode. Add code to check the type of
589 // node if necessary.
Akira Hatanaka1d6b38d2011-03-31 18:26:17 +0000590 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
591
592 return DAG.getNode(MipsISD::FPCmp, dl, MVT::Glue, LHS, RHS,
593 DAG.getConstant(FPCondCCodeToFCC(CC), MVT::i32));
594}
595
596// Creates and returns a CMovFPT/F node.
Akira Hatanaka864f6602012-06-14 21:10:56 +0000597static SDValue CreateCMovFP(SelectionDAG &DAG, SDValue Cond, SDValue True,
Akira Hatanaka1d6b38d2011-03-31 18:26:17 +0000598 SDValue False, DebugLoc DL) {
599 bool invert = InvertFPCondCode((Mips::CondCode)
600 cast<ConstantSDNode>(Cond.getOperand(2))
601 ->getSExtValue());
602
603 return DAG.getNode((invert ? MipsISD::CMovFP_F : MipsISD::CMovFP_T), DL,
604 True.getValueType(), True, False, Cond);
605}
606
Akira Hatanaka864f6602012-06-14 21:10:56 +0000607static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
Akira Hatanakae2bdf7f2012-03-08 02:14:24 +0000608 TargetLowering::DAGCombinerInfo &DCI,
Akira Hatanaka864f6602012-06-14 21:10:56 +0000609 const MipsSubtarget *Subtarget) {
Akira Hatanakae2bdf7f2012-03-08 02:14:24 +0000610 if (DCI.isBeforeLegalizeOps())
611 return SDValue();
612
613 SDValue SetCC = N->getOperand(0);
614
615 if ((SetCC.getOpcode() != ISD::SETCC) ||
616 !SetCC.getOperand(0).getValueType().isInteger())
617 return SDValue();
618
619 SDValue False = N->getOperand(2);
620 EVT FalseTy = False.getValueType();
621
622 if (!FalseTy.isInteger())
623 return SDValue();
624
625 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(False);
626
627 if (!CN || CN->getZExtValue())
628 return SDValue();
629
630 const DebugLoc DL = N->getDebugLoc();
631 ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get();
632 SDValue True = N->getOperand(1);
Akira Hatanaka864f6602012-06-14 21:10:56 +0000633
Akira Hatanakae2bdf7f2012-03-08 02:14:24 +0000634 SetCC = DAG.getSetCC(DL, SetCC.getValueType(), SetCC.getOperand(0),
635 SetCC.getOperand(1), ISD::getSetCCInverse(CC, true));
Akira Hatanaka864f6602012-06-14 21:10:56 +0000636
Akira Hatanakae2bdf7f2012-03-08 02:14:24 +0000637 return DAG.getNode(ISD::SELECT, DL, FalseTy, SetCC, False, True);
638}
639
Akira Hatanaka864f6602012-06-14 21:10:56 +0000640static SDValue PerformANDCombine(SDNode *N, SelectionDAG &DAG,
Akira Hatanaka77b85b62011-08-17 17:45:08 +0000641 TargetLowering::DAGCombinerInfo &DCI,
Akira Hatanaka864f6602012-06-14 21:10:56 +0000642 const MipsSubtarget *Subtarget) {
Akira Hatanaka77b85b62011-08-17 17:45:08 +0000643 // Pattern match EXT.
644 // $dst = and ((sra or srl) $src , pos), (2**size - 1)
645 // => ext $dst, $src, size, pos
Akira Hatanaka56633442011-09-20 23:53:09 +0000646 if (DCI.isBeforeLegalizeOps() || !Subtarget->hasMips32r2())
Akira Hatanaka77b85b62011-08-17 17:45:08 +0000647 return SDValue();
648
649 SDValue ShiftRight = N->getOperand(0), Mask = N->getOperand(1);
Akira Hatanakad6bc5232011-12-05 21:26:34 +0000650 unsigned ShiftRightOpc = ShiftRight.getOpcode();
651
Akira Hatanaka77b85b62011-08-17 17:45:08 +0000652 // Op's first operand must be a shift right.
Akira Hatanakad6bc5232011-12-05 21:26:34 +0000653 if (ShiftRightOpc != ISD::SRA && ShiftRightOpc != ISD::SRL)
Akira Hatanaka77b85b62011-08-17 17:45:08 +0000654 return SDValue();
655
656 // The second operand of the shift must be an immediate.
Akira Hatanaka77b85b62011-08-17 17:45:08 +0000657 ConstantSDNode *CN;
658 if (!(CN = dyn_cast<ConstantSDNode>(ShiftRight.getOperand(1))))
659 return SDValue();
Jia Liubb481f82012-02-28 07:46:26 +0000660
Akira Hatanakad6bc5232011-12-05 21:26:34 +0000661 uint64_t Pos = CN->getZExtValue();
Akira Hatanaka77b85b62011-08-17 17:45:08 +0000662 uint64_t SMPos, SMSize;
Akira Hatanakad6bc5232011-12-05 21:26:34 +0000663
Akira Hatanaka77b85b62011-08-17 17:45:08 +0000664 // Op's second operand must be a shifted mask.
665 if (!(CN = dyn_cast<ConstantSDNode>(Mask)) ||
Akira Hatanaka854a7db2011-08-19 22:59:00 +0000666 !IsShiftedMask(CN->getZExtValue(), SMPos, SMSize))
Akira Hatanaka77b85b62011-08-17 17:45:08 +0000667 return SDValue();
668
669 // Return if the shifted mask does not start at bit 0 or the sum of its size
670 // and Pos exceeds the word's size.
Akira Hatanakad6bc5232011-12-05 21:26:34 +0000671 EVT ValTy = N->getValueType(0);
672 if (SMPos != 0 || Pos + SMSize > ValTy.getSizeInBits())
Akira Hatanaka77b85b62011-08-17 17:45:08 +0000673 return SDValue();
674
Akira Hatanakad6bc5232011-12-05 21:26:34 +0000675 return DAG.getNode(MipsISD::Ext, N->getDebugLoc(), ValTy,
Akira Hatanaka82099682011-12-19 19:52:25 +0000676 ShiftRight.getOperand(0), DAG.getConstant(Pos, MVT::i32),
Akira Hatanaka667645f2011-08-17 22:59:46 +0000677 DAG.getConstant(SMSize, MVT::i32));
Akira Hatanaka77b85b62011-08-17 17:45:08 +0000678}
Jia Liubb481f82012-02-28 07:46:26 +0000679
Akira Hatanaka864f6602012-06-14 21:10:56 +0000680static SDValue PerformORCombine(SDNode *N, SelectionDAG &DAG,
Akira Hatanaka77b85b62011-08-17 17:45:08 +0000681 TargetLowering::DAGCombinerInfo &DCI,
Akira Hatanaka864f6602012-06-14 21:10:56 +0000682 const MipsSubtarget *Subtarget) {
Akira Hatanaka77b85b62011-08-17 17:45:08 +0000683 // Pattern match INS.
684 // $dst = or (and $src1 , mask0), (and (shl $src, pos), mask1),
Jia Liubb481f82012-02-28 07:46:26 +0000685 // where mask1 = (2**size - 1) << pos, mask0 = ~mask1
Akira Hatanaka77b85b62011-08-17 17:45:08 +0000686 // => ins $dst, $src, size, pos, $src1
Akira Hatanaka56633442011-09-20 23:53:09 +0000687 if (DCI.isBeforeLegalizeOps() || !Subtarget->hasMips32r2())
Akira Hatanaka77b85b62011-08-17 17:45:08 +0000688 return SDValue();
689
690 SDValue And0 = N->getOperand(0), And1 = N->getOperand(1);
691 uint64_t SMPos0, SMSize0, SMPos1, SMSize1;
692 ConstantSDNode *CN;
693
694 // See if Op's first operand matches (and $src1 , mask0).
695 if (And0.getOpcode() != ISD::AND)
696 return SDValue();
697
698 if (!(CN = dyn_cast<ConstantSDNode>(And0.getOperand(1))) ||
Akira Hatanaka854a7db2011-08-19 22:59:00 +0000699 !IsShiftedMask(~CN->getSExtValue(), SMPos0, SMSize0))
Akira Hatanaka77b85b62011-08-17 17:45:08 +0000700 return SDValue();
701
702 // See if Op's second operand matches (and (shl $src, pos), mask1).
703 if (And1.getOpcode() != ISD::AND)
704 return SDValue();
Jia Liubb481f82012-02-28 07:46:26 +0000705
Akira Hatanaka77b85b62011-08-17 17:45:08 +0000706 if (!(CN = dyn_cast<ConstantSDNode>(And1.getOperand(1))) ||
Akira Hatanaka854a7db2011-08-19 22:59:00 +0000707 !IsShiftedMask(CN->getZExtValue(), SMPos1, SMSize1))
Akira Hatanaka77b85b62011-08-17 17:45:08 +0000708 return SDValue();
709
710 // The shift masks must have the same position and size.
711 if (SMPos0 != SMPos1 || SMSize0 != SMSize1)
712 return SDValue();
713
714 SDValue Shl = And1.getOperand(0);
715 if (Shl.getOpcode() != ISD::SHL)
716 return SDValue();
717
718 if (!(CN = dyn_cast<ConstantSDNode>(Shl.getOperand(1))))
719 return SDValue();
720
721 unsigned Shamt = CN->getZExtValue();
722
723 // Return if the shift amount and the first bit position of mask are not the
Jia Liubb481f82012-02-28 07:46:26 +0000724 // same.
Akira Hatanakad6bc5232011-12-05 21:26:34 +0000725 EVT ValTy = N->getValueType(0);
726 if ((Shamt != SMPos0) || (SMPos0 + SMSize0 > ValTy.getSizeInBits()))
Akira Hatanaka77b85b62011-08-17 17:45:08 +0000727 return SDValue();
Jia Liubb481f82012-02-28 07:46:26 +0000728
Akira Hatanaka82099682011-12-19 19:52:25 +0000729 return DAG.getNode(MipsISD::Ins, N->getDebugLoc(), ValTy, Shl.getOperand(0),
Akira Hatanaka77b85b62011-08-17 17:45:08 +0000730 DAG.getConstant(SMPos0, MVT::i32),
Akira Hatanaka82099682011-12-19 19:52:25 +0000731 DAG.getConstant(SMSize0, MVT::i32), And0.getOperand(0));
Akira Hatanaka77b85b62011-08-17 17:45:08 +0000732}
Jia Liubb481f82012-02-28 07:46:26 +0000733
Akira Hatanaka864f6602012-06-14 21:10:56 +0000734static SDValue PerformADDCombine(SDNode *N, SelectionDAG &DAG,
Akira Hatanaka87827072012-06-13 20:33:18 +0000735 TargetLowering::DAGCombinerInfo &DCI,
Akira Hatanaka864f6602012-06-14 21:10:56 +0000736 const MipsSubtarget *Subtarget) {
Akira Hatanaka87827072012-06-13 20:33:18 +0000737 // (add v0, (add v1, abs_lo(tjt))) => (add (add v0, v1), abs_lo(tjt))
738
739 if (DCI.isBeforeLegalizeOps())
740 return SDValue();
741
742 SDValue Add = N->getOperand(1);
743
744 if (Add.getOpcode() != ISD::ADD)
745 return SDValue();
746
747 SDValue Lo = Add.getOperand(1);
748
749 if ((Lo.getOpcode() != MipsISD::Lo) ||
750 (Lo.getOperand(0).getOpcode() != ISD::TargetJumpTable))
751 return SDValue();
752
753 EVT ValTy = N->getValueType(0);
754 DebugLoc DL = N->getDebugLoc();
755
756 SDValue Add1 = DAG.getNode(ISD::ADD, DL, ValTy, N->getOperand(0),
757 Add.getOperand(0));
758 return DAG.getNode(ISD::ADD, DL, ValTy, Add1, Lo);
759}
760
Bruno Cardoso Lopes8e826e62011-02-10 18:05:10 +0000761SDValue MipsTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI)
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000762 const {
763 SelectionDAG &DAG = DCI.DAG;
764 unsigned opc = N->getOpcode();
765
766 switch (opc) {
767 default: break;
768 case ISD::ADDE:
769 return PerformADDECombine(N, DAG, DCI, Subtarget);
770 case ISD::SUBE:
771 return PerformSUBECombine(N, DAG, DCI, Subtarget);
Bruno Cardoso Lopes38b5e862011-03-04 21:03:24 +0000772 case ISD::SDIVREM:
773 case ISD::UDIVREM:
774 return PerformDivRemCombine(N, DAG, DCI, Subtarget);
Akira Hatanakae2bdf7f2012-03-08 02:14:24 +0000775 case ISD::SELECT:
Akira Hatanaka864f6602012-06-14 21:10:56 +0000776 return PerformSELECTCombine(N, DAG, DCI, Subtarget);
Akira Hatanaka77b85b62011-08-17 17:45:08 +0000777 case ISD::AND:
778 return PerformANDCombine(N, DAG, DCI, Subtarget);
779 case ISD::OR:
780 return PerformORCombine(N, DAG, DCI, Subtarget);
Akira Hatanaka87827072012-06-13 20:33:18 +0000781 case ISD::ADD:
782 return PerformADDCombine(N, DAG, DCI, Subtarget);
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000783 }
784
785 return SDValue();
786}
787
Dan Gohman475871a2008-07-27 21:46:04 +0000788SDValue MipsTargetLowering::
Dan Gohmand858e902010-04-17 15:26:15 +0000789LowerOperation(SDValue Op, SelectionDAG &DAG) const
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +0000790{
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000791 switch (Op.getOpcode())
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +0000792 {
Bruno Cardoso Lopes7da151c2008-08-07 19:08:11 +0000793 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
Bruno Cardoso Lopes7da151c2008-08-07 19:08:11 +0000794 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
795 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
Bruno Cardoso Lopes7da151c2008-08-07 19:08:11 +0000796 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
Bruno Cardoso Lopesca8a2aa2011-03-04 20:01:52 +0000797 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
Bruno Cardoso Lopes7da151c2008-08-07 19:08:11 +0000798 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
799 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
Bruno Cardoso Lopes7da151c2008-08-07 19:08:11 +0000800 case ISD::SELECT: return LowerSELECT(Op, DAG);
Akira Hatanaka3fef29d2012-07-11 19:32:27 +0000801 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
Akira Hatanaka0a40c232012-03-09 23:46:03 +0000802 case ISD::SETCC: return LowerSETCC(Op, DAG);
Bruno Cardoso Lopes6059b852010-02-06 21:00:02 +0000803 case ISD::VASTART: return LowerVASTART(Op, DAG);
Akira Hatanaka9c3d57c2011-05-25 19:32:07 +0000804 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
Akira Hatanakac12a6e62012-04-11 22:49:04 +0000805 case ISD::FABS: return LowerFABS(Op, DAG);
Akira Hatanaka2e591472011-06-02 00:24:44 +0000806 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
Akira Hatanakaba584fe2012-07-11 00:53:32 +0000807 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
Akira Hatanakadb548262011-07-19 23:30:50 +0000808 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op, DAG);
Eli Friedman14648462011-07-27 22:21:52 +0000809 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, DAG);
Akira Hatanakaa284acb2012-05-09 00:55:21 +0000810 case ISD::SHL_PARTS: return LowerShiftLeftParts(Op, DAG);
811 case ISD::SRA_PARTS: return LowerShiftRightParts(Op, DAG, true);
812 case ISD::SRL_PARTS: return LowerShiftRightParts(Op, DAG, false);
Akira Hatanaka1cd0ec02012-06-02 00:03:49 +0000813 case ISD::LOAD: return LowerLOAD(Op, DAG);
814 case ISD::STORE: return LowerSTORE(Op, DAG);
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +0000815 }
Dan Gohman475871a2008-07-27 21:46:04 +0000816 return SDValue();
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +0000817}
818
Akira Hatanaka4552c9a2011-04-15 21:51:11 +0000819//===----------------------------------------------------------------------===//
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +0000820// Lower helper functions
Akira Hatanaka4552c9a2011-04-15 21:51:11 +0000821//===----------------------------------------------------------------------===//
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +0000822
823// AddLiveIn - This helper function adds the specified physical register to the
824// MachineFunction as a live in value. It also creates a corresponding
825// virtual register for it.
826static unsigned
Craig Topper44d23822012-02-22 05:59:10 +0000827AddLiveIn(MachineFunction &MF, unsigned PReg, const TargetRegisterClass *RC)
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +0000828{
829 assert(RC->contains(PReg) && "Not the correct regclass!");
Chris Lattner84bc5422007-12-31 04:13:23 +0000830 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC);
831 MF.getRegInfo().addLiveIn(PReg, VReg);
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +0000832 return VReg;
833}
834
Bruno Cardoso Lopes85e31e32008-07-28 19:11:24 +0000835// Get fp branch code (not opcode) from condition code.
836static Mips::FPBranchCode GetFPBranchCodeFromCond(Mips::CondCode CC) {
837 if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT)
838 return Mips::BRANCH_T;
839
Akira Hatanaka82099682011-12-19 19:52:25 +0000840 assert((CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT) &&
841 "Invalid CondCode.");
Bruno Cardoso Lopes85e31e32008-07-28 19:11:24 +0000842
Akira Hatanaka82099682011-12-19 19:52:25 +0000843 return Mips::BRANCH_F;
Bruno Cardoso Lopes85e31e32008-07-28 19:11:24 +0000844}
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000845
Akira Hatanaka8ae330a2011-10-17 18:53:29 +0000846/*
Akira Hatanaka14487d42011-06-07 19:28:39 +0000847static MachineBasicBlock* ExpandCondMov(MachineInstr *MI, MachineBasicBlock *BB,
848 DebugLoc dl,
Akira Hatanaka864f6602012-06-14 21:10:56 +0000849 const MipsSubtarget *Subtarget,
Akira Hatanaka14487d42011-06-07 19:28:39 +0000850 const TargetInstrInfo *TII,
851 bool isFPCmp, unsigned Opc) {
852 // There is no need to expand CMov instructions if target has
853 // conditional moves.
854 if (Subtarget->hasCondMov())
855 return BB;
856
857 // To "insert" a SELECT_CC instruction, we actually have to insert the
858 // diamond control-flow pattern. The incoming instruction knows the
859 // destination vreg to set, the condition code register to branch on, the
860 // true/false values to select between, and a branch opcode to use.
861 const BasicBlock *LLVM_BB = BB->getBasicBlock();
862 MachineFunction::iterator It = BB;
863 ++It;
864
865 // thisMBB:
866 // ...
867 // TrueVal = ...
868 // setcc r1, r2, r3
869 // bNE r1, r0, copy1MBB
870 // fallthrough --> copy0MBB
871 MachineBasicBlock *thisMBB = BB;
872 MachineFunction *F = BB->getParent();
873 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
874 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
875 F->insert(It, copy0MBB);
876 F->insert(It, sinkMBB);
877
878 // Transfer the remainder of BB and its successor edges to sinkMBB.
879 sinkMBB->splice(sinkMBB->begin(), BB,
880 llvm::next(MachineBasicBlock::iterator(MI)),
881 BB->end());
882 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
883
884 // Next, add the true and fallthrough blocks as its successors.
885 BB->addSuccessor(copy0MBB);
886 BB->addSuccessor(sinkMBB);
887
888 // Emit the right instruction according to the type of the operands compared
889 if (isFPCmp)
890 BuildMI(BB, dl, TII->get(Opc)).addMBB(sinkMBB);
891 else
892 BuildMI(BB, dl, TII->get(Opc)).addReg(MI->getOperand(2).getReg())
893 .addReg(Mips::ZERO).addMBB(sinkMBB);
894
895 // copy0MBB:
896 // %FalseValue = ...
897 // # fallthrough to sinkMBB
898 BB = copy0MBB;
899
900 // Update machine-CFG edges
901 BB->addSuccessor(sinkMBB);
902
903 // sinkMBB:
904 // %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ]
905 // ...
906 BB = sinkMBB;
907
908 if (isFPCmp)
909 BuildMI(*BB, BB->begin(), dl,
910 TII->get(Mips::PHI), MI->getOperand(0).getReg())
911 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB)
912 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB);
913 else
914 BuildMI(*BB, BB->begin(), dl,
915 TII->get(Mips::PHI), MI->getOperand(0).getReg())
916 .addReg(MI->getOperand(3).getReg()).addMBB(thisMBB)
917 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB);
918
919 MI->eraseFromParent(); // The pseudo instruction is gone now.
920 return BB;
921}
Akira Hatanaka8ae330a2011-10-17 18:53:29 +0000922*/
Bruno Cardoso Lopes6d399bd2008-07-29 19:05:28 +0000923MachineBasicBlock *
924MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
Dan Gohmanaf1d8ca2010-05-01 00:01:06 +0000925 MachineBasicBlock *BB) const {
Bruno Cardoso Lopes6d399bd2008-07-29 19:05:28 +0000926 switch (MI->getOpcode()) {
Craig Topperbc219812012-02-07 02:50:20 +0000927 default: llvm_unreachable("Unexpected instr type to insert");
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000928 case Mips::ATOMIC_LOAD_ADD_I8:
Akira Hatanaka59068062011-11-11 04:14:30 +0000929 case Mips::ATOMIC_LOAD_ADD_I8_P8:
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000930 return EmitAtomicBinaryPartword(MI, BB, 1, Mips::ADDu);
931 case Mips::ATOMIC_LOAD_ADD_I16:
Akira Hatanaka59068062011-11-11 04:14:30 +0000932 case Mips::ATOMIC_LOAD_ADD_I16_P8:
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000933 return EmitAtomicBinaryPartword(MI, BB, 2, Mips::ADDu);
934 case Mips::ATOMIC_LOAD_ADD_I32:
Akira Hatanaka59068062011-11-11 04:14:30 +0000935 case Mips::ATOMIC_LOAD_ADD_I32_P8:
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000936 return EmitAtomicBinary(MI, BB, 4, Mips::ADDu);
Akira Hatanaka59068062011-11-11 04:14:30 +0000937 case Mips::ATOMIC_LOAD_ADD_I64:
938 case Mips::ATOMIC_LOAD_ADD_I64_P8:
939 return EmitAtomicBinary(MI, BB, 8, Mips::DADDu);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000940
941 case Mips::ATOMIC_LOAD_AND_I8:
Akira Hatanaka59068062011-11-11 04:14:30 +0000942 case Mips::ATOMIC_LOAD_AND_I8_P8:
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000943 return EmitAtomicBinaryPartword(MI, BB, 1, Mips::AND);
944 case Mips::ATOMIC_LOAD_AND_I16:
Akira Hatanaka59068062011-11-11 04:14:30 +0000945 case Mips::ATOMIC_LOAD_AND_I16_P8:
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000946 return EmitAtomicBinaryPartword(MI, BB, 2, Mips::AND);
947 case Mips::ATOMIC_LOAD_AND_I32:
Akira Hatanaka59068062011-11-11 04:14:30 +0000948 case Mips::ATOMIC_LOAD_AND_I32_P8:
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000949 return EmitAtomicBinary(MI, BB, 4, Mips::AND);
Akira Hatanaka59068062011-11-11 04:14:30 +0000950 case Mips::ATOMIC_LOAD_AND_I64:
951 case Mips::ATOMIC_LOAD_AND_I64_P8:
Akira Hatanaka73866122011-11-12 02:38:12 +0000952 return EmitAtomicBinary(MI, BB, 8, Mips::AND64);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000953
954 case Mips::ATOMIC_LOAD_OR_I8:
Akira Hatanaka59068062011-11-11 04:14:30 +0000955 case Mips::ATOMIC_LOAD_OR_I8_P8:
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000956 return EmitAtomicBinaryPartword(MI, BB, 1, Mips::OR);
957 case Mips::ATOMIC_LOAD_OR_I16:
Akira Hatanaka59068062011-11-11 04:14:30 +0000958 case Mips::ATOMIC_LOAD_OR_I16_P8:
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000959 return EmitAtomicBinaryPartword(MI, BB, 2, Mips::OR);
960 case Mips::ATOMIC_LOAD_OR_I32:
Akira Hatanaka59068062011-11-11 04:14:30 +0000961 case Mips::ATOMIC_LOAD_OR_I32_P8:
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000962 return EmitAtomicBinary(MI, BB, 4, Mips::OR);
Akira Hatanaka59068062011-11-11 04:14:30 +0000963 case Mips::ATOMIC_LOAD_OR_I64:
964 case Mips::ATOMIC_LOAD_OR_I64_P8:
965 return EmitAtomicBinary(MI, BB, 8, Mips::OR64);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000966
967 case Mips::ATOMIC_LOAD_XOR_I8:
Akira Hatanaka59068062011-11-11 04:14:30 +0000968 case Mips::ATOMIC_LOAD_XOR_I8_P8:
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000969 return EmitAtomicBinaryPartword(MI, BB, 1, Mips::XOR);
970 case Mips::ATOMIC_LOAD_XOR_I16:
Akira Hatanaka59068062011-11-11 04:14:30 +0000971 case Mips::ATOMIC_LOAD_XOR_I16_P8:
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000972 return EmitAtomicBinaryPartword(MI, BB, 2, Mips::XOR);
973 case Mips::ATOMIC_LOAD_XOR_I32:
Akira Hatanaka59068062011-11-11 04:14:30 +0000974 case Mips::ATOMIC_LOAD_XOR_I32_P8:
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000975 return EmitAtomicBinary(MI, BB, 4, Mips::XOR);
Akira Hatanaka59068062011-11-11 04:14:30 +0000976 case Mips::ATOMIC_LOAD_XOR_I64:
977 case Mips::ATOMIC_LOAD_XOR_I64_P8:
978 return EmitAtomicBinary(MI, BB, 8, Mips::XOR64);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000979
980 case Mips::ATOMIC_LOAD_NAND_I8:
Akira Hatanaka59068062011-11-11 04:14:30 +0000981 case Mips::ATOMIC_LOAD_NAND_I8_P8:
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000982 return EmitAtomicBinaryPartword(MI, BB, 1, 0, true);
983 case Mips::ATOMIC_LOAD_NAND_I16:
Akira Hatanaka59068062011-11-11 04:14:30 +0000984 case Mips::ATOMIC_LOAD_NAND_I16_P8:
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000985 return EmitAtomicBinaryPartword(MI, BB, 2, 0, true);
986 case Mips::ATOMIC_LOAD_NAND_I32:
Akira Hatanaka59068062011-11-11 04:14:30 +0000987 case Mips::ATOMIC_LOAD_NAND_I32_P8:
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000988 return EmitAtomicBinary(MI, BB, 4, 0, true);
Akira Hatanaka59068062011-11-11 04:14:30 +0000989 case Mips::ATOMIC_LOAD_NAND_I64:
990 case Mips::ATOMIC_LOAD_NAND_I64_P8:
991 return EmitAtomicBinary(MI, BB, 8, 0, true);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000992
993 case Mips::ATOMIC_LOAD_SUB_I8:
Akira Hatanaka59068062011-11-11 04:14:30 +0000994 case Mips::ATOMIC_LOAD_SUB_I8_P8:
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000995 return EmitAtomicBinaryPartword(MI, BB, 1, Mips::SUBu);
996 case Mips::ATOMIC_LOAD_SUB_I16:
Akira Hatanaka59068062011-11-11 04:14:30 +0000997 case Mips::ATOMIC_LOAD_SUB_I16_P8:
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000998 return EmitAtomicBinaryPartword(MI, BB, 2, Mips::SUBu);
999 case Mips::ATOMIC_LOAD_SUB_I32:
Akira Hatanaka59068062011-11-11 04:14:30 +00001000 case Mips::ATOMIC_LOAD_SUB_I32_P8:
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001001 return EmitAtomicBinary(MI, BB, 4, Mips::SUBu);
Akira Hatanaka59068062011-11-11 04:14:30 +00001002 case Mips::ATOMIC_LOAD_SUB_I64:
1003 case Mips::ATOMIC_LOAD_SUB_I64_P8:
1004 return EmitAtomicBinary(MI, BB, 8, Mips::DSUBu);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001005
1006 case Mips::ATOMIC_SWAP_I8:
Akira Hatanaka59068062011-11-11 04:14:30 +00001007 case Mips::ATOMIC_SWAP_I8_P8:
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001008 return EmitAtomicBinaryPartword(MI, BB, 1, 0);
1009 case Mips::ATOMIC_SWAP_I16:
Akira Hatanaka59068062011-11-11 04:14:30 +00001010 case Mips::ATOMIC_SWAP_I16_P8:
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001011 return EmitAtomicBinaryPartword(MI, BB, 2, 0);
1012 case Mips::ATOMIC_SWAP_I32:
Akira Hatanaka59068062011-11-11 04:14:30 +00001013 case Mips::ATOMIC_SWAP_I32_P8:
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001014 return EmitAtomicBinary(MI, BB, 4, 0);
Akira Hatanaka59068062011-11-11 04:14:30 +00001015 case Mips::ATOMIC_SWAP_I64:
1016 case Mips::ATOMIC_SWAP_I64_P8:
1017 return EmitAtomicBinary(MI, BB, 8, 0);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001018
1019 case Mips::ATOMIC_CMP_SWAP_I8:
Akira Hatanaka59068062011-11-11 04:14:30 +00001020 case Mips::ATOMIC_CMP_SWAP_I8_P8:
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001021 return EmitAtomicCmpSwapPartword(MI, BB, 1);
1022 case Mips::ATOMIC_CMP_SWAP_I16:
Akira Hatanaka59068062011-11-11 04:14:30 +00001023 case Mips::ATOMIC_CMP_SWAP_I16_P8:
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001024 return EmitAtomicCmpSwapPartword(MI, BB, 2);
1025 case Mips::ATOMIC_CMP_SWAP_I32:
Akira Hatanaka59068062011-11-11 04:14:30 +00001026 case Mips::ATOMIC_CMP_SWAP_I32_P8:
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001027 return EmitAtomicCmpSwap(MI, BB, 4);
Akira Hatanaka59068062011-11-11 04:14:30 +00001028 case Mips::ATOMIC_CMP_SWAP_I64:
1029 case Mips::ATOMIC_CMP_SWAP_I64_P8:
1030 return EmitAtomicCmpSwap(MI, BB, 8);
Akira Hatanaka1d6b38d2011-03-31 18:26:17 +00001031 }
Bruno Cardoso Lopes6d399bd2008-07-29 19:05:28 +00001032}
1033
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001034// This function also handles Mips::ATOMIC_SWAP_I32 (when BinOpcode == 0), and
1035// Mips::ATOMIC_LOAD_NAND_I32 (when Nand == true)
1036MachineBasicBlock *
1037MipsTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
Eric Christopher471e4222011-06-08 23:55:35 +00001038 unsigned Size, unsigned BinOpcode,
Akira Hatanaka0f843822011-06-07 18:58:42 +00001039 bool Nand) const {
Akira Hatanaka59068062011-11-11 04:14:30 +00001040 assert((Size == 4 || Size == 8) && "Unsupported size for EmitAtomicBinary.");
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001041
1042 MachineFunction *MF = BB->getParent();
1043 MachineRegisterInfo &RegInfo = MF->getRegInfo();
Akira Hatanaka59068062011-11-11 04:14:30 +00001044 const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8));
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001045 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
1046 DebugLoc dl = MI->getDebugLoc();
Akira Hatanaka59068062011-11-11 04:14:30 +00001047 unsigned LL, SC, AND, NOR, ZERO, BEQ;
1048
1049 if (Size == 4) {
1050 LL = IsN64 ? Mips::LL_P8 : Mips::LL;
1051 SC = IsN64 ? Mips::SC_P8 : Mips::SC;
1052 AND = Mips::AND;
1053 NOR = Mips::NOR;
1054 ZERO = Mips::ZERO;
1055 BEQ = Mips::BEQ;
1056 }
1057 else {
1058 LL = IsN64 ? Mips::LLD_P8 : Mips::LLD;
1059 SC = IsN64 ? Mips::SCD_P8 : Mips::SCD;
1060 AND = Mips::AND64;
1061 NOR = Mips::NOR64;
1062 ZERO = Mips::ZERO_64;
1063 BEQ = Mips::BEQ64;
1064 }
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001065
Akira Hatanaka4061da12011-07-19 20:11:17 +00001066 unsigned OldVal = MI->getOperand(0).getReg();
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001067 unsigned Ptr = MI->getOperand(1).getReg();
1068 unsigned Incr = MI->getOperand(2).getReg();
1069
Akira Hatanaka4061da12011-07-19 20:11:17 +00001070 unsigned StoreVal = RegInfo.createVirtualRegister(RC);
1071 unsigned AndRes = RegInfo.createVirtualRegister(RC);
1072 unsigned Success = RegInfo.createVirtualRegister(RC);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001073
1074 // insert new blocks after the current block
1075 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1076 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1077 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1078 MachineFunction::iterator It = BB;
1079 ++It;
1080 MF->insert(It, loopMBB);
1081 MF->insert(It, exitMBB);
1082
1083 // Transfer the remainder of BB and its successor edges to exitMBB.
1084 exitMBB->splice(exitMBB->begin(), BB,
1085 llvm::next(MachineBasicBlock::iterator(MI)),
1086 BB->end());
1087 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
1088
1089 // thisMBB:
1090 // ...
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001091 // fallthrough --> loopMBB
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001092 BB->addSuccessor(loopMBB);
Akira Hatanaka81b44112011-07-19 17:09:53 +00001093 loopMBB->addSuccessor(loopMBB);
1094 loopMBB->addSuccessor(exitMBB);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001095
1096 // loopMBB:
1097 // ll oldval, 0(ptr)
Akira Hatanaka4061da12011-07-19 20:11:17 +00001098 // <binop> storeval, oldval, incr
1099 // sc success, storeval, 0(ptr)
1100 // beq success, $0, loopMBB
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001101 BB = loopMBB;
Akira Hatanaka59068062011-11-11 04:14:30 +00001102 BuildMI(BB, dl, TII->get(LL), OldVal).addReg(Ptr).addImm(0);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001103 if (Nand) {
Akira Hatanaka4061da12011-07-19 20:11:17 +00001104 // and andres, oldval, incr
1105 // nor storeval, $0, andres
Akira Hatanaka59068062011-11-11 04:14:30 +00001106 BuildMI(BB, dl, TII->get(AND), AndRes).addReg(OldVal).addReg(Incr);
1107 BuildMI(BB, dl, TII->get(NOR), StoreVal).addReg(ZERO).addReg(AndRes);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001108 } else if (BinOpcode) {
Akira Hatanaka4061da12011-07-19 20:11:17 +00001109 // <binop> storeval, oldval, incr
1110 BuildMI(BB, dl, TII->get(BinOpcode), StoreVal).addReg(OldVal).addReg(Incr);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001111 } else {
Akira Hatanaka4061da12011-07-19 20:11:17 +00001112 StoreVal = Incr;
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001113 }
Akira Hatanaka59068062011-11-11 04:14:30 +00001114 BuildMI(BB, dl, TII->get(SC), Success).addReg(StoreVal).addReg(Ptr).addImm(0);
1115 BuildMI(BB, dl, TII->get(BEQ)).addReg(Success).addReg(ZERO).addMBB(loopMBB);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001116
1117 MI->eraseFromParent(); // The instruction is gone now.
1118
Akira Hatanaka939ece12011-07-19 03:42:13 +00001119 return exitMBB;
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001120}
1121
1122MachineBasicBlock *
1123MipsTargetLowering::EmitAtomicBinaryPartword(MachineInstr *MI,
Akira Hatanaka0f843822011-06-07 18:58:42 +00001124 MachineBasicBlock *BB,
1125 unsigned Size, unsigned BinOpcode,
1126 bool Nand) const {
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001127 assert((Size == 1 || Size == 2) &&
1128 "Unsupported size for EmitAtomicBinaryPartial.");
1129
1130 MachineFunction *MF = BB->getParent();
1131 MachineRegisterInfo &RegInfo = MF->getRegInfo();
1132 const TargetRegisterClass *RC = getRegClassFor(MVT::i32);
1133 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
1134 DebugLoc dl = MI->getDebugLoc();
Akira Hatanaka59068062011-11-11 04:14:30 +00001135 unsigned LL = IsN64 ? Mips::LL_P8 : Mips::LL;
1136 unsigned SC = IsN64 ? Mips::SC_P8 : Mips::SC;
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001137
1138 unsigned Dest = MI->getOperand(0).getReg();
1139 unsigned Ptr = MI->getOperand(1).getReg();
1140 unsigned Incr = MI->getOperand(2).getReg();
1141
Akira Hatanaka4061da12011-07-19 20:11:17 +00001142 unsigned AlignedAddr = RegInfo.createVirtualRegister(RC);
1143 unsigned ShiftAmt = RegInfo.createVirtualRegister(RC);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001144 unsigned Mask = RegInfo.createVirtualRegister(RC);
1145 unsigned Mask2 = RegInfo.createVirtualRegister(RC);
Akira Hatanaka4061da12011-07-19 20:11:17 +00001146 unsigned NewVal = RegInfo.createVirtualRegister(RC);
1147 unsigned OldVal = RegInfo.createVirtualRegister(RC);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001148 unsigned Incr2 = RegInfo.createVirtualRegister(RC);
Akira Hatanaka4061da12011-07-19 20:11:17 +00001149 unsigned MaskLSB2 = RegInfo.createVirtualRegister(RC);
1150 unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC);
1151 unsigned MaskUpper = RegInfo.createVirtualRegister(RC);
1152 unsigned AndRes = RegInfo.createVirtualRegister(RC);
1153 unsigned BinOpRes = RegInfo.createVirtualRegister(RC);
Akira Hatanakabdd83fe2011-07-19 20:56:53 +00001154 unsigned MaskedOldVal0 = RegInfo.createVirtualRegister(RC);
Akira Hatanaka4061da12011-07-19 20:11:17 +00001155 unsigned StoreVal = RegInfo.createVirtualRegister(RC);
1156 unsigned MaskedOldVal1 = RegInfo.createVirtualRegister(RC);
1157 unsigned SrlRes = RegInfo.createVirtualRegister(RC);
1158 unsigned SllRes = RegInfo.createVirtualRegister(RC);
1159 unsigned Success = RegInfo.createVirtualRegister(RC);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001160
1161 // insert new blocks after the current block
1162 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1163 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
Akira Hatanaka939ece12011-07-19 03:42:13 +00001164 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(LLVM_BB);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001165 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1166 MachineFunction::iterator It = BB;
1167 ++It;
1168 MF->insert(It, loopMBB);
Akira Hatanaka939ece12011-07-19 03:42:13 +00001169 MF->insert(It, sinkMBB);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001170 MF->insert(It, exitMBB);
1171
1172 // Transfer the remainder of BB and its successor edges to exitMBB.
1173 exitMBB->splice(exitMBB->begin(), BB,
Akira Hatanaka82099682011-12-19 19:52:25 +00001174 llvm::next(MachineBasicBlock::iterator(MI)), BB->end());
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001175 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
1176
Akira Hatanaka81b44112011-07-19 17:09:53 +00001177 BB->addSuccessor(loopMBB);
1178 loopMBB->addSuccessor(loopMBB);
1179 loopMBB->addSuccessor(sinkMBB);
1180 sinkMBB->addSuccessor(exitMBB);
1181
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001182 // thisMBB:
Akira Hatanaka4061da12011-07-19 20:11:17 +00001183 // addiu masklsb2,$0,-4 # 0xfffffffc
1184 // and alignedaddr,ptr,masklsb2
1185 // andi ptrlsb2,ptr,3
1186 // sll shiftamt,ptrlsb2,3
1187 // ori maskupper,$0,255 # 0xff
1188 // sll mask,maskupper,shiftamt
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001189 // nor mask2,$0,mask
Akira Hatanaka4061da12011-07-19 20:11:17 +00001190 // sll incr2,incr,shiftamt
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001191
1192 int64_t MaskImm = (Size == 1) ? 255 : 65535;
Akira Hatanaka4061da12011-07-19 20:11:17 +00001193 BuildMI(BB, dl, TII->get(Mips::ADDiu), MaskLSB2)
1194 .addReg(Mips::ZERO).addImm(-4);
1195 BuildMI(BB, dl, TII->get(Mips::AND), AlignedAddr)
1196 .addReg(Ptr).addReg(MaskLSB2);
1197 BuildMI(BB, dl, TII->get(Mips::ANDi), PtrLSB2).addReg(Ptr).addImm(3);
1198 BuildMI(BB, dl, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3);
1199 BuildMI(BB, dl, TII->get(Mips::ORi), MaskUpper)
1200 .addReg(Mips::ZERO).addImm(MaskImm);
Akira Hatanakacc7ecc72011-07-19 20:34:00 +00001201 BuildMI(BB, dl, TII->get(Mips::SLLV), Mask)
1202 .addReg(ShiftAmt).addReg(MaskUpper);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001203 BuildMI(BB, dl, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask);
Akira Hatanakacc7ecc72011-07-19 20:34:00 +00001204 BuildMI(BB, dl, TII->get(Mips::SLLV), Incr2).addReg(ShiftAmt).addReg(Incr);
Bruno Cardoso Lopescada2d02011-05-31 20:25:26 +00001205
Akira Hatanaka0d7d0b52011-07-18 18:52:12 +00001206 // atomic.load.binop
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001207 // loopMBB:
Akira Hatanaka4061da12011-07-19 20:11:17 +00001208 // ll oldval,0(alignedaddr)
1209 // binop binopres,oldval,incr2
1210 // and newval,binopres,mask
1211 // and maskedoldval0,oldval,mask2
1212 // or storeval,maskedoldval0,newval
1213 // sc success,storeval,0(alignedaddr)
1214 // beq success,$0,loopMBB
1215
Akira Hatanaka0d7d0b52011-07-18 18:52:12 +00001216 // atomic.swap
1217 // loopMBB:
Akira Hatanaka4061da12011-07-19 20:11:17 +00001218 // ll oldval,0(alignedaddr)
Akira Hatanaka70564a92011-07-19 18:14:26 +00001219 // and newval,incr2,mask
Akira Hatanaka4061da12011-07-19 20:11:17 +00001220 // and maskedoldval0,oldval,mask2
1221 // or storeval,maskedoldval0,newval
1222 // sc success,storeval,0(alignedaddr)
1223 // beq success,$0,loopMBB
Akira Hatanaka0d7d0b52011-07-18 18:52:12 +00001224
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001225 BB = loopMBB;
Akira Hatanaka59068062011-11-11 04:14:30 +00001226 BuildMI(BB, dl, TII->get(LL), OldVal).addReg(AlignedAddr).addImm(0);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001227 if (Nand) {
Akira Hatanaka4061da12011-07-19 20:11:17 +00001228 // and andres, oldval, incr2
1229 // nor binopres, $0, andres
1230 // and newval, binopres, mask
1231 BuildMI(BB, dl, TII->get(Mips::AND), AndRes).addReg(OldVal).addReg(Incr2);
1232 BuildMI(BB, dl, TII->get(Mips::NOR), BinOpRes)
1233 .addReg(Mips::ZERO).addReg(AndRes);
1234 BuildMI(BB, dl, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001235 } else if (BinOpcode) {
Akira Hatanaka4061da12011-07-19 20:11:17 +00001236 // <binop> binopres, oldval, incr2
1237 // and newval, binopres, mask
1238 BuildMI(BB, dl, TII->get(BinOpcode), BinOpRes).addReg(OldVal).addReg(Incr2);
1239 BuildMI(BB, dl, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask);
Akira Hatanaka70564a92011-07-19 18:14:26 +00001240 } else {// atomic.swap
Akira Hatanaka4061da12011-07-19 20:11:17 +00001241 // and newval, incr2, mask
Akira Hatanakacc7ecc72011-07-19 20:34:00 +00001242 BuildMI(BB, dl, TII->get(Mips::AND), NewVal).addReg(Incr2).addReg(Mask);
Akira Hatanaka70564a92011-07-19 18:14:26 +00001243 }
Jia Liubb481f82012-02-28 07:46:26 +00001244
Akira Hatanakabdd83fe2011-07-19 20:56:53 +00001245 BuildMI(BB, dl, TII->get(Mips::AND), MaskedOldVal0)
Akira Hatanaka4061da12011-07-19 20:11:17 +00001246 .addReg(OldVal).addReg(Mask2);
1247 BuildMI(BB, dl, TII->get(Mips::OR), StoreVal)
Akira Hatanakabdd83fe2011-07-19 20:56:53 +00001248 .addReg(MaskedOldVal0).addReg(NewVal);
Akira Hatanaka59068062011-11-11 04:14:30 +00001249 BuildMI(BB, dl, TII->get(SC), Success)
Akira Hatanaka4061da12011-07-19 20:11:17 +00001250 .addReg(StoreVal).addReg(AlignedAddr).addImm(0);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001251 BuildMI(BB, dl, TII->get(Mips::BEQ))
Akira Hatanaka4061da12011-07-19 20:11:17 +00001252 .addReg(Success).addReg(Mips::ZERO).addMBB(loopMBB);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001253
Akira Hatanaka939ece12011-07-19 03:42:13 +00001254 // sinkMBB:
Akira Hatanaka4061da12011-07-19 20:11:17 +00001255 // and maskedoldval1,oldval,mask
1256 // srl srlres,maskedoldval1,shiftamt
1257 // sll sllres,srlres,24
1258 // sra dest,sllres,24
Akira Hatanaka939ece12011-07-19 03:42:13 +00001259 BB = sinkMBB;
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001260 int64_t ShiftImm = (Size == 1) ? 24 : 16;
Akira Hatanakaa308c672011-07-19 03:14:58 +00001261
Akira Hatanaka4061da12011-07-19 20:11:17 +00001262 BuildMI(BB, dl, TII->get(Mips::AND), MaskedOldVal1)
1263 .addReg(OldVal).addReg(Mask);
Akira Hatanakacc7ecc72011-07-19 20:34:00 +00001264 BuildMI(BB, dl, TII->get(Mips::SRLV), SrlRes)
1265 .addReg(ShiftAmt).addReg(MaskedOldVal1);
Akira Hatanaka4061da12011-07-19 20:11:17 +00001266 BuildMI(BB, dl, TII->get(Mips::SLL), SllRes)
1267 .addReg(SrlRes).addImm(ShiftImm);
Akira Hatanaka939ece12011-07-19 03:42:13 +00001268 BuildMI(BB, dl, TII->get(Mips::SRA), Dest)
Akira Hatanaka4061da12011-07-19 20:11:17 +00001269 .addReg(SllRes).addImm(ShiftImm);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001270
1271 MI->eraseFromParent(); // The instruction is gone now.
1272
Akira Hatanaka939ece12011-07-19 03:42:13 +00001273 return exitMBB;
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001274}
1275
1276MachineBasicBlock *
1277MipsTargetLowering::EmitAtomicCmpSwap(MachineInstr *MI,
Akira Hatanaka0f843822011-06-07 18:58:42 +00001278 MachineBasicBlock *BB,
1279 unsigned Size) const {
Akira Hatanaka59068062011-11-11 04:14:30 +00001280 assert((Size == 4 || Size == 8) && "Unsupported size for EmitAtomicCmpSwap.");
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001281
1282 MachineFunction *MF = BB->getParent();
1283 MachineRegisterInfo &RegInfo = MF->getRegInfo();
Akira Hatanaka59068062011-11-11 04:14:30 +00001284 const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8));
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001285 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
1286 DebugLoc dl = MI->getDebugLoc();
Akira Hatanaka59068062011-11-11 04:14:30 +00001287 unsigned LL, SC, ZERO, BNE, BEQ;
1288
1289 if (Size == 4) {
1290 LL = IsN64 ? Mips::LL_P8 : Mips::LL;
1291 SC = IsN64 ? Mips::SC_P8 : Mips::SC;
1292 ZERO = Mips::ZERO;
1293 BNE = Mips::BNE;
1294 BEQ = Mips::BEQ;
1295 }
1296 else {
1297 LL = IsN64 ? Mips::LLD_P8 : Mips::LLD;
1298 SC = IsN64 ? Mips::SCD_P8 : Mips::SCD;
1299 ZERO = Mips::ZERO_64;
1300 BNE = Mips::BNE64;
1301 BEQ = Mips::BEQ64;
1302 }
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001303
1304 unsigned Dest = MI->getOperand(0).getReg();
1305 unsigned Ptr = MI->getOperand(1).getReg();
Akira Hatanaka4061da12011-07-19 20:11:17 +00001306 unsigned OldVal = MI->getOperand(2).getReg();
1307 unsigned NewVal = MI->getOperand(3).getReg();
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001308
Akira Hatanaka4061da12011-07-19 20:11:17 +00001309 unsigned Success = RegInfo.createVirtualRegister(RC);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001310
1311 // insert new blocks after the current block
1312 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1313 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB);
1314 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB);
1315 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1316 MachineFunction::iterator It = BB;
1317 ++It;
1318 MF->insert(It, loop1MBB);
1319 MF->insert(It, loop2MBB);
1320 MF->insert(It, exitMBB);
1321
1322 // Transfer the remainder of BB and its successor edges to exitMBB.
1323 exitMBB->splice(exitMBB->begin(), BB,
Akira Hatanaka82099682011-12-19 19:52:25 +00001324 llvm::next(MachineBasicBlock::iterator(MI)), BB->end());
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001325 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
1326
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001327 // thisMBB:
1328 // ...
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001329 // fallthrough --> loop1MBB
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001330 BB->addSuccessor(loop1MBB);
Akira Hatanaka81b44112011-07-19 17:09:53 +00001331 loop1MBB->addSuccessor(exitMBB);
1332 loop1MBB->addSuccessor(loop2MBB);
1333 loop2MBB->addSuccessor(loop1MBB);
1334 loop2MBB->addSuccessor(exitMBB);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001335
1336 // loop1MBB:
1337 // ll dest, 0(ptr)
1338 // bne dest, oldval, exitMBB
1339 BB = loop1MBB;
Akira Hatanaka59068062011-11-11 04:14:30 +00001340 BuildMI(BB, dl, TII->get(LL), Dest).addReg(Ptr).addImm(0);
1341 BuildMI(BB, dl, TII->get(BNE))
Akira Hatanaka4061da12011-07-19 20:11:17 +00001342 .addReg(Dest).addReg(OldVal).addMBB(exitMBB);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001343
1344 // loop2MBB:
Akira Hatanaka4061da12011-07-19 20:11:17 +00001345 // sc success, newval, 0(ptr)
1346 // beq success, $0, loop1MBB
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001347 BB = loop2MBB;
Akira Hatanaka59068062011-11-11 04:14:30 +00001348 BuildMI(BB, dl, TII->get(SC), Success)
Akira Hatanaka4061da12011-07-19 20:11:17 +00001349 .addReg(NewVal).addReg(Ptr).addImm(0);
Akira Hatanaka59068062011-11-11 04:14:30 +00001350 BuildMI(BB, dl, TII->get(BEQ))
1351 .addReg(Success).addReg(ZERO).addMBB(loop1MBB);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001352
1353 MI->eraseFromParent(); // The instruction is gone now.
1354
Akira Hatanaka939ece12011-07-19 03:42:13 +00001355 return exitMBB;
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001356}
1357
1358MachineBasicBlock *
1359MipsTargetLowering::EmitAtomicCmpSwapPartword(MachineInstr *MI,
Akira Hatanaka0f843822011-06-07 18:58:42 +00001360 MachineBasicBlock *BB,
1361 unsigned Size) const {
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001362 assert((Size == 1 || Size == 2) &&
1363 "Unsupported size for EmitAtomicCmpSwapPartial.");
1364
1365 MachineFunction *MF = BB->getParent();
1366 MachineRegisterInfo &RegInfo = MF->getRegInfo();
1367 const TargetRegisterClass *RC = getRegClassFor(MVT::i32);
1368 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
1369 DebugLoc dl = MI->getDebugLoc();
Akira Hatanaka59068062011-11-11 04:14:30 +00001370 unsigned LL = IsN64 ? Mips::LL_P8 : Mips::LL;
1371 unsigned SC = IsN64 ? Mips::SC_P8 : Mips::SC;
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001372
1373 unsigned Dest = MI->getOperand(0).getReg();
1374 unsigned Ptr = MI->getOperand(1).getReg();
Akira Hatanaka4061da12011-07-19 20:11:17 +00001375 unsigned CmpVal = MI->getOperand(2).getReg();
1376 unsigned NewVal = MI->getOperand(3).getReg();
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001377
Akira Hatanaka4061da12011-07-19 20:11:17 +00001378 unsigned AlignedAddr = RegInfo.createVirtualRegister(RC);
1379 unsigned ShiftAmt = RegInfo.createVirtualRegister(RC);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001380 unsigned Mask = RegInfo.createVirtualRegister(RC);
1381 unsigned Mask2 = RegInfo.createVirtualRegister(RC);
Akira Hatanaka4061da12011-07-19 20:11:17 +00001382 unsigned ShiftedCmpVal = RegInfo.createVirtualRegister(RC);
1383 unsigned OldVal = RegInfo.createVirtualRegister(RC);
1384 unsigned MaskedOldVal0 = RegInfo.createVirtualRegister(RC);
1385 unsigned ShiftedNewVal = RegInfo.createVirtualRegister(RC);
1386 unsigned MaskLSB2 = RegInfo.createVirtualRegister(RC);
1387 unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC);
1388 unsigned MaskUpper = RegInfo.createVirtualRegister(RC);
1389 unsigned MaskedCmpVal = RegInfo.createVirtualRegister(RC);
1390 unsigned MaskedNewVal = RegInfo.createVirtualRegister(RC);
1391 unsigned MaskedOldVal1 = RegInfo.createVirtualRegister(RC);
1392 unsigned StoreVal = RegInfo.createVirtualRegister(RC);
1393 unsigned SrlRes = RegInfo.createVirtualRegister(RC);
1394 unsigned SllRes = RegInfo.createVirtualRegister(RC);
1395 unsigned Success = RegInfo.createVirtualRegister(RC);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001396
1397 // insert new blocks after the current block
1398 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1399 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB);
1400 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB);
Akira Hatanaka939ece12011-07-19 03:42:13 +00001401 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(LLVM_BB);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001402 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1403 MachineFunction::iterator It = BB;
1404 ++It;
1405 MF->insert(It, loop1MBB);
1406 MF->insert(It, loop2MBB);
Akira Hatanaka939ece12011-07-19 03:42:13 +00001407 MF->insert(It, sinkMBB);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001408 MF->insert(It, exitMBB);
1409
1410 // Transfer the remainder of BB and its successor edges to exitMBB.
1411 exitMBB->splice(exitMBB->begin(), BB,
Akira Hatanaka82099682011-12-19 19:52:25 +00001412 llvm::next(MachineBasicBlock::iterator(MI)), BB->end());
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001413 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
1414
Akira Hatanaka81b44112011-07-19 17:09:53 +00001415 BB->addSuccessor(loop1MBB);
1416 loop1MBB->addSuccessor(sinkMBB);
1417 loop1MBB->addSuccessor(loop2MBB);
1418 loop2MBB->addSuccessor(loop1MBB);
1419 loop2MBB->addSuccessor(sinkMBB);
1420 sinkMBB->addSuccessor(exitMBB);
1421
Akira Hatanaka70564a92011-07-19 18:14:26 +00001422 // FIXME: computation of newval2 can be moved to loop2MBB.
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001423 // thisMBB:
Akira Hatanaka4061da12011-07-19 20:11:17 +00001424 // addiu masklsb2,$0,-4 # 0xfffffffc
1425 // and alignedaddr,ptr,masklsb2
1426 // andi ptrlsb2,ptr,3
1427 // sll shiftamt,ptrlsb2,3
1428 // ori maskupper,$0,255 # 0xff
1429 // sll mask,maskupper,shiftamt
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001430 // nor mask2,$0,mask
Akira Hatanaka4061da12011-07-19 20:11:17 +00001431 // andi maskedcmpval,cmpval,255
1432 // sll shiftedcmpval,maskedcmpval,shiftamt
1433 // andi maskednewval,newval,255
1434 // sll shiftednewval,maskednewval,shiftamt
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001435 int64_t MaskImm = (Size == 1) ? 255 : 65535;
Akira Hatanaka4061da12011-07-19 20:11:17 +00001436 BuildMI(BB, dl, TII->get(Mips::ADDiu), MaskLSB2)
1437 .addReg(Mips::ZERO).addImm(-4);
1438 BuildMI(BB, dl, TII->get(Mips::AND), AlignedAddr)
1439 .addReg(Ptr).addReg(MaskLSB2);
1440 BuildMI(BB, dl, TII->get(Mips::ANDi), PtrLSB2).addReg(Ptr).addImm(3);
1441 BuildMI(BB, dl, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3);
1442 BuildMI(BB, dl, TII->get(Mips::ORi), MaskUpper)
1443 .addReg(Mips::ZERO).addImm(MaskImm);
Akira Hatanakacc7ecc72011-07-19 20:34:00 +00001444 BuildMI(BB, dl, TII->get(Mips::SLLV), Mask)
1445 .addReg(ShiftAmt).addReg(MaskUpper);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001446 BuildMI(BB, dl, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask);
Akira Hatanaka4061da12011-07-19 20:11:17 +00001447 BuildMI(BB, dl, TII->get(Mips::ANDi), MaskedCmpVal)
1448 .addReg(CmpVal).addImm(MaskImm);
Akira Hatanakacc7ecc72011-07-19 20:34:00 +00001449 BuildMI(BB, dl, TII->get(Mips::SLLV), ShiftedCmpVal)
1450 .addReg(ShiftAmt).addReg(MaskedCmpVal);
Akira Hatanaka4061da12011-07-19 20:11:17 +00001451 BuildMI(BB, dl, TII->get(Mips::ANDi), MaskedNewVal)
1452 .addReg(NewVal).addImm(MaskImm);
Akira Hatanakacc7ecc72011-07-19 20:34:00 +00001453 BuildMI(BB, dl, TII->get(Mips::SLLV), ShiftedNewVal)
1454 .addReg(ShiftAmt).addReg(MaskedNewVal);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001455
1456 // loop1MBB:
Akira Hatanaka4061da12011-07-19 20:11:17 +00001457 // ll oldval,0(alginedaddr)
1458 // and maskedoldval0,oldval,mask
1459 // bne maskedoldval0,shiftedcmpval,sinkMBB
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001460 BB = loop1MBB;
Akira Hatanaka59068062011-11-11 04:14:30 +00001461 BuildMI(BB, dl, TII->get(LL), OldVal).addReg(AlignedAddr).addImm(0);
Akira Hatanaka4061da12011-07-19 20:11:17 +00001462 BuildMI(BB, dl, TII->get(Mips::AND), MaskedOldVal0)
1463 .addReg(OldVal).addReg(Mask);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001464 BuildMI(BB, dl, TII->get(Mips::BNE))
Akira Hatanaka4061da12011-07-19 20:11:17 +00001465 .addReg(MaskedOldVal0).addReg(ShiftedCmpVal).addMBB(sinkMBB);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001466
1467 // loop2MBB:
Akira Hatanaka4061da12011-07-19 20:11:17 +00001468 // and maskedoldval1,oldval,mask2
1469 // or storeval,maskedoldval1,shiftednewval
1470 // sc success,storeval,0(alignedaddr)
1471 // beq success,$0,loop1MBB
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001472 BB = loop2MBB;
Akira Hatanaka4061da12011-07-19 20:11:17 +00001473 BuildMI(BB, dl, TII->get(Mips::AND), MaskedOldVal1)
1474 .addReg(OldVal).addReg(Mask2);
1475 BuildMI(BB, dl, TII->get(Mips::OR), StoreVal)
1476 .addReg(MaskedOldVal1).addReg(ShiftedNewVal);
Akira Hatanaka59068062011-11-11 04:14:30 +00001477 BuildMI(BB, dl, TII->get(SC), Success)
Akira Hatanaka4061da12011-07-19 20:11:17 +00001478 .addReg(StoreVal).addReg(AlignedAddr).addImm(0);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001479 BuildMI(BB, dl, TII->get(Mips::BEQ))
Akira Hatanaka4061da12011-07-19 20:11:17 +00001480 .addReg(Success).addReg(Mips::ZERO).addMBB(loop1MBB);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001481
Akira Hatanaka939ece12011-07-19 03:42:13 +00001482 // sinkMBB:
Akira Hatanaka4061da12011-07-19 20:11:17 +00001483 // srl srlres,maskedoldval0,shiftamt
1484 // sll sllres,srlres,24
1485 // sra dest,sllres,24
Akira Hatanaka939ece12011-07-19 03:42:13 +00001486 BB = sinkMBB;
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001487 int64_t ShiftImm = (Size == 1) ? 24 : 16;
Akira Hatanakaa308c672011-07-19 03:14:58 +00001488
Akira Hatanakacc7ecc72011-07-19 20:34:00 +00001489 BuildMI(BB, dl, TII->get(Mips::SRLV), SrlRes)
1490 .addReg(ShiftAmt).addReg(MaskedOldVal0);
Akira Hatanaka4061da12011-07-19 20:11:17 +00001491 BuildMI(BB, dl, TII->get(Mips::SLL), SllRes)
1492 .addReg(SrlRes).addImm(ShiftImm);
Akira Hatanaka939ece12011-07-19 03:42:13 +00001493 BuildMI(BB, dl, TII->get(Mips::SRA), Dest)
Akira Hatanaka4061da12011-07-19 20:11:17 +00001494 .addReg(SllRes).addImm(ShiftImm);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001495
1496 MI->eraseFromParent(); // The instruction is gone now.
1497
Akira Hatanaka939ece12011-07-19 03:42:13 +00001498 return exitMBB;
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001499}
1500
Akira Hatanaka4552c9a2011-04-15 21:51:11 +00001501//===----------------------------------------------------------------------===//
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00001502// Misc Lower Operation implementation
Akira Hatanaka4552c9a2011-04-15 21:51:11 +00001503//===----------------------------------------------------------------------===//
Bruno Cardoso Lopesd3bdf192009-05-27 17:23:44 +00001504SDValue MipsTargetLowering::
Dan Gohmand858e902010-04-17 15:26:15 +00001505LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const
Bruno Cardoso Lopes7da151c2008-08-07 19:08:11 +00001506{
Akira Hatanaka21afc632011-06-21 00:40:49 +00001507 MachineFunction &MF = DAG.getMachineFunction();
1508 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
Akira Hatanakac742e4f2011-11-11 04:06:38 +00001509 unsigned SP = IsN64 ? Mips::SP_64 : Mips::SP;
Akira Hatanaka21afc632011-06-21 00:40:49 +00001510
1511 assert(getTargetMachine().getFrameLowering()->getStackAlignment() >=
Akira Hatanaka053546c2011-05-25 02:20:00 +00001512 cast<ConstantSDNode>(Op.getOperand(2).getNode())->getZExtValue() &&
1513 "Cannot lower if the alignment of the allocated space is larger than \
1514 that of the stack.");
1515
Bruno Cardoso Lopes7da151c2008-08-07 19:08:11 +00001516 SDValue Chain = Op.getOperand(0);
1517 SDValue Size = Op.getOperand(1);
Dale Johannesena05dca42009-02-04 23:02:30 +00001518 DebugLoc dl = Op.getDebugLoc();
Bruno Cardoso Lopes7da151c2008-08-07 19:08:11 +00001519
1520 // Get a reference from Mips stack pointer
Akira Hatanakac742e4f2011-11-11 04:06:38 +00001521 SDValue StackPointer = DAG.getCopyFromReg(Chain, dl, SP, getPointerTy());
Bruno Cardoso Lopes7da151c2008-08-07 19:08:11 +00001522
1523 // Subtract the dynamic size from the actual stack size to
1524 // obtain the new stack size.
Akira Hatanakac742e4f2011-11-11 04:06:38 +00001525 SDValue Sub = DAG.getNode(ISD::SUB, dl, getPointerTy(), StackPointer, Size);
Bruno Cardoso Lopes7da151c2008-08-07 19:08:11 +00001526
Wesley Peckbf17cfa2010-11-23 03:31:01 +00001527 // The Sub result contains the new stack start address, so it
Bruno Cardoso Lopes7da151c2008-08-07 19:08:11 +00001528 // must be placed in the stack pointer register.
Akira Hatanakac742e4f2011-11-11 04:06:38 +00001529 Chain = DAG.getCopyToReg(StackPointer.getValue(1), dl, SP, Sub, SDValue());
Wesley Peckbf17cfa2010-11-23 03:31:01 +00001530
1531 // This node always has two return values: a new stack pointer
Bruno Cardoso Lopes7da151c2008-08-07 19:08:11 +00001532 // value and a chain
Akira Hatanakac742e4f2011-11-11 04:06:38 +00001533 SDVTList VTLs = DAG.getVTList(getPointerTy(), MVT::Other);
Akira Hatanaka21afc632011-06-21 00:40:49 +00001534 SDValue Ptr = DAG.getFrameIndex(MipsFI->getDynAllocFI(), getPointerTy());
1535 SDValue Ops[] = { Chain, Ptr, Chain.getValue(1) };
1536
1537 return DAG.getNode(MipsISD::DynAlloc, dl, VTLs, Ops, 3);
Bruno Cardoso Lopes7da151c2008-08-07 19:08:11 +00001538}
1539
1540SDValue MipsTargetLowering::
Dan Gohmand858e902010-04-17 15:26:15 +00001541LowerBRCOND(SDValue Op, SelectionDAG &DAG) const
Bruno Cardoso Lopes85e31e32008-07-28 19:11:24 +00001542{
Wesley Peckbf17cfa2010-11-23 03:31:01 +00001543 // The first operand is the chain, the second is the condition, the third is
Bruno Cardoso Lopes85e31e32008-07-28 19:11:24 +00001544 // the block to branch to if the condition is true.
1545 SDValue Chain = Op.getOperand(0);
1546 SDValue Dest = Op.getOperand(2);
Dale Johannesende064702009-02-06 21:50:26 +00001547 DebugLoc dl = Op.getDebugLoc();
Bruno Cardoso Lopes85e31e32008-07-28 19:11:24 +00001548
Akira Hatanaka1d6b38d2011-03-31 18:26:17 +00001549 SDValue CondRes = CreateFPCmp(DAG, Op.getOperand(1));
1550
Chris Lattner7a2bdde2011-04-15 05:18:47 +00001551 // Return if flag is not set by a floating point comparison.
Akira Hatanaka1d6b38d2011-03-31 18:26:17 +00001552 if (CondRes.getOpcode() != MipsISD::FPCmp)
Bruno Cardoso Lopes4b877ca2008-07-30 17:06:13 +00001553 return Op;
Wesley Peckbf17cfa2010-11-23 03:31:01 +00001554
Bruno Cardoso Lopes77283772008-07-31 18:31:28 +00001555 SDValue CCNode = CondRes.getOperand(2);
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +00001556 Mips::CondCode CC =
1557 (Mips::CondCode)cast<ConstantSDNode>(CCNode)->getZExtValue();
Wesley Peckbf17cfa2010-11-23 03:31:01 +00001558 SDValue BrCode = DAG.getConstant(GetFPBranchCodeFromCond(CC), MVT::i32);
Bruno Cardoso Lopes85e31e32008-07-28 19:11:24 +00001559
Wesley Peckbf17cfa2010-11-23 03:31:01 +00001560 return DAG.getNode(MipsISD::FPBrcond, dl, Op.getValueType(), Chain, BrCode,
Akira Hatanaka1d6b38d2011-03-31 18:26:17 +00001561 Dest, CondRes);
Bruno Cardoso Lopes85e31e32008-07-28 19:11:24 +00001562}
1563
1564SDValue MipsTargetLowering::
Dan Gohmand858e902010-04-17 15:26:15 +00001565LowerSELECT(SDValue Op, SelectionDAG &DAG) const
Bruno Cardoso Lopes6d399bd2008-07-29 19:05:28 +00001566{
Akira Hatanaka1d6b38d2011-03-31 18:26:17 +00001567 SDValue Cond = CreateFPCmp(DAG, Op.getOperand(0));
Bruno Cardoso Lopes6d399bd2008-07-29 19:05:28 +00001568
Chris Lattner7a2bdde2011-04-15 05:18:47 +00001569 // Return if flag is not set by a floating point comparison.
Akira Hatanaka1d6b38d2011-03-31 18:26:17 +00001570 if (Cond.getOpcode() != MipsISD::FPCmp)
1571 return Op;
Bruno Cardoso Lopes739e4412008-08-13 07:13:40 +00001572
Akira Hatanaka1d6b38d2011-03-31 18:26:17 +00001573 return CreateCMovFP(DAG, Cond, Op.getOperand(1), Op.getOperand(2),
1574 Op.getDebugLoc());
Bruno Cardoso Lopes6d399bd2008-07-29 19:05:28 +00001575}
1576
Akira Hatanaka3fef29d2012-07-11 19:32:27 +00001577SDValue MipsTargetLowering::
1578LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const
1579{
1580 DebugLoc DL = Op.getDebugLoc();
1581 EVT Ty = Op.getOperand(0).getValueType();
1582 SDValue Cond = DAG.getNode(ISD::SETCC, DL, getSetCCResultType(Ty),
1583 Op.getOperand(0), Op.getOperand(1),
1584 Op.getOperand(4));
1585
1586 return DAG.getNode(ISD::SELECT, DL, Op.getValueType(), Cond, Op.getOperand(2),
1587 Op.getOperand(3));
1588}
1589
Akira Hatanaka0a40c232012-03-09 23:46:03 +00001590SDValue MipsTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
1591 SDValue Cond = CreateFPCmp(DAG, Op);
1592
1593 assert(Cond.getOpcode() == MipsISD::FPCmp &&
1594 "Floating point operand expected.");
1595
1596 SDValue True = DAG.getConstant(1, MVT::i32);
1597 SDValue False = DAG.getConstant(0, MVT::i32);
1598
1599 return CreateCMovFP(DAG, Cond, True, False, Op.getDebugLoc());
1600}
1601
Dan Gohmand858e902010-04-17 15:26:15 +00001602SDValue MipsTargetLowering::LowerGlobalAddress(SDValue Op,
1603 SelectionDAG &DAG) const {
Dale Johannesende064702009-02-06 21:50:26 +00001604 // FIXME there isn't actually debug info here
Dale Johannesen33c960f2009-02-04 20:06:27 +00001605 DebugLoc dl = Op.getDebugLoc();
Jia Liubb481f82012-02-28 07:46:26 +00001606 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
Bruno Cardoso Lopes97843cd2008-07-29 19:29:50 +00001607
Akira Hatanakaa5903ac2011-10-11 00:55:05 +00001608 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !IsN64) {
Chris Lattnere3736f82009-08-13 05:41:27 +00001609 SDVTList VTs = DAG.getVTList(MVT::i32);
Wesley Peckbf17cfa2010-11-23 03:31:01 +00001610
Chris Lattnerb71b9092009-08-13 06:28:06 +00001611 MipsTargetObjectFile &TLOF = (MipsTargetObjectFile&)getObjFileLowering();
Wesley Peckbf17cfa2010-11-23 03:31:01 +00001612
Chris Lattnere3736f82009-08-13 05:41:27 +00001613 // %gp_rel relocation
Wesley Peckbf17cfa2010-11-23 03:31:01 +00001614 if (TLOF.IsGlobalInSmallSection(GV, getTargetMachine())) {
1615 SDValue GA = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0,
Bruno Cardoso Lopesc517cb02009-09-01 17:27:58 +00001616 MipsII::MO_GPREL);
Chris Lattnere3736f82009-08-13 05:41:27 +00001617 SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, dl, VTs, &GA, 1);
1618 SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(MVT::i32);
Wesley Peckbf17cfa2010-11-23 03:31:01 +00001619 return DAG.getNode(ISD::ADD, dl, MVT::i32, GOT, GPRelNode);
Chris Lattnere3736f82009-08-13 05:41:27 +00001620 }
Bruno Cardoso Lopes97843cd2008-07-29 19:29:50 +00001621 // %hi/%lo relocation
Akira Hatanakae2e436a2011-04-01 21:41:06 +00001622 SDValue GAHi = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0,
1623 MipsII::MO_ABS_HI);
1624 SDValue GALo = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0,
1625 MipsII::MO_ABS_LO);
1626 SDValue HiPart = DAG.getNode(MipsISD::Hi, dl, VTs, &GAHi, 1);
1627 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, GALo);
Owen Anderson825b72b2009-08-11 20:47:22 +00001628 return DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo);
Bruno Cardoso Lopes97843cd2008-07-29 19:29:50 +00001629 }
1630
Akira Hatanakaa5903ac2011-10-11 00:55:05 +00001631 EVT ValTy = Op.getValueType();
1632 bool HasGotOfst = (GV->hasInternalLinkage() ||
1633 (GV->hasLocalLinkage() && !isa<Function>(GV)));
Akira Hatanaka56ce6b32012-04-04 22:16:36 +00001634 unsigned GotFlag = HasMips64 ?
Akira Hatanakaa5903ac2011-10-11 00:55:05 +00001635 (HasGotOfst ? MipsII::MO_GOT_PAGE : MipsII::MO_GOT_DISP) :
Bruno Cardoso Lopese3d35722011-12-07 00:28:57 +00001636 (HasGotOfst ? MipsII::MO_GOT : MipsII::MO_GOT16);
Akira Hatanakaa5903ac2011-10-11 00:55:05 +00001637 SDValue GA = DAG.getTargetGlobalAddress(GV, dl, ValTy, 0, GotFlag);
Akira Hatanaka648f00c2012-02-24 22:34:47 +00001638 GA = DAG.getNode(MipsISD::Wrapper, dl, ValTy, GetGlobalReg(DAG, ValTy), GA);
Akira Hatanaka82099682011-12-19 19:52:25 +00001639 SDValue ResNode = DAG.getLoad(ValTy, dl, DAG.getEntryNode(), GA,
1640 MachinePointerInfo(), false, false, false, 0);
Akira Hatanaka0f843822011-06-07 18:58:42 +00001641 // On functions and global targets not internal linked only
1642 // a load from got/GP is necessary for PIC to work.
Akira Hatanakaa5903ac2011-10-11 00:55:05 +00001643 if (!HasGotOfst)
Akira Hatanaka0f843822011-06-07 18:58:42 +00001644 return ResNode;
Akira Hatanakaa5903ac2011-10-11 00:55:05 +00001645 SDValue GALo = DAG.getTargetGlobalAddress(GV, dl, ValTy, 0,
Akira Hatanaka56ce6b32012-04-04 22:16:36 +00001646 HasMips64 ? MipsII::MO_GOT_OFST :
1647 MipsII::MO_ABS_LO);
Akira Hatanakaa5903ac2011-10-11 00:55:05 +00001648 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, ValTy, GALo);
1649 return DAG.getNode(ISD::ADD, dl, ValTy, ResNode, Lo);
Bruno Cardoso Lopes97843cd2008-07-29 19:29:50 +00001650}
1651
Bruno Cardoso Lopesca8a2aa2011-03-04 20:01:52 +00001652SDValue MipsTargetLowering::LowerBlockAddress(SDValue Op,
1653 SelectionDAG &DAG) const {
Akira Hatanakaf48eb532011-04-25 17:10:45 +00001654 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
1655 // FIXME there isn't actually debug info here
1656 DebugLoc dl = Op.getDebugLoc();
1657
Akira Hatanaka9b944a82011-11-16 22:42:10 +00001658 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !IsN64) {
Akira Hatanakaf48eb532011-04-25 17:10:45 +00001659 // %hi/%lo relocation
Akira Hatanaka82099682011-12-19 19:52:25 +00001660 SDValue BAHi = DAG.getBlockAddress(BA, MVT::i32, true, MipsII::MO_ABS_HI);
1661 SDValue BALo = DAG.getBlockAddress(BA, MVT::i32, true, MipsII::MO_ABS_LO);
Akira Hatanakaf48eb532011-04-25 17:10:45 +00001662 SDValue Hi = DAG.getNode(MipsISD::Hi, dl, MVT::i32, BAHi);
1663 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, BALo);
1664 return DAG.getNode(ISD::ADD, dl, MVT::i32, Hi, Lo);
Bruno Cardoso Lopesca8a2aa2011-03-04 20:01:52 +00001665 }
Akira Hatanakaf48eb532011-04-25 17:10:45 +00001666
Akira Hatanaka9b944a82011-11-16 22:42:10 +00001667 EVT ValTy = Op.getValueType();
Akira Hatanaka03d830e2012-04-04 18:22:53 +00001668 unsigned GOTFlag = HasMips64 ? MipsII::MO_GOT_PAGE : MipsII::MO_GOT;
1669 unsigned OFSTFlag = HasMips64 ? MipsII::MO_GOT_OFST : MipsII::MO_ABS_LO;
Akira Hatanaka9b944a82011-11-16 22:42:10 +00001670 SDValue BAGOTOffset = DAG.getBlockAddress(BA, ValTy, true, GOTFlag);
Akira Hatanaka648f00c2012-02-24 22:34:47 +00001671 BAGOTOffset = DAG.getNode(MipsISD::Wrapper, dl, ValTy,
1672 GetGlobalReg(DAG, ValTy), BAGOTOffset);
Akira Hatanaka9b944a82011-11-16 22:42:10 +00001673 SDValue BALOOffset = DAG.getBlockAddress(BA, ValTy, true, OFSTFlag);
Akira Hatanaka82099682011-12-19 19:52:25 +00001674 SDValue Load = DAG.getLoad(ValTy, dl, DAG.getEntryNode(), BAGOTOffset,
Pete Cooperd752e0f2011-11-08 18:42:53 +00001675 MachinePointerInfo(), false, false, false, 0);
Akira Hatanaka9b944a82011-11-16 22:42:10 +00001676 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, ValTy, BALOOffset);
1677 return DAG.getNode(ISD::ADD, dl, ValTy, Load, Lo);
Bruno Cardoso Lopesca8a2aa2011-03-04 20:01:52 +00001678}
1679
Bruno Cardoso Lopes97843cd2008-07-29 19:29:50 +00001680SDValue MipsTargetLowering::
Dan Gohmand858e902010-04-17 15:26:15 +00001681LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const
Bruno Cardoso Lopes97843cd2008-07-29 19:29:50 +00001682{
Akira Hatanaka3faac0a2011-12-14 18:26:41 +00001683 // If the relocation model is PIC, use the General Dynamic TLS Model or
1684 // Local Dynamic TLS model, otherwise use the Initial Exec or
1685 // Local Exec TLS Model.
Bruno Cardoso Lopesd9796862011-05-31 02:53:58 +00001686
1687 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
1688 DebugLoc dl = GA->getDebugLoc();
1689 const GlobalValue *GV = GA->getGlobal();
1690 EVT PtrVT = getPointerTy();
1691
Hans Wennborgfd5abd52012-05-04 09:40:39 +00001692 TLSModel::Model model = getTargetMachine().getTLSModel(GV);
1693
1694 if (model == TLSModel::GeneralDynamic || model == TLSModel::LocalDynamic) {
Hans Wennborg70a07c72012-06-04 14:02:08 +00001695 // General Dynamic and Local Dynamic TLS Model.
1696 unsigned Flag = (model == TLSModel::LocalDynamic) ? MipsII::MO_TLSLDM
1697 : MipsII::MO_TLSGD;
1698
Akira Hatanaka3faac0a2011-12-14 18:26:41 +00001699 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, Flag);
Akira Hatanaka648f00c2012-02-24 22:34:47 +00001700 SDValue Argument = DAG.getNode(MipsISD::Wrapper, dl, PtrVT,
1701 GetGlobalReg(DAG, PtrVT), TGA);
Akira Hatanaka7a7194b2011-12-08 21:05:38 +00001702 unsigned PtrSize = PtrVT.getSizeInBits();
1703 IntegerType *PtrTy = Type::getIntNTy(*DAG.getContext(), PtrSize);
1704
Benjamin Kramer5eccf672011-12-11 12:21:34 +00001705 SDValue TlsGetAddr = DAG.getExternalSymbol("__tls_get_addr", PtrVT);
Bruno Cardoso Lopesd9796862011-05-31 02:53:58 +00001706
1707 ArgListTy Args;
1708 ArgListEntry Entry;
1709 Entry.Node = Argument;
Akira Hatanakaca074792011-12-08 20:34:32 +00001710 Entry.Ty = PtrTy;
Bruno Cardoso Lopesd9796862011-05-31 02:53:58 +00001711 Args.push_back(Entry);
Jia Liubb481f82012-02-28 07:46:26 +00001712
Justin Holewinskid2ea0e12012-05-25 16:35:28 +00001713 TargetLowering::CallLoweringInfo CLI(DAG.getEntryNode(), PtrTy,
Evan Cheng4bfcd4a2012-02-28 18:51:51 +00001714 false, false, false, false, 0, CallingConv::C,
1715 /*isTailCall=*/false, /*doesNotRet=*/false,
1716 /*isReturnValueUsed=*/true,
Akira Hatanaka7a7194b2011-12-08 21:05:38 +00001717 TlsGetAddr, Args, DAG, dl);
Justin Holewinskid2ea0e12012-05-25 16:35:28 +00001718 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
Bruno Cardoso Lopesd9796862011-05-31 02:53:58 +00001719
Akira Hatanaka3faac0a2011-12-14 18:26:41 +00001720 SDValue Ret = CallResult.first;
1721
Hans Wennborgfd5abd52012-05-04 09:40:39 +00001722 if (model != TLSModel::LocalDynamic)
Akira Hatanaka3faac0a2011-12-14 18:26:41 +00001723 return Ret;
1724
1725 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1726 MipsII::MO_DTPREL_HI);
1727 SDValue Hi = DAG.getNode(MipsISD::Hi, dl, PtrVT, TGAHi);
1728 SDValue TGALo = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1729 MipsII::MO_DTPREL_LO);
1730 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, PtrVT, TGALo);
1731 SDValue Add = DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Ret);
1732 return DAG.getNode(ISD::ADD, dl, PtrVT, Add, Lo);
Bruno Cardoso Lopesd9796862011-05-31 02:53:58 +00001733 }
Akira Hatanaka5f7451f2011-06-21 01:02:03 +00001734
1735 SDValue Offset;
Hans Wennborgfd5abd52012-05-04 09:40:39 +00001736 if (model == TLSModel::InitialExec) {
Akira Hatanaka5f7451f2011-06-21 01:02:03 +00001737 // Initial Exec TLS Model
Akira Hatanakaca074792011-12-08 20:34:32 +00001738 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
Akira Hatanaka5f7451f2011-06-21 01:02:03 +00001739 MipsII::MO_GOTTPREL);
Akira Hatanaka648f00c2012-02-24 22:34:47 +00001740 TGA = DAG.getNode(MipsISD::Wrapper, dl, PtrVT, GetGlobalReg(DAG, PtrVT),
1741 TGA);
Akira Hatanakaca074792011-12-08 20:34:32 +00001742 Offset = DAG.getLoad(PtrVT, dl,
Akira Hatanaka5f7451f2011-06-21 01:02:03 +00001743 DAG.getEntryNode(), TGA, MachinePointerInfo(),
Pete Cooperd752e0f2011-11-08 18:42:53 +00001744 false, false, false, 0);
Akira Hatanaka5f7451f2011-06-21 01:02:03 +00001745 } else {
1746 // Local Exec TLS Model
Hans Wennborgfd5abd52012-05-04 09:40:39 +00001747 assert(model == TLSModel::LocalExec);
Akira Hatanakaca074792011-12-08 20:34:32 +00001748 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
Akira Hatanaka5f7451f2011-06-21 01:02:03 +00001749 MipsII::MO_TPREL_HI);
Akira Hatanakaca074792011-12-08 20:34:32 +00001750 SDValue TGALo = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
Akira Hatanaka5f7451f2011-06-21 01:02:03 +00001751 MipsII::MO_TPREL_LO);
Akira Hatanakaca074792011-12-08 20:34:32 +00001752 SDValue Hi = DAG.getNode(MipsISD::Hi, dl, PtrVT, TGAHi);
1753 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, PtrVT, TGALo);
1754 Offset = DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Lo);
Akira Hatanaka5f7451f2011-06-21 01:02:03 +00001755 }
1756
1757 SDValue ThreadPointer = DAG.getNode(MipsISD::ThreadPointer, dl, PtrVT);
1758 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
Bruno Cardoso Lopes97843cd2008-07-29 19:29:50 +00001759}
1760
1761SDValue MipsTargetLowering::
Dan Gohmand858e902010-04-17 15:26:15 +00001762LowerJumpTable(SDValue Op, SelectionDAG &DAG) const
Bruno Cardoso Lopes753a9872007-11-12 19:49:57 +00001763{
Akira Hatanaka2bf08ec2011-12-05 21:03:03 +00001764 SDValue HiPart, JTI, JTILo;
Dale Johannesende064702009-02-06 21:50:26 +00001765 // FIXME there isn't actually debug info here
Dale Johannesen33c960f2009-02-04 20:06:27 +00001766 DebugLoc dl = Op.getDebugLoc();
Bruno Cardoso Lopesc517cb02009-09-01 17:27:58 +00001767 bool IsPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_;
Owen Andersone50ed302009-08-10 22:56:29 +00001768 EVT PtrVT = Op.getValueType();
Akira Hatanaka2bf08ec2011-12-05 21:03:03 +00001769 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
Bruno Cardoso Lopes753a9872007-11-12 19:49:57 +00001770
Akira Hatanaka2bf08ec2011-12-05 21:03:03 +00001771 if (!IsPIC && !IsN64) {
1772 JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MipsII::MO_ABS_HI);
1773 HiPart = DAG.getNode(MipsISD::Hi, dl, PtrVT, JTI);
1774 JTILo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MipsII::MO_ABS_LO);
Akira Hatanaka342837d2011-05-28 01:07:07 +00001775 } else {// Emit Load from Global Pointer
Akira Hatanakac75ceb72012-04-04 18:31:32 +00001776 unsigned GOTFlag = HasMips64 ? MipsII::MO_GOT_PAGE : MipsII::MO_GOT;
1777 unsigned OfstFlag = HasMips64 ? MipsII::MO_GOT_OFST : MipsII::MO_ABS_LO;
Akira Hatanaka2bf08ec2011-12-05 21:03:03 +00001778 JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, GOTFlag);
Akira Hatanaka648f00c2012-02-24 22:34:47 +00001779 JTI = DAG.getNode(MipsISD::Wrapper, dl, PtrVT, GetGlobalReg(DAG, PtrVT),
1780 JTI);
Akira Hatanaka2bf08ec2011-12-05 21:03:03 +00001781 HiPart = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), JTI,
1782 MachinePointerInfo(), false, false, false, 0);
1783 JTILo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, OfstFlag);
Akira Hatanaka342837d2011-05-28 01:07:07 +00001784 }
Bruno Cardoso Lopes753a9872007-11-12 19:49:57 +00001785
Akira Hatanaka2bf08ec2011-12-05 21:03:03 +00001786 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, PtrVT, JTILo);
1787 return DAG.getNode(ISD::ADD, dl, PtrVT, HiPart, Lo);
Bruno Cardoso Lopes753a9872007-11-12 19:49:57 +00001788}
1789
Dan Gohman475871a2008-07-27 21:46:04 +00001790SDValue MipsTargetLowering::
Dan Gohmand858e902010-04-17 15:26:15 +00001791LowerConstantPool(SDValue Op, SelectionDAG &DAG) const
Bruno Cardoso Lopes97c25372008-07-09 04:15:08 +00001792{
Dan Gohman475871a2008-07-27 21:46:04 +00001793 SDValue ResNode;
Bruno Cardoso Lopes92e87f22008-07-23 16:01:50 +00001794 ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op);
Dan Gohman46510a72010-04-15 01:51:59 +00001795 const Constant *C = N->getConstVal();
Dale Johannesende064702009-02-06 21:50:26 +00001796 // FIXME there isn't actually debug info here
1797 DebugLoc dl = Op.getDebugLoc();
Bruno Cardoso Lopes92e87f22008-07-23 16:01:50 +00001798
1799 // gp_rel relocation
Wesley Peckbf17cfa2010-11-23 03:31:01 +00001800 // FIXME: we should reference the constant pool using small data sections,
Chris Lattner7a2bdde2011-04-15 05:18:47 +00001801 // but the asm printer currently doesn't support this feature without
Wesley Peckbf17cfa2010-11-23 03:31:01 +00001802 // hacking it. This feature should come soon so we can uncomment the
Bruno Cardoso Lopesf33bc432008-07-28 19:26:25 +00001803 // stuff below.
Eli Friedmane2c74082009-08-03 02:22:28 +00001804 //if (IsInSmallSection(C->getType())) {
Owen Anderson825b72b2009-08-11 20:47:22 +00001805 // SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, MVT::i32, CP);
1806 // SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(MVT::i32);
Wesley Peckbf17cfa2010-11-23 03:31:01 +00001807 // ResNode = DAG.getNode(ISD::ADD, MVT::i32, GOT, GPRelNode);
Bruno Cardoso Lopesd71cebf2009-11-25 12:17:58 +00001808
Akira Hatanaka13daee32012-03-27 02:55:31 +00001809 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !IsN64) {
Akira Hatanakae2e436a2011-04-01 21:41:06 +00001810 SDValue CPHi = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment(),
Akira Hatanaka4552c9a2011-04-15 21:51:11 +00001811 N->getOffset(), MipsII::MO_ABS_HI);
Akira Hatanakae2e436a2011-04-01 21:41:06 +00001812 SDValue CPLo = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment(),
Akira Hatanaka4552c9a2011-04-15 21:51:11 +00001813 N->getOffset(), MipsII::MO_ABS_LO);
Akira Hatanakae2e436a2011-04-01 21:41:06 +00001814 SDValue HiPart = DAG.getNode(MipsISD::Hi, dl, MVT::i32, CPHi);
1815 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, CPLo);
Owen Anderson825b72b2009-08-11 20:47:22 +00001816 ResNode = DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo);
Bruno Cardoso Lopesd71cebf2009-11-25 12:17:58 +00001817 } else {
Akira Hatanaka620db892011-11-16 22:44:38 +00001818 EVT ValTy = Op.getValueType();
Akira Hatanaka86a27332012-04-04 18:26:12 +00001819 unsigned GOTFlag = HasMips64 ? MipsII::MO_GOT_PAGE : MipsII::MO_GOT;
1820 unsigned OFSTFlag = HasMips64 ? MipsII::MO_GOT_OFST : MipsII::MO_ABS_LO;
Akira Hatanaka620db892011-11-16 22:44:38 +00001821 SDValue CP = DAG.getTargetConstantPool(C, ValTy, N->getAlignment(),
1822 N->getOffset(), GOTFlag);
Akira Hatanaka648f00c2012-02-24 22:34:47 +00001823 CP = DAG.getNode(MipsISD::Wrapper, dl, ValTy, GetGlobalReg(DAG, ValTy), CP);
Akira Hatanaka82099682011-12-19 19:52:25 +00001824 SDValue Load = DAG.getLoad(ValTy, dl, DAG.getEntryNode(), CP,
1825 MachinePointerInfo::getConstantPool(), false,
1826 false, false, 0);
Akira Hatanaka620db892011-11-16 22:44:38 +00001827 SDValue CPLo = DAG.getTargetConstantPool(C, ValTy, N->getAlignment(),
1828 N->getOffset(), OFSTFlag);
1829 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, ValTy, CPLo);
1830 ResNode = DAG.getNode(ISD::ADD, dl, ValTy, Load, Lo);
Bruno Cardoso Lopesd71cebf2009-11-25 12:17:58 +00001831 }
Bruno Cardoso Lopes92e87f22008-07-23 16:01:50 +00001832
1833 return ResNode;
Bruno Cardoso Lopes97c25372008-07-09 04:15:08 +00001834}
1835
Dan Gohmand858e902010-04-17 15:26:15 +00001836SDValue MipsTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
Dan Gohman1e93df62010-04-17 14:41:14 +00001837 MachineFunction &MF = DAG.getMachineFunction();
1838 MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>();
1839
Bruno Cardoso Lopes6059b852010-02-06 21:00:02 +00001840 DebugLoc dl = Op.getDebugLoc();
Dan Gohman1e93df62010-04-17 14:41:14 +00001841 SDValue FI = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
1842 getPointerTy());
Bruno Cardoso Lopes6059b852010-02-06 21:00:02 +00001843
1844 // vastart just stores the address of the VarArgsFrameIndex slot into the
1845 // memory location argument.
1846 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
Chris Lattner8026a9d2010-09-21 17:50:43 +00001847 return DAG.getStore(Op.getOperand(0), dl, FI, Op.getOperand(1),
Akira Hatanaka82099682011-12-19 19:52:25 +00001848 MachinePointerInfo(SV), false, false, 0);
Bruno Cardoso Lopes6059b852010-02-06 21:00:02 +00001849}
Jia Liubb481f82012-02-28 07:46:26 +00001850
Akira Hatanaka056c51e2012-04-11 22:13:04 +00001851static SDValue LowerFCOPYSIGN32(SDValue Op, SelectionDAG &DAG, bool HasR2) {
1852 EVT TyX = Op.getOperand(0).getValueType();
1853 EVT TyY = Op.getOperand(1).getValueType();
1854 SDValue Const1 = DAG.getConstant(1, MVT::i32);
1855 SDValue Const31 = DAG.getConstant(31, MVT::i32);
1856 DebugLoc DL = Op.getDebugLoc();
1857 SDValue Res;
1858
1859 // If operand is of type f64, extract the upper 32-bit. Otherwise, bitcast it
1860 // to i32.
1861 SDValue X = (TyX == MVT::f32) ?
1862 DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(0)) :
1863 DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(0),
1864 Const1);
1865 SDValue Y = (TyY == MVT::f32) ?
1866 DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(1)) :
1867 DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(1),
1868 Const1);
1869
1870 if (HasR2) {
1871 // ext E, Y, 31, 1 ; extract bit31 of Y
1872 // ins X, E, 31, 1 ; insert extracted bit at bit31 of X
1873 SDValue E = DAG.getNode(MipsISD::Ext, DL, MVT::i32, Y, Const31, Const1);
1874 Res = DAG.getNode(MipsISD::Ins, DL, MVT::i32, E, Const31, Const1, X);
1875 } else {
1876 // sll SllX, X, 1
1877 // srl SrlX, SllX, 1
1878 // srl SrlY, Y, 31
1879 // sll SllY, SrlX, 31
1880 // or Or, SrlX, SllY
1881 SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i32, X, Const1);
1882 SDValue SrlX = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1);
1883 SDValue SrlY = DAG.getNode(ISD::SRL, DL, MVT::i32, Y, Const31);
1884 SDValue SllY = DAG.getNode(ISD::SHL, DL, MVT::i32, SrlY, Const31);
1885 Res = DAG.getNode(ISD::OR, DL, MVT::i32, SrlX, SllY);
1886 }
1887
1888 if (TyX == MVT::f32)
1889 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Res);
1890
1891 SDValue LowX = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
1892 Op.getOperand(0), DAG.getConstant(0, MVT::i32));
1893 return DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, LowX, Res);
Akira Hatanaka9c3d57c2011-05-25 19:32:07 +00001894}
1895
Akira Hatanaka056c51e2012-04-11 22:13:04 +00001896static SDValue LowerFCOPYSIGN64(SDValue Op, SelectionDAG &DAG, bool HasR2) {
1897 unsigned WidthX = Op.getOperand(0).getValueSizeInBits();
1898 unsigned WidthY = Op.getOperand(1).getValueSizeInBits();
1899 EVT TyX = MVT::getIntegerVT(WidthX), TyY = MVT::getIntegerVT(WidthY);
1900 SDValue Const1 = DAG.getConstant(1, MVT::i32);
1901 DebugLoc DL = Op.getDebugLoc();
Eric Christopher471e4222011-06-08 23:55:35 +00001902
Akira Hatanaka056c51e2012-04-11 22:13:04 +00001903 // Bitcast to integer nodes.
1904 SDValue X = DAG.getNode(ISD::BITCAST, DL, TyX, Op.getOperand(0));
1905 SDValue Y = DAG.getNode(ISD::BITCAST, DL, TyY, Op.getOperand(1));
Akira Hatanaka9c3d57c2011-05-25 19:32:07 +00001906
Akira Hatanaka056c51e2012-04-11 22:13:04 +00001907 if (HasR2) {
1908 // ext E, Y, width(Y) - 1, 1 ; extract bit width(Y)-1 of Y
1909 // ins X, E, width(X) - 1, 1 ; insert extracted bit at bit width(X)-1 of X
1910 SDValue E = DAG.getNode(MipsISD::Ext, DL, TyY, Y,
1911 DAG.getConstant(WidthY - 1, MVT::i32), Const1);
Akira Hatanaka9c3d57c2011-05-25 19:32:07 +00001912
Akira Hatanaka056c51e2012-04-11 22:13:04 +00001913 if (WidthX > WidthY)
1914 E = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, E);
1915 else if (WidthY > WidthX)
1916 E = DAG.getNode(ISD::TRUNCATE, DL, TyX, E);
Akira Hatanaka9c3d57c2011-05-25 19:32:07 +00001917
Akira Hatanaka056c51e2012-04-11 22:13:04 +00001918 SDValue I = DAG.getNode(MipsISD::Ins, DL, TyX, E,
1919 DAG.getConstant(WidthX - 1, MVT::i32), Const1, X);
1920 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), I);
1921 }
1922
1923 // (d)sll SllX, X, 1
1924 // (d)srl SrlX, SllX, 1
1925 // (d)srl SrlY, Y, width(Y)-1
1926 // (d)sll SllY, SrlX, width(Y)-1
1927 // or Or, SrlX, SllY
1928 SDValue SllX = DAG.getNode(ISD::SHL, DL, TyX, X, Const1);
1929 SDValue SrlX = DAG.getNode(ISD::SRL, DL, TyX, SllX, Const1);
1930 SDValue SrlY = DAG.getNode(ISD::SRL, DL, TyY, Y,
1931 DAG.getConstant(WidthY - 1, MVT::i32));
1932
1933 if (WidthX > WidthY)
1934 SrlY = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, SrlY);
1935 else if (WidthY > WidthX)
1936 SrlY = DAG.getNode(ISD::TRUNCATE, DL, TyX, SrlY);
1937
1938 SDValue SllY = DAG.getNode(ISD::SHL, DL, TyX, SrlY,
1939 DAG.getConstant(WidthX - 1, MVT::i32));
1940 SDValue Or = DAG.getNode(ISD::OR, DL, TyX, SrlX, SllY);
1941 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Or);
Akira Hatanaka9c3d57c2011-05-25 19:32:07 +00001942}
1943
Akira Hatanaka82099682011-12-19 19:52:25 +00001944SDValue
1945MipsTargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
Akira Hatanaka056c51e2012-04-11 22:13:04 +00001946 if (Subtarget->hasMips64())
1947 return LowerFCOPYSIGN64(Op, DAG, Subtarget->hasMips32r2());
Akira Hatanaka9c3d57c2011-05-25 19:32:07 +00001948
Akira Hatanaka056c51e2012-04-11 22:13:04 +00001949 return LowerFCOPYSIGN32(Op, DAG, Subtarget->hasMips32r2());
Akira Hatanaka9c3d57c2011-05-25 19:32:07 +00001950}
1951
Akira Hatanakac12a6e62012-04-11 22:49:04 +00001952static SDValue LowerFABS32(SDValue Op, SelectionDAG &DAG, bool HasR2) {
1953 SDValue Res, Const1 = DAG.getConstant(1, MVT::i32);
1954 DebugLoc DL = Op.getDebugLoc();
1955
1956 // If operand is of type f64, extract the upper 32-bit. Otherwise, bitcast it
1957 // to i32.
1958 SDValue X = (Op.getValueType() == MVT::f32) ?
1959 DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(0)) :
1960 DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(0),
1961 Const1);
1962
1963 // Clear MSB.
1964 if (HasR2)
1965 Res = DAG.getNode(MipsISD::Ins, DL, MVT::i32,
1966 DAG.getRegister(Mips::ZERO, MVT::i32),
1967 DAG.getConstant(31, MVT::i32), Const1, X);
1968 else {
1969 SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i32, X, Const1);
1970 Res = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1);
1971 }
1972
1973 if (Op.getValueType() == MVT::f32)
1974 return DAG.getNode(ISD::BITCAST, DL, MVT::f32, Res);
1975
1976 SDValue LowX = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
1977 Op.getOperand(0), DAG.getConstant(0, MVT::i32));
1978 return DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, LowX, Res);
1979}
1980
1981static SDValue LowerFABS64(SDValue Op, SelectionDAG &DAG, bool HasR2) {
1982 SDValue Res, Const1 = DAG.getConstant(1, MVT::i32);
1983 DebugLoc DL = Op.getDebugLoc();
1984
1985 // Bitcast to integer node.
1986 SDValue X = DAG.getNode(ISD::BITCAST, DL, MVT::i64, Op.getOperand(0));
1987
1988 // Clear MSB.
1989 if (HasR2)
1990 Res = DAG.getNode(MipsISD::Ins, DL, MVT::i64,
1991 DAG.getRegister(Mips::ZERO_64, MVT::i64),
1992 DAG.getConstant(63, MVT::i32), Const1, X);
1993 else {
1994 SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i64, X, Const1);
1995 Res = DAG.getNode(ISD::SRL, DL, MVT::i64, SllX, Const1);
1996 }
1997
1998 return DAG.getNode(ISD::BITCAST, DL, MVT::f64, Res);
1999}
2000
2001SDValue
2002MipsTargetLowering::LowerFABS(SDValue Op, SelectionDAG &DAG) const {
2003 if (Subtarget->hasMips64() && (Op.getValueType() == MVT::f64))
2004 return LowerFABS64(Op, DAG, Subtarget->hasMips32r2());
2005
2006 return LowerFABS32(Op, DAG, Subtarget->hasMips32r2());
2007}
2008
Akira Hatanaka2e591472011-06-02 00:24:44 +00002009SDValue MipsTargetLowering::
2010LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
Bruno Cardoso Lopese0b5cfc2011-06-16 00:40:02 +00002011 // check the depth
2012 assert((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) &&
Akira Hatanaka0f843822011-06-07 18:58:42 +00002013 "Frame address can only be determined for current frame.");
Akira Hatanaka2e591472011-06-02 00:24:44 +00002014
2015 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
2016 MFI->setFrameAddressIsTaken(true);
2017 EVT VT = Op.getValueType();
2018 DebugLoc dl = Op.getDebugLoc();
Akira Hatanaka46ac4392011-11-11 04:11:56 +00002019 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl,
2020 IsN64 ? Mips::FP_64 : Mips::FP, VT);
Akira Hatanaka2e591472011-06-02 00:24:44 +00002021 return FrameAddr;
2022}
2023
Akira Hatanakaba584fe2012-07-11 00:53:32 +00002024SDValue MipsTargetLowering::LowerRETURNADDR(SDValue Op,
2025 SelectionDAG &DAG) const {
2026 // check the depth
2027 assert((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) &&
2028 "Return address can be determined only for current frame.");
2029
2030 MachineFunction &MF = DAG.getMachineFunction();
2031 MachineFrameInfo *MFI = MF.getFrameInfo();
2032 EVT VT = Op.getValueType();
2033 unsigned RA = IsN64 ? Mips::RA_64 : Mips::RA;
2034 MFI->setReturnAddressIsTaken(true);
2035
2036 // Return RA, which contains the return address. Mark it an implicit live-in.
2037 unsigned Reg = MF.addLiveIn(RA, getRegClassFor(VT));
2038 return DAG.getCopyFromReg(DAG.getEntryNode(), Op.getDebugLoc(), Reg, VT);
2039}
2040
Akira Hatanakadb548262011-07-19 23:30:50 +00002041// TODO: set SType according to the desired memory barrier behavior.
Akira Hatanaka82099682011-12-19 19:52:25 +00002042SDValue
Akira Hatanaka864f6602012-06-14 21:10:56 +00002043MipsTargetLowering::LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG) const {
Akira Hatanakadb548262011-07-19 23:30:50 +00002044 unsigned SType = 0;
2045 DebugLoc dl = Op.getDebugLoc();
2046 return DAG.getNode(MipsISD::Sync, dl, MVT::Other, Op.getOperand(0),
2047 DAG.getConstant(SType, MVT::i32));
2048}
2049
Eli Friedman14648462011-07-27 22:21:52 +00002050SDValue MipsTargetLowering::LowerATOMIC_FENCE(SDValue Op,
Akira Hatanaka864f6602012-06-14 21:10:56 +00002051 SelectionDAG &DAG) const {
Eli Friedman14648462011-07-27 22:21:52 +00002052 // FIXME: Need pseudo-fence for 'singlethread' fences
2053 // FIXME: Set SType for weaker fences where supported/appropriate.
2054 unsigned SType = 0;
2055 DebugLoc dl = Op.getDebugLoc();
2056 return DAG.getNode(MipsISD::Sync, dl, MVT::Other, Op.getOperand(0),
2057 DAG.getConstant(SType, MVT::i32));
2058}
2059
Akira Hatanakaa284acb2012-05-09 00:55:21 +00002060SDValue MipsTargetLowering::LowerShiftLeftParts(SDValue Op,
Akira Hatanaka864f6602012-06-14 21:10:56 +00002061 SelectionDAG &DAG) const {
Akira Hatanakaa284acb2012-05-09 00:55:21 +00002062 DebugLoc DL = Op.getDebugLoc();
2063 SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1);
2064 SDValue Shamt = Op.getOperand(2);
2065
2066 // if shamt < 32:
2067 // lo = (shl lo, shamt)
2068 // hi = (or (shl hi, shamt) (srl (srl lo, 1), ~shamt))
2069 // else:
2070 // lo = 0
2071 // hi = (shl lo, shamt[4:0])
2072 SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt,
2073 DAG.getConstant(-1, MVT::i32));
2074 SDValue ShiftRight1Lo = DAG.getNode(ISD::SRL, DL, MVT::i32, Lo,
2075 DAG.getConstant(1, MVT::i32));
2076 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, MVT::i32, ShiftRight1Lo,
2077 Not);
2078 SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, MVT::i32, Hi, Shamt);
2079 SDValue Or = DAG.getNode(ISD::OR, DL, MVT::i32, ShiftLeftHi, ShiftRightLo);
2080 SDValue ShiftLeftLo = DAG.getNode(ISD::SHL, DL, MVT::i32, Lo, Shamt);
2081 SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt,
2082 DAG.getConstant(0x20, MVT::i32));
Akira Hatanaka864f6602012-06-14 21:10:56 +00002083 Lo = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond,
2084 DAG.getConstant(0, MVT::i32), ShiftLeftLo);
Akira Hatanakaa284acb2012-05-09 00:55:21 +00002085 Hi = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond, ShiftLeftLo, Or);
2086
2087 SDValue Ops[2] = {Lo, Hi};
2088 return DAG.getMergeValues(Ops, 2, DL);
2089}
2090
Akira Hatanaka864f6602012-06-14 21:10:56 +00002091SDValue MipsTargetLowering::LowerShiftRightParts(SDValue Op, SelectionDAG &DAG,
Akira Hatanakaa284acb2012-05-09 00:55:21 +00002092 bool IsSRA) const {
2093 DebugLoc DL = Op.getDebugLoc();
2094 SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1);
2095 SDValue Shamt = Op.getOperand(2);
2096
2097 // if shamt < 32:
2098 // lo = (or (shl (shl hi, 1), ~shamt) (srl lo, shamt))
2099 // if isSRA:
2100 // hi = (sra hi, shamt)
2101 // else:
2102 // hi = (srl hi, shamt)
2103 // else:
2104 // if isSRA:
2105 // lo = (sra hi, shamt[4:0])
2106 // hi = (sra hi, 31)
2107 // else:
2108 // lo = (srl hi, shamt[4:0])
2109 // hi = 0
2110 SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt,
2111 DAG.getConstant(-1, MVT::i32));
2112 SDValue ShiftLeft1Hi = DAG.getNode(ISD::SHL, DL, MVT::i32, Hi,
2113 DAG.getConstant(1, MVT::i32));
2114 SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, MVT::i32, ShiftLeft1Hi, Not);
2115 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, MVT::i32, Lo, Shamt);
2116 SDValue Or = DAG.getNode(ISD::OR, DL, MVT::i32, ShiftLeftHi, ShiftRightLo);
2117 SDValue ShiftRightHi = DAG.getNode(IsSRA ? ISD::SRA : ISD::SRL, DL, MVT::i32,
2118 Hi, Shamt);
2119 SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt,
2120 DAG.getConstant(0x20, MVT::i32));
2121 SDValue Shift31 = DAG.getNode(ISD::SRA, DL, MVT::i32, Hi,
2122 DAG.getConstant(31, MVT::i32));
2123 Lo = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond, ShiftRightHi, Or);
2124 Hi = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond,
2125 IsSRA ? Shift31 : DAG.getConstant(0, MVT::i32),
2126 ShiftRightHi);
2127
2128 SDValue Ops[2] = {Lo, Hi};
2129 return DAG.getMergeValues(Ops, 2, DL);
2130}
2131
Akira Hatanaka1cd0ec02012-06-02 00:03:49 +00002132static SDValue CreateLoadLR(unsigned Opc, SelectionDAG &DAG, LoadSDNode *LD,
2133 SDValue Chain, SDValue Src, unsigned Offset) {
Akira Hatanaka2bd7e532012-06-13 19:06:08 +00002134 SDValue Ptr = LD->getBasePtr();
Akira Hatanaka1cd0ec02012-06-02 00:03:49 +00002135 EVT VT = LD->getValueType(0), MemVT = LD->getMemoryVT();
Akira Hatanaka2bd7e532012-06-13 19:06:08 +00002136 EVT BasePtrVT = Ptr.getValueType();
Akira Hatanaka1cd0ec02012-06-02 00:03:49 +00002137 DebugLoc DL = LD->getDebugLoc();
2138 SDVTList VTList = DAG.getVTList(VT, MVT::Other);
2139
2140 if (Offset)
Akira Hatanaka2bd7e532012-06-13 19:06:08 +00002141 Ptr = DAG.getNode(ISD::ADD, DL, BasePtrVT, Ptr,
Akira Hatanaka1cd0ec02012-06-02 00:03:49 +00002142 DAG.getConstant(Offset, BasePtrVT));
Akira Hatanaka1cd0ec02012-06-02 00:03:49 +00002143
2144 SDValue Ops[] = { Chain, Ptr, Src };
2145 return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, 3, MemVT,
2146 LD->getMemOperand());
2147}
2148
2149// Expand an unaligned 32 or 64-bit integer load node.
2150SDValue MipsTargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
2151 LoadSDNode *LD = cast<LoadSDNode>(Op);
2152 EVT MemVT = LD->getMemoryVT();
2153
2154 // Return if load is aligned or if MemVT is neither i32 nor i64.
2155 if ((LD->getAlignment() >= MemVT.getSizeInBits() / 8) ||
2156 ((MemVT != MVT::i32) && (MemVT != MVT::i64)))
2157 return SDValue();
2158
2159 bool IsLittle = Subtarget->isLittle();
2160 EVT VT = Op.getValueType();
2161 ISD::LoadExtType ExtType = LD->getExtensionType();
2162 SDValue Chain = LD->getChain(), Undef = DAG.getUNDEF(VT);
2163
2164 assert((VT == MVT::i32) || (VT == MVT::i64));
2165
2166 // Expand
2167 // (set dst, (i64 (load baseptr)))
2168 // to
2169 // (set tmp, (ldl (add baseptr, 7), undef))
2170 // (set dst, (ldr baseptr, tmp))
2171 if ((VT == MVT::i64) && (ExtType == ISD::NON_EXTLOAD)) {
2172 SDValue LDL = CreateLoadLR(MipsISD::LDL, DAG, LD, Chain, Undef,
2173 IsLittle ? 7 : 0);
2174 return CreateLoadLR(MipsISD::LDR, DAG, LD, LDL.getValue(1), LDL,
2175 IsLittle ? 0 : 7);
2176 }
2177
2178 SDValue LWL = CreateLoadLR(MipsISD::LWL, DAG, LD, Chain, Undef,
2179 IsLittle ? 3 : 0);
2180 SDValue LWR = CreateLoadLR(MipsISD::LWR, DAG, LD, LWL.getValue(1), LWL,
2181 IsLittle ? 0 : 3);
2182
2183 // Expand
2184 // (set dst, (i32 (load baseptr))) or
2185 // (set dst, (i64 (sextload baseptr))) or
2186 // (set dst, (i64 (extload baseptr)))
2187 // to
2188 // (set tmp, (lwl (add baseptr, 3), undef))
2189 // (set dst, (lwr baseptr, tmp))
2190 if ((VT == MVT::i32) || (ExtType == ISD::SEXTLOAD) ||
2191 (ExtType == ISD::EXTLOAD))
2192 return LWR;
2193
2194 assert((VT == MVT::i64) && (ExtType == ISD::ZEXTLOAD));
2195
2196 // Expand
2197 // (set dst, (i64 (zextload baseptr)))
2198 // to
2199 // (set tmp0, (lwl (add baseptr, 3), undef))
2200 // (set tmp1, (lwr baseptr, tmp0))
2201 // (set tmp2, (shl tmp1, 32))
2202 // (set dst, (srl tmp2, 32))
2203 DebugLoc DL = LD->getDebugLoc();
2204 SDValue Const32 = DAG.getConstant(32, MVT::i32);
2205 SDValue SLL = DAG.getNode(ISD::SHL, DL, MVT::i64, LWR, Const32);
Akira Hatanaka94ccee22012-06-04 17:46:29 +00002206 SDValue SRL = DAG.getNode(ISD::SRL, DL, MVT::i64, SLL, Const32);
2207 SDValue Ops[] = { SRL, LWR.getValue(1) };
Akira Hatanaka1cd0ec02012-06-02 00:03:49 +00002208 return DAG.getMergeValues(Ops, 2, DL);
2209}
2210
2211static SDValue CreateStoreLR(unsigned Opc, SelectionDAG &DAG, StoreSDNode *SD,
2212 SDValue Chain, unsigned Offset) {
Akira Hatanaka2bd7e532012-06-13 19:06:08 +00002213 SDValue Ptr = SD->getBasePtr(), Value = SD->getValue();
2214 EVT MemVT = SD->getMemoryVT(), BasePtrVT = Ptr.getValueType();
Akira Hatanaka1cd0ec02012-06-02 00:03:49 +00002215 DebugLoc DL = SD->getDebugLoc();
2216 SDVTList VTList = DAG.getVTList(MVT::Other);
2217
2218 if (Offset)
Akira Hatanaka2bd7e532012-06-13 19:06:08 +00002219 Ptr = DAG.getNode(ISD::ADD, DL, BasePtrVT, Ptr,
Akira Hatanaka1cd0ec02012-06-02 00:03:49 +00002220 DAG.getConstant(Offset, BasePtrVT));
Akira Hatanaka1cd0ec02012-06-02 00:03:49 +00002221
2222 SDValue Ops[] = { Chain, Value, Ptr };
2223 return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, 3, MemVT,
2224 SD->getMemOperand());
2225}
2226
2227// Expand an unaligned 32 or 64-bit integer store node.
2228SDValue MipsTargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
2229 StoreSDNode *SD = cast<StoreSDNode>(Op);
2230 EVT MemVT = SD->getMemoryVT();
2231
2232 // Return if store is aligned or if MemVT is neither i32 nor i64.
2233 if ((SD->getAlignment() >= MemVT.getSizeInBits() / 8) ||
2234 ((MemVT != MVT::i32) && (MemVT != MVT::i64)))
2235 return SDValue();
2236
2237 bool IsLittle = Subtarget->isLittle();
2238 SDValue Value = SD->getValue(), Chain = SD->getChain();
2239 EVT VT = Value.getValueType();
2240
2241 // Expand
2242 // (store val, baseptr) or
2243 // (truncstore val, baseptr)
2244 // to
2245 // (swl val, (add baseptr, 3))
2246 // (swr val, baseptr)
2247 if ((VT == MVT::i32) || SD->isTruncatingStore()) {
2248 SDValue SWL = CreateStoreLR(MipsISD::SWL, DAG, SD, Chain,
2249 IsLittle ? 3 : 0);
2250 return CreateStoreLR(MipsISD::SWR, DAG, SD, SWL, IsLittle ? 0 : 3);
2251 }
2252
2253 assert(VT == MVT::i64);
2254
2255 // Expand
2256 // (store val, baseptr)
2257 // to
2258 // (sdl val, (add baseptr, 7))
2259 // (sdr val, baseptr)
2260 SDValue SDL = CreateStoreLR(MipsISD::SDL, DAG, SD, Chain, IsLittle ? 7 : 0);
2261 return CreateStoreLR(MipsISD::SDR, DAG, SD, SDL, IsLittle ? 0 : 7);
2262}
2263
Akira Hatanaka4552c9a2011-04-15 21:51:11 +00002264//===----------------------------------------------------------------------===//
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002265// Calling Convention Implementation
Akira Hatanaka4552c9a2011-04-15 21:51:11 +00002266//===----------------------------------------------------------------------===//
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002267
Akira Hatanaka4552c9a2011-04-15 21:51:11 +00002268//===----------------------------------------------------------------------===//
Wesley Peckbf17cfa2010-11-23 03:31:01 +00002269// TODO: Implement a generic logic using tblgen that can support this.
Bruno Cardoso Lopesb53db4f2009-03-19 02:12:28 +00002270// Mips O32 ABI rules:
2271// ---
2272// i32 - Passed in A0, A1, A2, A3 and stack
Wesley Peckbf17cfa2010-11-23 03:31:01 +00002273// f32 - Only passed in f32 registers if no int reg has been used yet to hold
Bruno Cardoso Lopesb53db4f2009-03-19 02:12:28 +00002274// an argument. Otherwise, passed in A1, A2, A3 and stack.
Wesley Peckbf17cfa2010-11-23 03:31:01 +00002275// f64 - Only passed in two aliased f32 registers if no int reg has been used
2276// yet to hold an argument. Otherwise, use A2, A3 and stack. If A1 is
Bruno Cardoso Lopesb53db4f2009-03-19 02:12:28 +00002277// not used, it must be shadowed. If only A3 is avaiable, shadow it and
2278// go to stack.
Akira Hatanaka95b8ae12011-05-19 18:06:05 +00002279//
2280// For vararg functions, all arguments are passed in A0, A1, A2, A3 and stack.
Akira Hatanaka4552c9a2011-04-15 21:51:11 +00002281//===----------------------------------------------------------------------===//
Bruno Cardoso Lopesb53db4f2009-03-19 02:12:28 +00002282
Duncan Sands1e96bab2010-11-04 10:49:57 +00002283static bool CC_MipsO32(unsigned ValNo, MVT ValVT,
Duncan Sands1440e8b2010-11-03 11:35:31 +00002284 MVT LocVT, CCValAssign::LocInfo LocInfo,
Bruno Cardoso Lopesb53db4f2009-03-19 02:12:28 +00002285 ISD::ArgFlagsTy ArgFlags, CCState &State) {
2286
Wesley Peckbf17cfa2010-11-23 03:31:01 +00002287 static const unsigned IntRegsSize=4, FloatRegsSize=2;
Bruno Cardoso Lopesb53db4f2009-03-19 02:12:28 +00002288
Craig Topperc5eaae42012-03-11 07:57:25 +00002289 static const uint16_t IntRegs[] = {
Bruno Cardoso Lopesb53db4f2009-03-19 02:12:28 +00002290 Mips::A0, Mips::A1, Mips::A2, Mips::A3
2291 };
Craig Topperc5eaae42012-03-11 07:57:25 +00002292 static const uint16_t F32Regs[] = {
Bruno Cardoso Lopesb53db4f2009-03-19 02:12:28 +00002293 Mips::F12, Mips::F14
2294 };
Craig Topperc5eaae42012-03-11 07:57:25 +00002295 static const uint16_t F64Regs[] = {
Bruno Cardoso Lopesb53db4f2009-03-19 02:12:28 +00002296 Mips::D6, Mips::D7
2297 };
2298
Akira Hatanaka4231c7e2011-05-24 19:18:33 +00002299 // ByVal Args
2300 if (ArgFlags.isByVal()) {
2301 State.HandleByVal(ValNo, ValVT, LocVT, LocInfo,
2302 1 /*MinSize*/, 4 /*MinAlign*/, ArgFlags);
2303 unsigned NextReg = (State.getNextStackOffset() + 3) / 4;
2304 for (unsigned r = State.getFirstUnallocated(IntRegs, IntRegsSize);
2305 r < std::min(IntRegsSize, NextReg); ++r)
2306 State.AllocateReg(IntRegs[r]);
2307 return false;
2308 }
2309
Bruno Cardoso Lopesb37a7422010-02-06 19:20:49 +00002310 // Promote i8 and i16
2311 if (LocVT == MVT::i8 || LocVT == MVT::i16) {
2312 LocVT = MVT::i32;
2313 if (ArgFlags.isSExt())
2314 LocInfo = CCValAssign::SExt;
2315 else if (ArgFlags.isZExt())
2316 LocInfo = CCValAssign::ZExt;
2317 else
2318 LocInfo = CCValAssign::AExt;
2319 }
2320
Bruno Cardoso Lopesc42fb5f2011-03-04 20:27:44 +00002321 unsigned Reg;
2322
Akira Hatanaka95b8ae12011-05-19 18:06:05 +00002323 // f32 and f64 are allocated in A0, A1, A2, A3 when either of the following
2324 // is true: function is vararg, argument is 3rd or higher, there is previous
2325 // argument which is not f32 or f64.
2326 bool AllocateFloatsInIntReg = State.isVarArg() || ValNo > 1
2327 || State.getFirstUnallocated(F32Regs, FloatRegsSize) != ValNo;
Akira Hatanakaa1a7ba82011-05-19 20:29:48 +00002328 unsigned OrigAlign = ArgFlags.getOrigAlign();
2329 bool isI64 = (ValVT == MVT::i32 && OrigAlign == 8);
Akira Hatanaka95b8ae12011-05-19 18:06:05 +00002330
2331 if (ValVT == MVT::i32 || (ValVT == MVT::f32 && AllocateFloatsInIntReg)) {
Bruno Cardoso Lopesc42fb5f2011-03-04 20:27:44 +00002332 Reg = State.AllocateReg(IntRegs, IntRegsSize);
Akira Hatanakaa1a7ba82011-05-19 20:29:48 +00002333 // If this is the first part of an i64 arg,
2334 // the allocated register must be either A0 or A2.
2335 if (isI64 && (Reg == Mips::A1 || Reg == Mips::A3))
2336 Reg = State.AllocateReg(IntRegs, IntRegsSize);
Bruno Cardoso Lopesc42fb5f2011-03-04 20:27:44 +00002337 LocVT = MVT::i32;
Akira Hatanaka95b8ae12011-05-19 18:06:05 +00002338 } else if (ValVT == MVT::f64 && AllocateFloatsInIntReg) {
2339 // Allocate int register and shadow next int register. If first
2340 // available register is Mips::A1 or Mips::A3, shadow it too.
Bruno Cardoso Lopesc42fb5f2011-03-04 20:27:44 +00002341 Reg = State.AllocateReg(IntRegs, IntRegsSize);
2342 if (Reg == Mips::A1 || Reg == Mips::A3)
2343 Reg = State.AllocateReg(IntRegs, IntRegsSize);
2344 State.AllocateReg(IntRegs, IntRegsSize);
2345 LocVT = MVT::i32;
Akira Hatanaka95b8ae12011-05-19 18:06:05 +00002346 } else if (ValVT.isFloatingPoint() && !AllocateFloatsInIntReg) {
2347 // we are guaranteed to find an available float register
2348 if (ValVT == MVT::f32) {
2349 Reg = State.AllocateReg(F32Regs, FloatRegsSize);
2350 // Shadow int register
2351 State.AllocateReg(IntRegs, IntRegsSize);
2352 } else {
2353 Reg = State.AllocateReg(F64Regs, FloatRegsSize);
2354 // Shadow int registers
2355 unsigned Reg2 = State.AllocateReg(IntRegs, IntRegsSize);
2356 if (Reg2 == Mips::A1 || Reg2 == Mips::A3)
2357 State.AllocateReg(IntRegs, IntRegsSize);
2358 State.AllocateReg(IntRegs, IntRegsSize);
2359 }
Bruno Cardoso Lopesc42fb5f2011-03-04 20:27:44 +00002360 } else
2361 llvm_unreachable("Cannot handle this ValVT.");
Bruno Cardoso Lopesb37a7422010-02-06 19:20:49 +00002362
Akira Hatanakad37776d2011-05-20 21:39:54 +00002363 unsigned SizeInBytes = ValVT.getSizeInBits() >> 3;
2364 unsigned Offset = State.AllocateStack(SizeInBytes, OrigAlign);
2365
2366 if (!Reg)
Bruno Cardoso Lopesc42fb5f2011-03-04 20:27:44 +00002367 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
Akira Hatanakad37776d2011-05-20 21:39:54 +00002368 else
Bruno Cardoso Lopesc42fb5f2011-03-04 20:27:44 +00002369 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
Bruno Cardoso Lopesb37a7422010-02-06 19:20:49 +00002370
Bruno Cardoso Lopesc42fb5f2011-03-04 20:27:44 +00002371 return false; // CC must always match
Bruno Cardoso Lopesb37a7422010-02-06 19:20:49 +00002372}
2373
Craig Topperc5eaae42012-03-11 07:57:25 +00002374static const uint16_t Mips64IntRegs[8] =
Akira Hatanaka2c5d6522011-11-12 02:20:46 +00002375 {Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64,
2376 Mips::T0_64, Mips::T1_64, Mips::T2_64, Mips::T3_64};
Craig Topperc5eaae42012-03-11 07:57:25 +00002377static const uint16_t Mips64DPRegs[8] =
Akira Hatanaka2c5d6522011-11-12 02:20:46 +00002378 {Mips::D12_64, Mips::D13_64, Mips::D14_64, Mips::D15_64,
2379 Mips::D16_64, Mips::D17_64, Mips::D18_64, Mips::D19_64};
2380
2381static bool CC_Mips64Byval(unsigned ValNo, MVT ValVT, MVT LocVT,
2382 CCValAssign::LocInfo LocInfo,
2383 ISD::ArgFlagsTy ArgFlags, CCState &State) {
2384 unsigned Align = std::max(ArgFlags.getByValAlign(), (unsigned)8);
2385 unsigned Size = (ArgFlags.getByValSize() + 7) / 8 * 8;
2386 unsigned FirstIdx = State.getFirstUnallocated(Mips64IntRegs, 8);
2387
2388 assert(Align <= 16 && "Cannot handle alignments larger than 16.");
2389
Jia Liubb481f82012-02-28 07:46:26 +00002390 // If byval is 16-byte aligned, the first arg register must be even.
Akira Hatanaka2c5d6522011-11-12 02:20:46 +00002391 if ((Align == 16) && (FirstIdx % 2)) {
2392 State.AllocateReg(Mips64IntRegs[FirstIdx], Mips64DPRegs[FirstIdx]);
2393 ++FirstIdx;
2394 }
2395
2396 // Mark the registers allocated.
2397 for (unsigned I = FirstIdx; Size && (I < 8); Size -= 8, ++I)
2398 State.AllocateReg(Mips64IntRegs[I], Mips64DPRegs[I]);
2399
2400 // Allocate space on caller's stack.
2401 unsigned Offset = State.AllocateStack(Size, Align);
Jia Liubb481f82012-02-28 07:46:26 +00002402
Akira Hatanaka2c5d6522011-11-12 02:20:46 +00002403 if (FirstIdx < 8)
2404 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Mips64IntRegs[FirstIdx],
Jia Liubb481f82012-02-28 07:46:26 +00002405 LocVT, LocInfo));
Akira Hatanaka2c5d6522011-11-12 02:20:46 +00002406 else
2407 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
2408
2409 return true;
2410}
2411
2412#include "MipsGenCallingConv.inc"
2413
Akira Hatanaka49617092011-11-14 19:02:54 +00002414static void
Akira Hatanaka08067b22012-01-24 22:07:36 +00002415AnalyzeMips64CallOperands(CCState &CCInfo,
Akira Hatanaka49617092011-11-14 19:02:54 +00002416 const SmallVectorImpl<ISD::OutputArg> &Outs) {
2417 unsigned NumOps = Outs.size();
2418 for (unsigned i = 0; i != NumOps; ++i) {
2419 MVT ArgVT = Outs[i].VT;
2420 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
2421 bool R;
2422
2423 if (Outs[i].IsFixed)
2424 R = CC_MipsN(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, CCInfo);
2425 else
2426 R = CC_MipsN_VarArg(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, CCInfo);
Jia Liubb481f82012-02-28 07:46:26 +00002427
Akira Hatanaka49617092011-11-14 19:02:54 +00002428 if (R) {
Benjamin Kramer6296ee32011-11-14 19:51:48 +00002429#ifndef NDEBUG
Akira Hatanaka49617092011-11-14 19:02:54 +00002430 dbgs() << "Call operand #" << i << " has unhandled type "
2431 << EVT(ArgVT).getEVTString();
2432#endif
2433 llvm_unreachable(0);
2434 }
2435 }
2436}
2437
Akira Hatanaka4552c9a2011-04-15 21:51:11 +00002438//===----------------------------------------------------------------------===//
Dan Gohman98ca4f22009-08-05 01:29:28 +00002439// Call Calling Convention Implementation
Akira Hatanaka4552c9a2011-04-15 21:51:11 +00002440//===----------------------------------------------------------------------===//
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002441
Akira Hatanaka4231c7e2011-05-24 19:18:33 +00002442static const unsigned O32IntRegsSize = 4;
2443
Craig Topperc5eaae42012-03-11 07:57:25 +00002444static const uint16_t O32IntRegs[] = {
Akira Hatanaka4231c7e2011-05-24 19:18:33 +00002445 Mips::A0, Mips::A1, Mips::A2, Mips::A3
2446};
2447
Akira Hatanaka373e3a42011-09-23 00:58:33 +00002448// Return next O32 integer argument register.
2449static unsigned getNextIntArgReg(unsigned Reg) {
2450 assert((Reg == Mips::A0) || (Reg == Mips::A2));
2451 return (Reg == Mips::A0) ? Mips::A1 : Mips::A3;
2452}
2453
Akira Hatanaka4231c7e2011-05-24 19:18:33 +00002454// Write ByVal Arg to arg registers and stack.
2455static void
Akira Hatanakae2d529a2012-07-31 18:46:41 +00002456WriteByValArg(SDValue Chain, DebugLoc dl,
Akira Hatanaka864f6602012-06-14 21:10:56 +00002457 SmallVector<std::pair<unsigned, SDValue>, 16> &RegsToPass,
Akira Hatanakae2d529a2012-07-31 18:46:41 +00002458 SmallVector<SDValue, 8> &MemOpChains, SDValue StackPtr,
Akira Hatanaka4231c7e2011-05-24 19:18:33 +00002459 MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg,
Akira Hatanaka864f6602012-06-14 21:10:56 +00002460 const CCValAssign &VA, const ISD::ArgFlagsTy &Flags,
Akira Hatanaka5ac85472011-08-18 23:39:37 +00002461 MVT PtrType, bool isLittle) {
2462 unsigned LocMemOffset = VA.getLocMemOffset();
2463 unsigned Offset = 0;
2464 uint32_t RemainingSize = Flags.getByValSize();
Akira Hatanaka5c21c9e2011-08-12 21:30:06 +00002465 unsigned ByValAlign = Flags.getByValAlign();
Akira Hatanaka4231c7e2011-05-24 19:18:33 +00002466
Akira Hatanaka5ac85472011-08-18 23:39:37 +00002467 // Copy the first 4 words of byval arg to registers A0 - A3.
2468 // FIXME: Use a stricter alignment if it enables better optimization in passes
2469 // run later.
2470 for (; RemainingSize >= 4 && LocMemOffset < 4 * 4;
2471 Offset += 4, RemainingSize -= 4, LocMemOffset += 4) {
Akira Hatanaka4231c7e2011-05-24 19:18:33 +00002472 SDValue LoadPtr = DAG.getNode(ISD::ADD, dl, MVT::i32, Arg,
Akira Hatanaka5ac85472011-08-18 23:39:37 +00002473 DAG.getConstant(Offset, MVT::i32));
Akira Hatanaka4231c7e2011-05-24 19:18:33 +00002474 SDValue LoadVal = DAG.getLoad(MVT::i32, dl, Chain, LoadPtr,
Akira Hatanaka82099682011-12-19 19:52:25 +00002475 MachinePointerInfo(), false, false, false,
2476 std::min(ByValAlign, (unsigned )4));
Akira Hatanaka4231c7e2011-05-24 19:18:33 +00002477 MemOpChains.push_back(LoadVal.getValue(1));
Akira Hatanaka5ac85472011-08-18 23:39:37 +00002478 unsigned DstReg = O32IntRegs[LocMemOffset / 4];
Akira Hatanaka4231c7e2011-05-24 19:18:33 +00002479 RegsToPass.push_back(std::make_pair(DstReg, LoadVal));
2480 }
2481
Akira Hatanaka5ac85472011-08-18 23:39:37 +00002482 if (RemainingSize == 0)
2483 return;
2484
2485 // If there still is a register available for argument passing, write the
2486 // remaining part of the structure to it using subword loads and shifts.
2487 if (LocMemOffset < 4 * 4) {
2488 assert(RemainingSize <= 3 && RemainingSize >= 1 &&
2489 "There must be one to three bytes remaining.");
2490 unsigned LoadSize = (RemainingSize == 3 ? 2 : RemainingSize);
2491 SDValue LoadPtr = DAG.getNode(ISD::ADD, dl, MVT::i32, Arg,
2492 DAG.getConstant(Offset, MVT::i32));
2493 unsigned Alignment = std::min(ByValAlign, (unsigned )4);
2494 SDValue LoadVal = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, Chain,
2495 LoadPtr, MachinePointerInfo(),
2496 MVT::getIntegerVT(LoadSize * 8), false,
2497 false, Alignment);
2498 MemOpChains.push_back(LoadVal.getValue(1));
2499
2500 // If target is big endian, shift it to the most significant half-word or
2501 // byte.
2502 if (!isLittle)
2503 LoadVal = DAG.getNode(ISD::SHL, dl, MVT::i32, LoadVal,
2504 DAG.getConstant(32 - LoadSize * 8, MVT::i32));
2505
2506 Offset += LoadSize;
2507 RemainingSize -= LoadSize;
2508
2509 // Read second subword if necessary.
2510 if (RemainingSize != 0) {
2511 assert(RemainingSize == 1 && "There must be one byte remaining.");
Jia Liubb481f82012-02-28 07:46:26 +00002512 LoadPtr = DAG.getNode(ISD::ADD, dl, MVT::i32, Arg,
Akira Hatanaka5ac85472011-08-18 23:39:37 +00002513 DAG.getConstant(Offset, MVT::i32));
2514 unsigned Alignment = std::min(ByValAlign, (unsigned )2);
2515 SDValue Subword = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, Chain,
2516 LoadPtr, MachinePointerInfo(),
2517 MVT::i8, false, false, Alignment);
2518 MemOpChains.push_back(Subword.getValue(1));
2519 // Insert the loaded byte to LoadVal.
2520 // FIXME: Use INS if supported by target.
2521 unsigned ShiftAmt = isLittle ? 16 : 8;
2522 SDValue Shift = DAG.getNode(ISD::SHL, dl, MVT::i32, Subword,
2523 DAG.getConstant(ShiftAmt, MVT::i32));
2524 LoadVal = DAG.getNode(ISD::OR, dl, MVT::i32, LoadVal, Shift);
2525 }
2526
2527 unsigned DstReg = O32IntRegs[LocMemOffset / 4];
2528 RegsToPass.push_back(std::make_pair(DstReg, LoadVal));
2529 return;
Akira Hatanaka4231c7e2011-05-24 19:18:33 +00002530 }
Akira Hatanaka5ac85472011-08-18 23:39:37 +00002531
Akira Hatanakae2d529a2012-07-31 18:46:41 +00002532 // Copy remaining part of byval arg using memcpy.
Akira Hatanaka5ac85472011-08-18 23:39:37 +00002533 SDValue Src = DAG.getNode(ISD::ADD, dl, MVT::i32, Arg,
2534 DAG.getConstant(Offset, MVT::i32));
Akira Hatanakae2d529a2012-07-31 18:46:41 +00002535 SDValue Dst = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr,
2536 DAG.getIntPtrConstant(LocMemOffset));
2537 Chain = DAG.getMemcpy(Chain, dl, Dst, Src,
2538 DAG.getConstant(RemainingSize, MVT::i32),
2539 std::min(ByValAlign, (unsigned)4),
2540 /*isVolatile=*/false, /*AlwaysInline=*/false,
2541 MachinePointerInfo(0), MachinePointerInfo(0));
2542 MemOpChains.push_back(Chain);
Akira Hatanaka4231c7e2011-05-24 19:18:33 +00002543}
2544
Akira Hatanaka6df3e7b2011-11-12 02:34:50 +00002545// Copy Mips64 byVal arg to registers and stack.
2546void static
Akira Hatanakae2d529a2012-07-31 18:46:41 +00002547PassByValArg64(SDValue Chain, DebugLoc dl,
Akira Hatanaka864f6602012-06-14 21:10:56 +00002548 SmallVector<std::pair<unsigned, SDValue>, 16> &RegsToPass,
Akira Hatanakae2d529a2012-07-31 18:46:41 +00002549 SmallVector<SDValue, 8> &MemOpChains, SDValue StackPtr,
Akira Hatanaka6df3e7b2011-11-12 02:34:50 +00002550 MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg,
Akira Hatanaka864f6602012-06-14 21:10:56 +00002551 const CCValAssign &VA, const ISD::ArgFlagsTy &Flags,
Akira Hatanaka6df3e7b2011-11-12 02:34:50 +00002552 EVT PtrTy, bool isLittle) {
2553 unsigned ByValSize = Flags.getByValSize();
2554 unsigned Alignment = std::min(Flags.getByValAlign(), (unsigned)8);
2555 bool IsRegLoc = VA.isRegLoc();
2556 unsigned Offset = 0; // Offset in # of bytes from the beginning of struct.
2557 unsigned LocMemOffset = 0;
Akira Hatanaka16040852011-11-15 18:42:25 +00002558 unsigned MemCpySize = ByValSize;
Akira Hatanaka6df3e7b2011-11-12 02:34:50 +00002559
2560 if (!IsRegLoc)
2561 LocMemOffset = VA.getLocMemOffset();
2562 else {
Craig Topperc5eaae42012-03-11 07:57:25 +00002563 const uint16_t *Reg = std::find(Mips64IntRegs, Mips64IntRegs + 8,
Akira Hatanaka6df3e7b2011-11-12 02:34:50 +00002564 VA.getLocReg());
Craig Topperc5eaae42012-03-11 07:57:25 +00002565 const uint16_t *RegEnd = Mips64IntRegs + 8;
Akira Hatanaka6df3e7b2011-11-12 02:34:50 +00002566
2567 // Copy double words to registers.
2568 for (; (Reg != RegEnd) && (ByValSize >= Offset + 8); ++Reg, Offset += 8) {
2569 SDValue LoadPtr = DAG.getNode(ISD::ADD, dl, PtrTy, Arg,
2570 DAG.getConstant(Offset, PtrTy));
2571 SDValue LoadVal = DAG.getLoad(MVT::i64, dl, Chain, LoadPtr,
2572 MachinePointerInfo(), false, false, false,
2573 Alignment);
2574 MemOpChains.push_back(LoadVal.getValue(1));
2575 RegsToPass.push_back(std::make_pair(*Reg, LoadVal));
2576 }
2577
Jia Liubb481f82012-02-28 07:46:26 +00002578 // Return if the struct has been fully copied.
Akira Hatanaka16040852011-11-15 18:42:25 +00002579 if (!(MemCpySize = ByValSize - Offset))
2580 return;
2581
Akira Hatanaka6df3e7b2011-11-12 02:34:50 +00002582 // If there is an argument register available, copy the remainder of the
2583 // byval argument with sub-doubleword loads and shifts.
Akira Hatanaka16040852011-11-15 18:42:25 +00002584 if (Reg != RegEnd) {
Akira Hatanaka6df3e7b2011-11-12 02:34:50 +00002585 assert((ByValSize < Offset + 8) &&
2586 "Size of the remainder should be smaller than 8-byte.");
2587 SDValue Val;
2588 for (unsigned LoadSize = 4; Offset < ByValSize; LoadSize /= 2) {
2589 unsigned RemSize = ByValSize - Offset;
2590
2591 if (RemSize < LoadSize)
2592 continue;
Jia Liubb481f82012-02-28 07:46:26 +00002593
Akira Hatanaka6df3e7b2011-11-12 02:34:50 +00002594 SDValue LoadPtr = DAG.getNode(ISD::ADD, dl, PtrTy, Arg,
2595 DAG.getConstant(Offset, PtrTy));
Jia Liubb481f82012-02-28 07:46:26 +00002596 SDValue LoadVal =
Akira Hatanaka6df3e7b2011-11-12 02:34:50 +00002597 DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i64, Chain, LoadPtr,
2598 MachinePointerInfo(), MVT::getIntegerVT(LoadSize * 8),
2599 false, false, Alignment);
2600 MemOpChains.push_back(LoadVal.getValue(1));
2601
2602 // Offset in number of bits from double word boundary.
2603 unsigned OffsetDW = (Offset % 8) * 8;
2604 unsigned Shamt = isLittle ? OffsetDW : 64 - (OffsetDW + LoadSize * 8);
2605 SDValue Shift = DAG.getNode(ISD::SHL, dl, MVT::i64, LoadVal,
2606 DAG.getConstant(Shamt, MVT::i32));
Jia Liubb481f82012-02-28 07:46:26 +00002607
Akira Hatanaka6df3e7b2011-11-12 02:34:50 +00002608 Val = Val.getNode() ? DAG.getNode(ISD::OR, dl, MVT::i64, Val, Shift) :
2609 Shift;
2610 Offset += LoadSize;
2611 Alignment = std::min(Alignment, LoadSize);
2612 }
Jia Liubb481f82012-02-28 07:46:26 +00002613
Akira Hatanaka6df3e7b2011-11-12 02:34:50 +00002614 RegsToPass.push_back(std::make_pair(*Reg, Val));
2615 return;
2616 }
2617 }
2618
Akira Hatanaka16040852011-11-15 18:42:25 +00002619 assert(MemCpySize && "MemCpySize must not be zero.");
2620
Akira Hatanakae2d529a2012-07-31 18:46:41 +00002621 // Copy remainder of byval arg to it with memcpy.
Akira Hatanaka16040852011-11-15 18:42:25 +00002622 SDValue Src = DAG.getNode(ISD::ADD, dl, PtrTy, Arg,
2623 DAG.getConstant(Offset, PtrTy));
Akira Hatanakae2d529a2012-07-31 18:46:41 +00002624 SDValue Dst = DAG.getNode(ISD::ADD, dl, MVT::i64, StackPtr,
2625 DAG.getIntPtrConstant(LocMemOffset));
2626 Chain = DAG.getMemcpy(Chain, dl, Dst, Src,
2627 DAG.getConstant(MemCpySize, PtrTy), Alignment,
2628 /*isVolatile=*/false, /*AlwaysInline=*/false,
2629 MachinePointerInfo(0), MachinePointerInfo(0));
2630 MemOpChains.push_back(Chain);
Akira Hatanaka6df3e7b2011-11-12 02:34:50 +00002631}
2632
Dan Gohman98ca4f22009-08-05 01:29:28 +00002633/// LowerCall - functions arguments are copied from virtual regs to
Nate Begeman5bf4b752009-01-26 03:15:54 +00002634/// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
Bruno Cardoso Lopesb37a7422010-02-06 19:20:49 +00002635/// TODO: isTailCall.
Dan Gohman98ca4f22009-08-05 01:29:28 +00002636SDValue
Justin Holewinskid2ea0e12012-05-25 16:35:28 +00002637MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
Dan Gohmand858e902010-04-17 15:26:15 +00002638 SmallVectorImpl<SDValue> &InVals) const {
Justin Holewinskid2ea0e12012-05-25 16:35:28 +00002639 SelectionDAG &DAG = CLI.DAG;
2640 DebugLoc &dl = CLI.DL;
2641 SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs;
2642 SmallVector<SDValue, 32> &OutVals = CLI.OutVals;
2643 SmallVector<ISD::InputArg, 32> &Ins = CLI.Ins;
Akira Hatanakae2d529a2012-07-31 18:46:41 +00002644 SDValue Chain = CLI.Chain;
Justin Holewinskid2ea0e12012-05-25 16:35:28 +00002645 SDValue Callee = CLI.Callee;
2646 bool &isTailCall = CLI.IsTailCall;
2647 CallingConv::ID CallConv = CLI.CallConv;
2648 bool isVarArg = CLI.IsVarArg;
2649
Evan Cheng0c439eb2010-01-27 00:07:07 +00002650 // MIPs target does not yet support tail call optimization.
2651 isTailCall = false;
Dan Gohman98ca4f22009-08-05 01:29:28 +00002652
Bruno Cardoso Lopes2ab22d12007-07-11 23:16:16 +00002653 MachineFunction &MF = DAG.getMachineFunction();
Bruno Cardoso Lopes2ab22d12007-07-11 23:16:16 +00002654 MachineFrameInfo *MFI = MF.getFrameInfo();
Akira Hatanakad37776d2011-05-20 21:39:54 +00002655 const TargetFrameLowering *TFL = MF.getTarget().getFrameLowering();
Bruno Cardoso Lopesc517cb02009-09-01 17:27:58 +00002656 bool IsPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_;
Akira Hatanaka17a1e872011-05-20 18:39:33 +00002657 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002658
2659 // Analyze operands of the call, assigning locations to each operand.
2660 SmallVector<CCValAssign, 16> ArgLocs;
Eric Christopher471e4222011-06-08 23:55:35 +00002661 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
Akira Hatanaka82099682011-12-19 19:52:25 +00002662 getTargetMachine(), ArgLocs, *DAG.getContext());
Bruno Cardoso Lopes2ab22d12007-07-11 23:16:16 +00002663
Akira Hatanaka777a1202012-06-13 18:06:00 +00002664 if (CallConv == CallingConv::Fast)
2665 CCInfo.AnalyzeCallOperands(Outs, CC_Mips_FastCC);
2666 else if (IsO32)
Akira Hatanaka95b8ae12011-05-19 18:06:05 +00002667 CCInfo.AnalyzeCallOperands(Outs, CC_MipsO32);
Akira Hatanaka49617092011-11-14 19:02:54 +00002668 else if (HasMips64)
2669 AnalyzeMips64CallOperands(CCInfo, Outs);
Akira Hatanakabdd2ce92011-05-23 21:13:59 +00002670 else
Dan Gohman98ca4f22009-08-05 01:29:28 +00002671 CCInfo.AnalyzeCallOperands(Outs, CC_Mips);
Wesley Peckbf17cfa2010-11-23 03:31:01 +00002672
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002673 // Get a count of how many bytes are to be pushed on the stack.
Akira Hatanaka3d21c242011-06-08 17:39:33 +00002674 unsigned NextStackOffset = CCInfo.getNextStackOffset();
Akira Hatanaka480eeb52012-07-26 23:27:01 +00002675 unsigned StackAlignment = TFL->getStackAlignment();
2676 NextStackOffset = RoundUpToAlignment(NextStackOffset, StackAlignment);
2677
2678 // Update size of the maximum argument space.
2679 // For O32, a minimum of four words (16 bytes) of argument space is
2680 // allocated.
2681 if (IsO32 && (CallConv != CallingConv::Fast))
2682 NextStackOffset = std::max(NextStackOffset, (unsigned)16);
Akira Hatanaka3d21c242011-06-08 17:39:33 +00002683
Akira Hatanakada7f5f12011-09-19 20:26:02 +00002684 // Chain is the output chain of the last Load/Store or CopyToReg node.
2685 // ByValChain is the output chain of the last Memcpy node created for copying
2686 // byval arguments to the stack.
Akira Hatanakada7f5f12011-09-19 20:26:02 +00002687 SDValue NextStackOffsetVal = DAG.getIntPtrConstant(NextStackOffset, true);
Akira Hatanakae2d529a2012-07-31 18:46:41 +00002688 Chain = DAG.getCALLSEQ_START(Chain, NextStackOffsetVal);
2689
2690 SDValue StackPtr = DAG.getCopyFromReg(Chain, dl,
2691 IsN64 ? Mips::SP_64 : Mips::SP,
2692 getPointerTy());
Akira Hatanaka3d21c242011-06-08 17:39:33 +00002693
Akira Hatanaka21afc632011-06-21 00:40:49 +00002694 // Get the frame index of the stack frame object that points to the location
2695 // of dynamically allocated area on the stack.
2696 int DynAllocFI = MipsFI->getDynAllocFI();
2697
Akira Hatanaka480eeb52012-07-26 23:27:01 +00002698 if (MipsFI->getMaxCallFrameSize() < NextStackOffset) {
Akira Hatanaka3d21c242011-06-08 17:39:33 +00002699 MipsFI->setMaxCallFrameSize(NextStackOffset);
2700
Akira Hatanaka21afc632011-06-21 00:40:49 +00002701 // Set the offsets relative to $sp of the $gp restore slot and dynamically
2702 // allocated stack space. These offsets must be aligned to a boundary
2703 // determined by the stack alignment of the ABI.
Akira Hatanaka21afc632011-06-21 00:40:49 +00002704 MFI->setObjectOffset(DynAllocFI, NextStackOffset);
Akira Hatanaka3d21c242011-06-08 17:39:33 +00002705 }
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002706
Bruno Cardoso Lopes225ca9c2008-07-05 19:05:21 +00002707 // With EABI is it possible to have 16 args on registers.
Dan Gohman475871a2008-07-27 21:46:04 +00002708 SmallVector<std::pair<unsigned, SDValue>, 16> RegsToPass;
2709 SmallVector<SDValue, 8> MemOpChains;
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002710
2711 // Walk the register/memloc assignments, inserting copies/loads.
2712 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
Dan Gohmanc9403652010-07-07 15:54:55 +00002713 SDValue Arg = OutVals[i];
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002714 CCValAssign &VA = ArgLocs[i];
Akira Hatanakae42f33b2011-10-28 19:49:00 +00002715 MVT ValVT = VA.getValVT(), LocVT = VA.getLocVT();
Akira Hatanaka6df3e7b2011-11-12 02:34:50 +00002716 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2717
2718 // ByVal Arg.
2719 if (Flags.isByVal()) {
2720 assert(Flags.getByValSize() &&
2721 "ByVal args of size 0 should have been ignored by front-end.");
2722 if (IsO32)
Akira Hatanakae2d529a2012-07-31 18:46:41 +00002723 WriteByValArg(Chain, dl, RegsToPass, MemOpChains, StackPtr,
Akira Hatanaka6df3e7b2011-11-12 02:34:50 +00002724 MFI, DAG, Arg, VA, Flags, getPointerTy(),
2725 Subtarget->isLittle());
2726 else
Akira Hatanakae2d529a2012-07-31 18:46:41 +00002727 PassByValArg64(Chain, dl, RegsToPass, MemOpChains, StackPtr,
Jia Liubb481f82012-02-28 07:46:26 +00002728 MFI, DAG, Arg, VA, Flags, getPointerTy(),
Akira Hatanaka6df3e7b2011-11-12 02:34:50 +00002729 Subtarget->isLittle());
2730 continue;
2731 }
Jia Liubb481f82012-02-28 07:46:26 +00002732
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002733 // Promote the value if needed.
2734 switch (VA.getLocInfo()) {
Torok Edwinc23197a2009-07-14 16:55:14 +00002735 default: llvm_unreachable("Unknown loc info!");
Wesley Peckbf17cfa2010-11-23 03:31:01 +00002736 case CCValAssign::Full:
Akira Hatanakae42f33b2011-10-28 19:49:00 +00002737 if (VA.isRegLoc()) {
2738 if ((ValVT == MVT::f32 && LocVT == MVT::i32) ||
2739 (ValVT == MVT::f64 && LocVT == MVT::i64))
2740 Arg = DAG.getNode(ISD::BITCAST, dl, LocVT, Arg);
2741 else if (ValVT == MVT::f64 && LocVT == MVT::i32) {
Akira Hatanaka4552c9a2011-04-15 21:51:11 +00002742 SDValue Lo = DAG.getNode(MipsISD::ExtractElementF64, dl, MVT::i32,
2743 Arg, DAG.getConstant(0, MVT::i32));
Akira Hatanaka0bf3dfb2011-04-15 21:00:26 +00002744 SDValue Hi = DAG.getNode(MipsISD::ExtractElementF64, dl, MVT::i32,
2745 Arg, DAG.getConstant(1, MVT::i32));
Akira Hatanaka99a2e982011-04-15 19:52:08 +00002746 if (!Subtarget->isLittle())
2747 std::swap(Lo, Hi);
Jia Liubb481f82012-02-28 07:46:26 +00002748 unsigned LocRegLo = VA.getLocReg();
Akira Hatanaka373e3a42011-09-23 00:58:33 +00002749 unsigned LocRegHigh = getNextIntArgReg(LocRegLo);
2750 RegsToPass.push_back(std::make_pair(LocRegLo, Lo));
2751 RegsToPass.push_back(std::make_pair(LocRegHigh, Hi));
Bruno Cardoso Lopesb53db4f2009-03-19 02:12:28 +00002752 continue;
Wesley Peckbf17cfa2010-11-23 03:31:01 +00002753 }
Bruno Cardoso Lopesb53db4f2009-03-19 02:12:28 +00002754 }
2755 break;
Chris Lattnere0b12152008-03-17 06:57:02 +00002756 case CCValAssign::SExt:
Akira Hatanakae42f33b2011-10-28 19:49:00 +00002757 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, LocVT, Arg);
Chris Lattnere0b12152008-03-17 06:57:02 +00002758 break;
2759 case CCValAssign::ZExt:
Akira Hatanakae42f33b2011-10-28 19:49:00 +00002760 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, LocVT, Arg);
Chris Lattnere0b12152008-03-17 06:57:02 +00002761 break;
2762 case CCValAssign::AExt:
Akira Hatanaka38bdc572012-02-17 02:20:26 +00002763 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, LocVT, Arg);
Chris Lattnere0b12152008-03-17 06:57:02 +00002764 break;
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002765 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +00002766
2767 // Arguments that can be passed on register must be kept at
Bruno Cardoso Lopesc7db5612007-11-05 03:02:32 +00002768 // RegsToPass vector
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002769 if (VA.isRegLoc()) {
2770 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
Chris Lattnere0b12152008-03-17 06:57:02 +00002771 continue;
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002772 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +00002773
Bruno Cardoso Lopesb53db4f2009-03-19 02:12:28 +00002774 // Register can't get to this point...
Chris Lattnere0b12152008-03-17 06:57:02 +00002775 assert(VA.isMemLoc());
Wesley Peckbf17cfa2010-11-23 03:31:01 +00002776
Wesley Peckbf17cfa2010-11-23 03:31:01 +00002777 // emit ISD::STORE whichs stores the
Chris Lattnere0b12152008-03-17 06:57:02 +00002778 // parameter value to a stack Location
Akira Hatanakae2d529a2012-07-31 18:46:41 +00002779 SDValue PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr,
2780 DAG.getIntPtrConstant(VA.getLocMemOffset()));
Chris Lattner8026a9d2010-09-21 17:50:43 +00002781 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
Akira Hatanaka82099682011-12-19 19:52:25 +00002782 MachinePointerInfo(), false, false, 0));
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002783 }
2784
Bruno Cardoso Lopes225ca9c2008-07-05 19:05:21 +00002785 // Transform all store nodes into one single node because all store
2786 // nodes are independent of each other.
Wesley Peckbf17cfa2010-11-23 03:31:01 +00002787 if (!MemOpChains.empty())
2788 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002789 &MemOpChains[0], MemOpChains.size());
2790
Bill Wendling056292f2008-09-16 21:48:12 +00002791 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
Wesley Peckbf17cfa2010-11-23 03:31:01 +00002792 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
2793 // node so that legalize doesn't hack it.
Akira Hatanakae42f33b2011-10-28 19:49:00 +00002794 unsigned char OpFlag;
2795 bool IsPICCall = (IsN64 || IsPIC); // true if calls are translated to jalr $25
Akira Hatanaka0dca9452011-12-09 01:45:12 +00002796 bool GlobalOrExternal = false;
Akira Hatanaka9777e7a2011-04-07 19:51:44 +00002797 SDValue CalleeLo;
Akira Hatanakaf49fde22011-04-04 17:11:07 +00002798
2799 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
Akira Hatanakae42f33b2011-10-28 19:49:00 +00002800 if (IsPICCall && G->getGlobal()->hasInternalLinkage()) {
2801 OpFlag = IsO32 ? MipsII::MO_GOT : MipsII::MO_GOT_PAGE;
2802 unsigned char LoFlag = IsO32 ? MipsII::MO_ABS_LO : MipsII::MO_GOT_OFST;
2803 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, getPointerTy(), 0,
2804 OpFlag);
Akira Hatanaka9777e7a2011-04-07 19:51:44 +00002805 CalleeLo = DAG.getTargetGlobalAddress(G->getGlobal(), dl, getPointerTy(),
Akira Hatanakae42f33b2011-10-28 19:49:00 +00002806 0, LoFlag);
Akira Hatanaka9777e7a2011-04-07 19:51:44 +00002807 } else {
Akira Hatanakae42f33b2011-10-28 19:49:00 +00002808 OpFlag = IsPICCall ? MipsII::MO_GOT_CALL : MipsII::MO_NO_FLAG;
Akira Hatanaka9777e7a2011-04-07 19:51:44 +00002809 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl,
2810 getPointerTy(), 0, OpFlag);
2811 }
2812
Akira Hatanaka0dca9452011-12-09 01:45:12 +00002813 GlobalOrExternal = true;
Akira Hatanakaf49fde22011-04-04 17:11:07 +00002814 }
2815 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
Akira Hatanakae42f33b2011-10-28 19:49:00 +00002816 if (IsN64 || (!IsO32 && IsPIC))
2817 OpFlag = MipsII::MO_GOT_DISP;
2818 else if (!IsPIC) // !N64 && static
2819 OpFlag = MipsII::MO_NO_FLAG;
2820 else // O32 & PIC
2821 OpFlag = MipsII::MO_GOT_CALL;
Akira Hatanaka82099682011-12-19 19:52:25 +00002822 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
2823 OpFlag);
Akira Hatanaka0dca9452011-12-09 01:45:12 +00002824 GlobalOrExternal = true;
Akira Hatanakaf49fde22011-04-04 17:11:07 +00002825 }
2826
Akira Hatanakacd0f90f2011-05-20 02:30:51 +00002827 SDValue InFlag;
2828
Akira Hatanakaf49fde22011-04-04 17:11:07 +00002829 // Create nodes that load address of callee and copy it to T9
Akira Hatanakae42f33b2011-10-28 19:49:00 +00002830 if (IsPICCall) {
Akira Hatanaka0dca9452011-12-09 01:45:12 +00002831 if (GlobalOrExternal) {
Akira Hatanaka9777e7a2011-04-07 19:51:44 +00002832 // Load callee address
Akira Hatanaka648f00c2012-02-24 22:34:47 +00002833 Callee = DAG.getNode(MipsISD::Wrapper, dl, getPointerTy(),
2834 GetGlobalReg(DAG, getPointerTy()), Callee);
Akira Hatanakae42f33b2011-10-28 19:49:00 +00002835 SDValue LoadValue = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
2836 Callee, MachinePointerInfo::getGOT(),
Pete Cooperd752e0f2011-11-08 18:42:53 +00002837 false, false, false, 0);
Akira Hatanaka9777e7a2011-04-07 19:51:44 +00002838
2839 // Use GOT+LO if callee has internal linkage.
2840 if (CalleeLo.getNode()) {
Akira Hatanakae42f33b2011-10-28 19:49:00 +00002841 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, getPointerTy(), CalleeLo);
2842 Callee = DAG.getNode(ISD::ADD, dl, getPointerTy(), LoadValue, Lo);
Akira Hatanaka9777e7a2011-04-07 19:51:44 +00002843 } else
2844 Callee = LoadValue;
Akira Hatanakaf49fde22011-04-04 17:11:07 +00002845 }
Akira Hatanaka0dca9452011-12-09 01:45:12 +00002846 }
Akira Hatanakaf49fde22011-04-04 17:11:07 +00002847
Akira Hatanakae11246c2012-07-26 02:24:43 +00002848 // T9 register operand.
2849 SDValue T9;
2850
Jia Liubb481f82012-02-28 07:46:26 +00002851 // T9 should contain the address of the callee function if
Akira Hatanaka0dca9452011-12-09 01:45:12 +00002852 // -reloction-model=pic or it is an indirect call.
2853 if (IsPICCall || !GlobalOrExternal) {
Akira Hatanakaf49fde22011-04-04 17:11:07 +00002854 // copy to T9
Akira Hatanakae42f33b2011-10-28 19:49:00 +00002855 unsigned T9Reg = IsN64 ? Mips::T9_64 : Mips::T9;
2856 Chain = DAG.getCopyToReg(Chain, dl, T9Reg, Callee, SDValue(0, 0));
Akira Hatanakaf49fde22011-04-04 17:11:07 +00002857 InFlag = Chain.getValue(1);
Akira Hatanakae11246c2012-07-26 02:24:43 +00002858
2859 if (Subtarget->inMips16Mode())
2860 T9 = DAG.getRegister(T9Reg, getPointerTy());
2861 else
2862 Callee = DAG.getRegister(T9Reg, getPointerTy());
Akira Hatanakaf49fde22011-04-04 17:11:07 +00002863 }
Bill Wendling056292f2008-09-16 21:48:12 +00002864
Akira Hatanaka92d4aec2012-05-12 03:19:04 +00002865 // Insert node "GP copy globalreg" before call to function.
2866 // Lazy-binding stubs require GP to point to the GOT.
2867 if (IsPICCall) {
2868 unsigned GPReg = IsN64 ? Mips::GP_64 : Mips::GP;
2869 EVT Ty = IsN64 ? MVT::i64 : MVT::i32;
2870 RegsToPass.push_back(std::make_pair(GPReg, GetGlobalReg(DAG, Ty)));
2871 }
2872
Akira Hatanakacd0f90f2011-05-20 02:30:51 +00002873 // Build a sequence of copy-to-reg nodes chained together with token
2874 // chain and flag operands which copy the outgoing args into registers.
2875 // The InFlag in necessary since all emitted instructions must be
2876 // stuck together.
2877 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2878 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2879 RegsToPass[i].second, InFlag);
2880 InFlag = Chain.getValue(1);
2881 }
2882
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002883 // MipsJmpLink = #chain, #target_address, #opt_in_flags...
Wesley Peckbf17cfa2010-11-23 03:31:01 +00002884 // = Chain, Callee, Reg#1, Reg#2, ...
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002885 //
2886 // Returns a chain & a flag for retval copy to use.
Chris Lattnerf1b4eaf2010-12-21 02:38:05 +00002887 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
Dan Gohman475871a2008-07-27 21:46:04 +00002888 SmallVector<SDValue, 8> Ops;
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002889 Ops.push_back(Chain);
Akira Hatanakae11246c2012-07-26 02:24:43 +00002890 Ops.push_back(Callee);
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002891
Wesley Peckbf17cfa2010-11-23 03:31:01 +00002892 // Add argument registers to the end of the list so that they are
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002893 // known live into the call.
2894 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2895 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2896 RegsToPass[i].second.getValueType()));
2897
Akira Hatanakae11246c2012-07-26 02:24:43 +00002898 // Add T9 register operand.
2899 if (T9.getNode())
2900 Ops.push_back(T9);
2901
Akira Hatanakab2930b92012-03-01 22:27:29 +00002902 // Add a register mask operand representing the call-preserved registers.
2903 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
2904 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
2905 assert(Mask && "Missing call preserved mask for calling convention");
2906 Ops.push_back(DAG.getRegisterMask(Mask));
2907
Gabor Greifba36cb52008-08-28 21:40:38 +00002908 if (InFlag.getNode())
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002909 Ops.push_back(InFlag);
2910
Dale Johannesen33c960f2009-02-04 20:06:27 +00002911 Chain = DAG.getNode(MipsISD::JmpLink, dl, NodeTys, &Ops[0], Ops.size());
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002912 InFlag = Chain.getValue(1);
2913
Bruno Cardoso Lopes3ed6f872010-01-30 18:32:07 +00002914 // Create the CALLSEQ_END node.
Akira Hatanaka480eeb52012-07-26 23:27:01 +00002915 Chain = DAG.getCALLSEQ_END(Chain, NextStackOffsetVal,
Bruno Cardoso Lopes3ed6f872010-01-30 18:32:07 +00002916 DAG.getIntPtrConstant(0, true), InFlag);
2917 InFlag = Chain.getValue(1);
2918
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002919 // Handle result values, copying them out of physregs into vregs that we
2920 // return.
Dan Gohman98ca4f22009-08-05 01:29:28 +00002921 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
2922 Ins, dl, DAG, InVals);
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002923}
2924
Dan Gohman98ca4f22009-08-05 01:29:28 +00002925/// LowerCallResult - Lower the result values of a call into the
2926/// appropriate copies out of appropriate physical registers.
2927SDValue
2928MipsTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
Sandeep Patel65c3c8f2009-09-02 08:44:58 +00002929 CallingConv::ID CallConv, bool isVarArg,
Dan Gohman98ca4f22009-08-05 01:29:28 +00002930 const SmallVectorImpl<ISD::InputArg> &Ins,
2931 DebugLoc dl, SelectionDAG &DAG,
Dan Gohmand858e902010-04-17 15:26:15 +00002932 SmallVectorImpl<SDValue> &InVals) const {
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002933 // Assign locations to each value returned by this call.
2934 SmallVector<CCValAssign, 16> RVLocs;
Eric Christopher471e4222011-06-08 23:55:35 +00002935 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
Akira Hatanaka864f6602012-06-14 21:10:56 +00002936 getTargetMachine(), RVLocs, *DAG.getContext());
Bruno Cardoso Lopes2ab22d12007-07-11 23:16:16 +00002937
Dan Gohman98ca4f22009-08-05 01:29:28 +00002938 CCInfo.AnalyzeCallResult(Ins, RetCC_Mips);
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002939
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002940 // Copy all of the result registers out of their specified physreg.
2941 for (unsigned i = 0; i != RVLocs.size(); ++i) {
Dale Johannesen33c960f2009-02-04 20:06:27 +00002942 Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(),
Dan Gohman98ca4f22009-08-05 01:29:28 +00002943 RVLocs[i].getValVT(), InFlag).getValue(1);
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002944 InFlag = Chain.getValue(2);
Dan Gohman98ca4f22009-08-05 01:29:28 +00002945 InVals.push_back(Chain.getValue(0));
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002946 }
Bruno Cardoso Lopesc7db5612007-11-05 03:02:32 +00002947
Dan Gohman98ca4f22009-08-05 01:29:28 +00002948 return Chain;
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002949}
2950
Akira Hatanaka4552c9a2011-04-15 21:51:11 +00002951//===----------------------------------------------------------------------===//
Dan Gohman98ca4f22009-08-05 01:29:28 +00002952// Formal Arguments Calling Convention Implementation
Akira Hatanaka4552c9a2011-04-15 21:51:11 +00002953//===----------------------------------------------------------------------===//
Akira Hatanaka4231c7e2011-05-24 19:18:33 +00002954static void ReadByValArg(MachineFunction &MF, SDValue Chain, DebugLoc dl,
Akira Hatanaka864f6602012-06-14 21:10:56 +00002955 std::vector<SDValue> &OutChains,
Akira Hatanaka4231c7e2011-05-24 19:18:33 +00002956 SelectionDAG &DAG, unsigned NumWords, SDValue FIN,
Akira Hatanaka864f6602012-06-14 21:10:56 +00002957 const CCValAssign &VA, const ISD::ArgFlagsTy &Flags,
Akira Hatanakab4549e12012-03-27 03:13:56 +00002958 const Argument *FuncArg) {
Akira Hatanaka4231c7e2011-05-24 19:18:33 +00002959 unsigned LocMem = VA.getLocMemOffset();
2960 unsigned FirstWord = LocMem / 4;
2961
2962 // copy register A0 - A3 to frame object
2963 for (unsigned i = 0; i < NumWords; ++i) {
2964 unsigned CurWord = FirstWord + i;
2965 if (CurWord >= O32IntRegsSize)
2966 break;
2967
2968 unsigned SrcReg = O32IntRegs[CurWord];
Craig Topper420761a2012-04-20 07:30:17 +00002969 unsigned Reg = AddLiveIn(MF, SrcReg, &Mips::CPURegsRegClass);
Akira Hatanaka4231c7e2011-05-24 19:18:33 +00002970 SDValue StorePtr = DAG.getNode(ISD::ADD, dl, MVT::i32, FIN,
2971 DAG.getConstant(i * 4, MVT::i32));
2972 SDValue Store = DAG.getStore(Chain, dl, DAG.getRegister(Reg, MVT::i32),
Akira Hatanakab4549e12012-03-27 03:13:56 +00002973 StorePtr, MachinePointerInfo(FuncArg, i * 4),
2974 false, false, 0);
Akira Hatanaka4231c7e2011-05-24 19:18:33 +00002975 OutChains.push_back(Store);
2976 }
2977}
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002978
Akira Hatanaka3a5257d2011-11-12 02:29:58 +00002979// Create frame object on stack and copy registers used for byval passing to it.
2980static unsigned
2981CopyMips64ByValRegs(MachineFunction &MF, SDValue Chain, DebugLoc dl,
Akira Hatanaka864f6602012-06-14 21:10:56 +00002982 std::vector<SDValue> &OutChains, SelectionDAG &DAG,
2983 const CCValAssign &VA, const ISD::ArgFlagsTy &Flags,
Akira Hatanaka3a5257d2011-11-12 02:29:58 +00002984 MachineFrameInfo *MFI, bool IsRegLoc,
2985 SmallVectorImpl<SDValue> &InVals, MipsFunctionInfo *MipsFI,
Akira Hatanakab4549e12012-03-27 03:13:56 +00002986 EVT PtrTy, const Argument *FuncArg) {
Craig Topperc5eaae42012-03-11 07:57:25 +00002987 const uint16_t *Reg = Mips64IntRegs + 8;
Akira Hatanaka3a5257d2011-11-12 02:29:58 +00002988 int FOOffset; // Frame object offset from virtual frame pointer.
2989
2990 if (IsRegLoc) {
2991 Reg = std::find(Mips64IntRegs, Mips64IntRegs + 8, VA.getLocReg());
2992 FOOffset = (Reg - Mips64IntRegs) * 8 - 8 * 8;
Akira Hatanaka3a5257d2011-11-12 02:29:58 +00002993 }
2994 else
2995 FOOffset = VA.getLocMemOffset();
2996
2997 // Create frame object.
2998 unsigned NumRegs = (Flags.getByValSize() + 7) / 8;
2999 unsigned LastFI = MFI->CreateFixedObject(NumRegs * 8, FOOffset, true);
3000 SDValue FIN = DAG.getFrameIndex(LastFI, PtrTy);
3001 InVals.push_back(FIN);
3002
3003 // Copy arg registers.
3004 for (unsigned I = 0; (Reg != Mips64IntRegs + 8) && (I < NumRegs);
3005 ++Reg, ++I) {
Craig Topper420761a2012-04-20 07:30:17 +00003006 unsigned VReg = AddLiveIn(MF, *Reg, &Mips::CPU64RegsRegClass);
Akira Hatanaka3a5257d2011-11-12 02:29:58 +00003007 SDValue StorePtr = DAG.getNode(ISD::ADD, dl, PtrTy, FIN,
3008 DAG.getConstant(I * 8, PtrTy));
3009 SDValue Store = DAG.getStore(Chain, dl, DAG.getRegister(VReg, MVT::i64),
Akira Hatanakab4549e12012-03-27 03:13:56 +00003010 StorePtr, MachinePointerInfo(FuncArg, I * 8),
3011 false, false, 0);
Akira Hatanaka3a5257d2011-11-12 02:29:58 +00003012 OutChains.push_back(Store);
3013 }
Jia Liubb481f82012-02-28 07:46:26 +00003014
Akira Hatanaka3a5257d2011-11-12 02:29:58 +00003015 return LastFI;
3016}
3017
Wesley Peckbf17cfa2010-11-23 03:31:01 +00003018/// LowerFormalArguments - transform physical registers into virtual registers
Bruno Cardoso Lopesb37a7422010-02-06 19:20:49 +00003019/// and generate load operations for arguments places on the stack.
Dan Gohman98ca4f22009-08-05 01:29:28 +00003020SDValue
3021MipsTargetLowering::LowerFormalArguments(SDValue Chain,
Akira Hatanaka0bf3dfb2011-04-15 21:00:26 +00003022 CallingConv::ID CallConv,
3023 bool isVarArg,
Akira Hatanaka82099682011-12-19 19:52:25 +00003024 const SmallVectorImpl<ISD::InputArg> &Ins,
Akira Hatanaka0bf3dfb2011-04-15 21:00:26 +00003025 DebugLoc dl, SelectionDAG &DAG,
3026 SmallVectorImpl<SDValue> &InVals)
Akira Hatanaka4552c9a2011-04-15 21:51:11 +00003027 const {
Bruno Cardoso Lopesf7f3b502008-08-04 07:12:52 +00003028 MachineFunction &MF = DAG.getMachineFunction();
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00003029 MachineFrameInfo *MFI = MF.getFrameInfo();
Bruno Cardoso Lopesa2b1bb52007-08-28 05:08:16 +00003030 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
Bruno Cardoso Lopes2ab22d12007-07-11 23:16:16 +00003031
Dan Gohman1e93df62010-04-17 14:41:14 +00003032 MipsFI->setVarArgsFrameIndex(0);
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00003033
Bruno Cardoso Lopesb37a7422010-02-06 19:20:49 +00003034 // Used with vargs to acumulate store chains.
3035 std::vector<SDValue> OutChains;
3036
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00003037 // Assign locations to all of the incoming arguments.
3038 SmallVector<CCValAssign, 16> ArgLocs;
Eric Christopher471e4222011-06-08 23:55:35 +00003039 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
Akira Hatanaka82099682011-12-19 19:52:25 +00003040 getTargetMachine(), ArgLocs, *DAG.getContext());
Bruno Cardoso Lopes2ab22d12007-07-11 23:16:16 +00003041
Akira Hatanaka777a1202012-06-13 18:06:00 +00003042 if (CallConv == CallingConv::Fast)
3043 CCInfo.AnalyzeFormalArguments(Ins, CC_Mips_FastCC);
3044 else if (IsO32)
Akira Hatanaka95b8ae12011-05-19 18:06:05 +00003045 CCInfo.AnalyzeFormalArguments(Ins, CC_MipsO32);
Bruno Cardoso Lopesb53db4f2009-03-19 02:12:28 +00003046 else
Dan Gohman98ca4f22009-08-05 01:29:28 +00003047 CCInfo.AnalyzeFormalArguments(Ins, CC_Mips);
Bruno Cardoso Lopesb53db4f2009-03-19 02:12:28 +00003048
Akira Hatanakab4549e12012-03-27 03:13:56 +00003049 Function::const_arg_iterator FuncArg =
3050 DAG.getMachineFunction().getFunction()->arg_begin();
Akira Hatanaka43299772011-05-20 23:22:14 +00003051 int LastFI = 0;// MipsFI->LastInArgFI is 0 at the entry of this function.
Bruno Cardoso Lopes225ca9c2008-07-05 19:05:21 +00003052
Akira Hatanakab4549e12012-03-27 03:13:56 +00003053 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i, ++FuncArg) {
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00003054 CCValAssign &VA = ArgLocs[i];
Akira Hatanakafeaa4c32011-10-28 19:55:48 +00003055 EVT ValVT = VA.getValVT();
Akira Hatanaka3a5257d2011-11-12 02:29:58 +00003056 ISD::ArgFlagsTy Flags = Ins[i].Flags;
3057 bool IsRegLoc = VA.isRegLoc();
3058
3059 if (Flags.isByVal()) {
3060 assert(Flags.getByValSize() &&
3061 "ByVal args of size 0 should have been ignored by front-end.");
3062 if (IsO32) {
3063 unsigned NumWords = (Flags.getByValSize() + 3) / 4;
3064 LastFI = MFI->CreateFixedObject(NumWords * 4, VA.getLocMemOffset(),
3065 true);
3066 SDValue FIN = DAG.getFrameIndex(LastFI, getPointerTy());
3067 InVals.push_back(FIN);
Akira Hatanakab4549e12012-03-27 03:13:56 +00003068 ReadByValArg(MF, Chain, dl, OutChains, DAG, NumWords, FIN, VA, Flags,
3069 &*FuncArg);
Akira Hatanaka3a5257d2011-11-12 02:29:58 +00003070 } else // N32/64
3071 LastFI = CopyMips64ByValRegs(MF, Chain, dl, OutChains, DAG, VA, Flags,
3072 MFI, IsRegLoc, InVals, MipsFI,
Akira Hatanakab4549e12012-03-27 03:13:56 +00003073 getPointerTy(), &*FuncArg);
Akira Hatanaka3a5257d2011-11-12 02:29:58 +00003074 continue;
3075 }
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00003076
3077 // Arguments stored on registers
Akira Hatanaka3a5257d2011-11-12 02:29:58 +00003078 if (IsRegLoc) {
Owen Andersone50ed302009-08-10 22:56:29 +00003079 EVT RegVT = VA.getLocVT();
Akira Hatanakab4d8d312011-05-24 00:23:52 +00003080 unsigned ArgReg = VA.getLocReg();
Craig Topper44d23822012-02-22 05:59:10 +00003081 const TargetRegisterClass *RC;
Bruno Cardoso Lopesb53db4f2009-03-19 02:12:28 +00003082
Owen Anderson825b72b2009-08-11 20:47:22 +00003083 if (RegVT == MVT::i32)
Craig Topper420761a2012-04-20 07:30:17 +00003084 RC = &Mips::CPURegsRegClass;
Akira Hatanaka95934842011-09-24 01:34:44 +00003085 else if (RegVT == MVT::i64)
Craig Topper420761a2012-04-20 07:30:17 +00003086 RC = &Mips::CPU64RegsRegClass;
Wesley Peckbf17cfa2010-11-23 03:31:01 +00003087 else if (RegVT == MVT::f32)
Craig Topper420761a2012-04-20 07:30:17 +00003088 RC = &Mips::FGR32RegClass;
Akira Hatanaka09dd60f2011-09-26 21:37:50 +00003089 else if (RegVT == MVT::f64)
Craig Topper420761a2012-04-20 07:30:17 +00003090 RC = HasMips64 ? &Mips::FGR64RegClass : &Mips::AFGR64RegClass;
Akira Hatanaka09dd60f2011-09-26 21:37:50 +00003091 else
Bruno Cardoso Lopesb37a7422010-02-06 19:20:49 +00003092 llvm_unreachable("RegVT not supported by FormalArguments Lowering");
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00003093
Wesley Peckbf17cfa2010-11-23 03:31:01 +00003094 // Transform the arguments stored on
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00003095 // physical registers into virtual ones
Akira Hatanakab4d8d312011-05-24 00:23:52 +00003096 unsigned Reg = AddLiveIn(DAG.getMachineFunction(), ArgReg, RC);
Dan Gohman98ca4f22009-08-05 01:29:28 +00003097 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
Wesley Peckbf17cfa2010-11-23 03:31:01 +00003098
3099 // If this is an 8 or 16-bit value, it has been passed promoted
3100 // to 32 bits. Insert an assert[sz]ext to capture this, then
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00003101 // truncate to the right size.
Bruno Cardoso Lopesb53db4f2009-03-19 02:12:28 +00003102 if (VA.getLocInfo() != CCValAssign::Full) {
Chris Lattnerd4015072009-03-26 05:28:14 +00003103 unsigned Opcode = 0;
Bruno Cardoso Lopesb53db4f2009-03-19 02:12:28 +00003104 if (VA.getLocInfo() == CCValAssign::SExt)
3105 Opcode = ISD::AssertSext;
3106 else if (VA.getLocInfo() == CCValAssign::ZExt)
3107 Opcode = ISD::AssertZext;
Chris Lattnerd4015072009-03-26 05:28:14 +00003108 if (Opcode)
Wesley Peckbf17cfa2010-11-23 03:31:01 +00003109 ArgValue = DAG.getNode(Opcode, dl, RegVT, ArgValue,
Akira Hatanakafeaa4c32011-10-28 19:55:48 +00003110 DAG.getValueType(ValVT));
3111 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, ValVT, ArgValue);
Bruno Cardoso Lopesb53db4f2009-03-19 02:12:28 +00003112 }
3113
Akira Hatanakafeaa4c32011-10-28 19:55:48 +00003114 // Handle floating point arguments passed in integer registers.
3115 if ((RegVT == MVT::i32 && ValVT == MVT::f32) ||
3116 (RegVT == MVT::i64 && ValVT == MVT::f64))
3117 ArgValue = DAG.getNode(ISD::BITCAST, dl, ValVT, ArgValue);
3118 else if (IsO32 && RegVT == MVT::i32 && ValVT == MVT::f64) {
3119 unsigned Reg2 = AddLiveIn(DAG.getMachineFunction(),
3120 getNextIntArgReg(ArgReg), RC);
3121 SDValue ArgValue2 = DAG.getCopyFromReg(Chain, dl, Reg2, RegVT);
3122 if (!Subtarget->isLittle())
3123 std::swap(ArgValue, ArgValue2);
3124 ArgValue = DAG.getNode(MipsISD::BuildPairF64, dl, MVT::f64,
3125 ArgValue, ArgValue2);
Bruno Cardoso Lopesb53db4f2009-03-19 02:12:28 +00003126 }
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00003127
Dan Gohman98ca4f22009-08-05 01:29:28 +00003128 InVals.push_back(ArgValue);
Bruno Cardoso Lopes225ca9c2008-07-05 19:05:21 +00003129 } else { // VA.isRegLoc()
3130
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00003131 // sanity check
3132 assert(VA.isMemLoc());
Bruno Cardoso Lopesb37a7422010-02-06 19:20:49 +00003133
Wesley Peckbf17cfa2010-11-23 03:31:01 +00003134 // The stack pointer offset is relative to the caller stack frame.
Akira Hatanakafeaa4c32011-10-28 19:55:48 +00003135 LastFI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
Akira Hatanakab4d8d312011-05-24 00:23:52 +00003136 VA.getLocMemOffset(), true);
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00003137
3138 // Create load nodes to retrieve arguments from the stack
Akira Hatanaka43299772011-05-20 23:22:14 +00003139 SDValue FIN = DAG.getFrameIndex(LastFI, getPointerTy());
Akira Hatanakafeaa4c32011-10-28 19:55:48 +00003140 InVals.push_back(DAG.getLoad(ValVT, dl, Chain, FIN,
Akira Hatanaka43299772011-05-20 23:22:14 +00003141 MachinePointerInfo::getFixedStack(LastFI),
Pete Cooperd752e0f2011-11-08 18:42:53 +00003142 false, false, false, 0));
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00003143 }
3144 }
Bruno Cardoso Lopes225ca9c2008-07-05 19:05:21 +00003145
3146 // The mips ABIs for returning structs by value requires that we copy
3147 // the sret argument into $v0 for the return. Save the argument into
3148 // a virtual register so that we can access it from the return points.
3149 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
3150 unsigned Reg = MipsFI->getSRetReturnReg();
3151 if (!Reg) {
Owen Anderson825b72b2009-08-11 20:47:22 +00003152 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i32));
Bruno Cardoso Lopes225ca9c2008-07-05 19:05:21 +00003153 MipsFI->setSRetReturnReg(Reg);
3154 }
Dan Gohman98ca4f22009-08-05 01:29:28 +00003155 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
Owen Anderson825b72b2009-08-11 20:47:22 +00003156 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
Bruno Cardoso Lopes225ca9c2008-07-05 19:05:21 +00003157 }
3158
Akira Hatanakabad53f42011-11-14 19:01:09 +00003159 if (isVarArg) {
3160 unsigned NumOfRegs = IsO32 ? 4 : 8;
Craig Topperc5eaae42012-03-11 07:57:25 +00003161 const uint16_t *ArgRegs = IsO32 ? O32IntRegs : Mips64IntRegs;
Akira Hatanakabad53f42011-11-14 19:01:09 +00003162 unsigned Idx = CCInfo.getFirstUnallocated(ArgRegs, NumOfRegs);
3163 int FirstRegSlotOffset = IsO32 ? 0 : -64 ; // offset of $a0's slot.
Craig Topper420761a2012-04-20 07:30:17 +00003164 const TargetRegisterClass *RC = IsO32 ?
3165 (const TargetRegisterClass*)&Mips::CPURegsRegClass :
3166 (const TargetRegisterClass*)&Mips::CPU64RegsRegClass;
Akira Hatanakabad53f42011-11-14 19:01:09 +00003167 unsigned RegSize = RC->getSize();
3168 int RegSlotOffset = FirstRegSlotOffset + Idx * RegSize;
3169
3170 // Offset of the first variable argument from stack pointer.
3171 int FirstVaArgOffset;
3172
3173 if (IsO32 || (Idx == NumOfRegs)) {
3174 FirstVaArgOffset =
3175 (CCInfo.getNextStackOffset() + RegSize - 1) / RegSize * RegSize;
3176 } else
3177 FirstVaArgOffset = RegSlotOffset;
3178
Akira Hatanakab4d8d312011-05-24 00:23:52 +00003179 // Record the frame index of the first variable argument
Eric Christopher471e4222011-06-08 23:55:35 +00003180 // which is a value necessary to VASTART.
Akira Hatanakabad53f42011-11-14 19:01:09 +00003181 LastFI = MFI->CreateFixedObject(RegSize, FirstVaArgOffset, true);
Akira Hatanakab4d8d312011-05-24 00:23:52 +00003182 MipsFI->setVarArgsFrameIndex(LastFI);
Akira Hatanakaedacba82011-05-25 17:32:06 +00003183
Akira Hatanakabad53f42011-11-14 19:01:09 +00003184 // Copy the integer registers that have not been used for argument passing
3185 // to the argument register save area. For O32, the save area is allocated
3186 // in the caller's stack frame, while for N32/64, it is allocated in the
3187 // callee's stack frame.
3188 for (int StackOffset = RegSlotOffset;
3189 Idx < NumOfRegs; ++Idx, StackOffset += RegSize) {
3190 unsigned Reg = AddLiveIn(DAG.getMachineFunction(), ArgRegs[Idx], RC);
3191 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg,
3192 MVT::getIntegerVT(RegSize * 8));
3193 LastFI = MFI->CreateFixedObject(RegSize, StackOffset, true);
Akira Hatanakab4d8d312011-05-24 00:23:52 +00003194 SDValue PtrOff = DAG.getFrameIndex(LastFI, getPointerTy());
3195 OutChains.push_back(DAG.getStore(Chain, dl, ArgValue, PtrOff,
Akira Hatanaka82099682011-12-19 19:52:25 +00003196 MachinePointerInfo(), false, false, 0));
Bruno Cardoso Lopesb37a7422010-02-06 19:20:49 +00003197 }
3198 }
3199
Akira Hatanaka43299772011-05-20 23:22:14 +00003200 MipsFI->setLastInArgFI(LastFI);
3201
Wesley Peckbf17cfa2010-11-23 03:31:01 +00003202 // All stores are grouped in one node to allow the matching between
Bruno Cardoso Lopesb37a7422010-02-06 19:20:49 +00003203 // the size of Ins and InVals. This only happens when on varg functions
3204 if (!OutChains.empty()) {
3205 OutChains.push_back(Chain);
3206 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3207 &OutChains[0], OutChains.size());
3208 }
3209
Dan Gohman98ca4f22009-08-05 01:29:28 +00003210 return Chain;
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00003211}
3212
Akira Hatanaka4552c9a2011-04-15 21:51:11 +00003213//===----------------------------------------------------------------------===//
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00003214// Return Value Calling Convention Implementation
Akira Hatanaka4552c9a2011-04-15 21:51:11 +00003215//===----------------------------------------------------------------------===//
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00003216
Dan Gohman98ca4f22009-08-05 01:29:28 +00003217SDValue
3218MipsTargetLowering::LowerReturn(SDValue Chain,
Sandeep Patel65c3c8f2009-09-02 08:44:58 +00003219 CallingConv::ID CallConv, bool isVarArg,
Dan Gohman98ca4f22009-08-05 01:29:28 +00003220 const SmallVectorImpl<ISD::OutputArg> &Outs,
Dan Gohmanc9403652010-07-07 15:54:55 +00003221 const SmallVectorImpl<SDValue> &OutVals,
Dan Gohmand858e902010-04-17 15:26:15 +00003222 DebugLoc dl, SelectionDAG &DAG) const {
Dan Gohman98ca4f22009-08-05 01:29:28 +00003223
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00003224 // CCValAssign - represent the assignment of
3225 // the return value to a location
3226 SmallVector<CCValAssign, 16> RVLocs;
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00003227
3228 // CCState - Info about the registers and stack slot.
Eric Christopher471e4222011-06-08 23:55:35 +00003229 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
Akira Hatanaka864f6602012-06-14 21:10:56 +00003230 getTargetMachine(), RVLocs, *DAG.getContext());
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00003231
Dan Gohman98ca4f22009-08-05 01:29:28 +00003232 // Analize return values.
3233 CCInfo.AnalyzeReturn(Outs, RetCC_Mips);
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00003234
Wesley Peckbf17cfa2010-11-23 03:31:01 +00003235 // If this is the first return lowered for this function, add
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00003236 // the regs to the liveout set for the function.
Chris Lattner84bc5422007-12-31 04:13:23 +00003237 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00003238 for (unsigned i = 0; i != RVLocs.size(); ++i)
Bruno Cardoso Lopes2ab22d12007-07-11 23:16:16 +00003239 if (RVLocs[i].isRegLoc())
Akira Hatanaka4552c9a2011-04-15 21:51:11 +00003240 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00003241 }
3242
Dan Gohman475871a2008-07-27 21:46:04 +00003243 SDValue Flag;
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00003244
3245 // Copy the result values into the output registers.
3246 for (unsigned i = 0; i != RVLocs.size(); ++i) {
3247 CCValAssign &VA = RVLocs[i];
3248 assert(VA.isRegLoc() && "Can only return in registers!");
3249
Akira Hatanaka82099682011-12-19 19:52:25 +00003250 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), OutVals[i], Flag);
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00003251
3252 // guarantee that all emitted copies are
3253 // stuck together, avoiding something bad
3254 Flag = Chain.getValue(1);
3255 }
3256
Bruno Cardoso Lopes225ca9c2008-07-05 19:05:21 +00003257 // The mips ABIs for returning structs by value requires that we copy
3258 // the sret argument into $v0 for the return. We saved the argument into
3259 // a virtual register in the entry block, so now we copy the value out
3260 // and into $v0.
3261 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
3262 MachineFunction &MF = DAG.getMachineFunction();
3263 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
3264 unsigned Reg = MipsFI->getSRetReturnReg();
3265
Wesley Peckbf17cfa2010-11-23 03:31:01 +00003266 if (!Reg)
Torok Edwinc23197a2009-07-14 16:55:14 +00003267 llvm_unreachable("sret virtual register not created in the entry block");
Dale Johannesena05dca42009-02-04 23:02:30 +00003268 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
Bruno Cardoso Lopes225ca9c2008-07-05 19:05:21 +00003269
Dale Johannesena05dca42009-02-04 23:02:30 +00003270 Chain = DAG.getCopyToReg(Chain, dl, Mips::V0, Val, Flag);
Bruno Cardoso Lopes225ca9c2008-07-05 19:05:21 +00003271 Flag = Chain.getValue(1);
3272 }
3273
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00003274 // Return on Mips is always a "jr $ra"
Gabor Greifba36cb52008-08-28 21:40:38 +00003275 if (Flag.getNode())
Akira Hatanaka182ef6f2012-07-10 00:19:06 +00003276 return DAG.getNode(MipsISD::Ret, dl, MVT::Other, Chain, Flag);
3277
3278 // Return Void
3279 return DAG.getNode(MipsISD::Ret, dl, MVT::Other, Chain);
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00003280}
Bruno Cardoso Lopes84f47c52007-08-21 16:09:25 +00003281
Akira Hatanaka4552c9a2011-04-15 21:51:11 +00003282//===----------------------------------------------------------------------===//
Bruno Cardoso Lopes84f47c52007-08-21 16:09:25 +00003283// Mips Inline Assembly Support
Akira Hatanaka4552c9a2011-04-15 21:51:11 +00003284//===----------------------------------------------------------------------===//
Bruno Cardoso Lopes84f47c52007-08-21 16:09:25 +00003285
3286/// getConstraintType - Given a constraint letter, return the type of
3287/// constraint it is for this target.
3288MipsTargetLowering::ConstraintType MipsTargetLowering::
Wesley Peckbf17cfa2010-11-23 03:31:01 +00003289getConstraintType(const std::string &Constraint) const
Bruno Cardoso Lopes84f47c52007-08-21 16:09:25 +00003290{
Wesley Peckbf17cfa2010-11-23 03:31:01 +00003291 // Mips specific constrainy
Bruno Cardoso Lopes225ca9c2008-07-05 19:05:21 +00003292 // GCC config/mips/constraints.md
3293 //
Wesley Peckbf17cfa2010-11-23 03:31:01 +00003294 // 'd' : An address register. Equivalent to r
3295 // unless generating MIPS16 code.
3296 // 'y' : Equivalent to r; retained for
3297 // backwards compatibility.
Eric Christopher1d5a3922012-05-07 06:25:10 +00003298 // 'c' : A register suitable for use in an indirect
3299 // jump. This will always be $25 for -mabicalls.
Eric Christopheraf97f732012-05-07 06:25:19 +00003300 // 'l' : The lo register. 1 word storage.
3301 // 'x' : The hilo register pair. Double word storage.
Bruno Cardoso Lopes84f47c52007-08-21 16:09:25 +00003302 if (Constraint.size() == 1) {
Bruno Cardoso Lopes84f47c52007-08-21 16:09:25 +00003303 switch (Constraint[0]) {
3304 default : break;
Wesley Peckbf17cfa2010-11-23 03:31:01 +00003305 case 'd':
3306 case 'y':
Bruno Cardoso Lopes225ca9c2008-07-05 19:05:21 +00003307 case 'f':
Eric Christopher1d5a3922012-05-07 06:25:10 +00003308 case 'c':
Eric Christopher4adbefe2012-05-07 06:25:15 +00003309 case 'l':
Eric Christopheraf97f732012-05-07 06:25:19 +00003310 case 'x':
Bruno Cardoso Lopes84f47c52007-08-21 16:09:25 +00003311 return C_RegisterClass;
Bruno Cardoso Lopes84f47c52007-08-21 16:09:25 +00003312 }
3313 }
3314 return TargetLowering::getConstraintType(Constraint);
3315}
3316
John Thompson44ab89e2010-10-29 17:29:13 +00003317/// Examine constraint type and operand type and determine a weight value.
3318/// This object must already have been set up with the operand type
3319/// and the current alternative constraint selected.
3320TargetLowering::ConstraintWeight
3321MipsTargetLowering::getSingleConstraintMatchWeight(
3322 AsmOperandInfo &info, const char *constraint) const {
3323 ConstraintWeight weight = CW_Invalid;
3324 Value *CallOperandVal = info.CallOperandVal;
3325 // If we don't have a value, we can't do a match,
3326 // but allow it at the lowest weight.
3327 if (CallOperandVal == NULL)
3328 return CW_Default;
Chris Lattnerdb125cf2011-07-18 04:54:35 +00003329 Type *type = CallOperandVal->getType();
John Thompson44ab89e2010-10-29 17:29:13 +00003330 // Look at the constraint type.
3331 switch (*constraint) {
3332 default:
3333 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
3334 break;
Wesley Peckbf17cfa2010-11-23 03:31:01 +00003335 case 'd':
3336 case 'y':
John Thompson44ab89e2010-10-29 17:29:13 +00003337 if (type->isIntegerTy())
3338 weight = CW_Register;
3339 break;
3340 case 'f':
3341 if (type->isFloatTy())
3342 weight = CW_Register;
3343 break;
Eric Christopher1d5a3922012-05-07 06:25:10 +00003344 case 'c': // $25 for indirect jumps
Eric Christopher4adbefe2012-05-07 06:25:15 +00003345 case 'l': // lo register
Eric Christopheraf97f732012-05-07 06:25:19 +00003346 case 'x': // hilo register pair
Eric Christopher1d5a3922012-05-07 06:25:10 +00003347 if (type->isIntegerTy())
3348 weight = CW_SpecificReg;
3349 break;
Eric Christopher50ab0392012-05-07 03:13:32 +00003350 case 'I': // signed 16 bit immediate
Eric Christophere5076d42012-05-07 03:13:42 +00003351 case 'J': // integer zero
Eric Christopherf49f8462012-05-07 05:46:29 +00003352 case 'K': // unsigned 16 bit immediate
Eric Christopher5ac47bb2012-05-07 05:46:37 +00003353 case 'L': // signed 32 bit immediate where lower 16 bits are 0
Eric Christopher60cfc792012-05-07 05:46:43 +00003354 case 'N': // immediate in the range of -65535 to -1 (inclusive)
Eric Christopher1ce20342012-05-07 05:46:48 +00003355 case 'O': // signed 15 bit immediate (+- 16383)
Eric Christopher54412a72012-05-07 06:25:02 +00003356 case 'P': // immediate in the range of 65535 to 1 (inclusive)
Eric Christopher50ab0392012-05-07 03:13:32 +00003357 if (isa<ConstantInt>(CallOperandVal))
3358 weight = CW_Constant;
3359 break;
John Thompson44ab89e2010-10-29 17:29:13 +00003360 }
3361 return weight;
3362}
3363
Eric Christopher38d64262011-06-29 19:33:04 +00003364/// Given a register class constraint, like 'r', if this corresponds directly
3365/// to an LLVM register class, return a register of 0 and the register class
3366/// pointer.
Bruno Cardoso Lopes84f47c52007-08-21 16:09:25 +00003367std::pair<unsigned, const TargetRegisterClass*> MipsTargetLowering::
Owen Andersone50ed302009-08-10 22:56:29 +00003368getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const
Bruno Cardoso Lopes84f47c52007-08-21 16:09:25 +00003369{
3370 if (Constraint.size() == 1) {
3371 switch (Constraint[0]) {
Eric Christopher314aff12011-06-29 19:04:31 +00003372 case 'd': // Address register. Same as 'r' unless generating MIPS16 code.
3373 case 'y': // Same as 'r'. Exists for compatibility.
Bruno Cardoso Lopes84f47c52007-08-21 16:09:25 +00003374 case 'r':
Eric Christopher3ccbd472012-05-07 03:13:16 +00003375 if (VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8)
Craig Topper420761a2012-04-20 07:30:17 +00003376 return std::make_pair(0U, &Mips::CPURegsRegClass);
Jack Carter10de0252012-07-02 23:35:23 +00003377 if (VT == MVT::i64 && !HasMips64)
3378 return std::make_pair(0U, &Mips::CPURegsRegClass);
Eric Christopher0ed1f762012-05-07 03:13:22 +00003379 if (VT == MVT::i64 && HasMips64)
3380 return std::make_pair(0U, &Mips::CPU64RegsRegClass);
3381 // This will generate an error message
3382 return std::make_pair(0u, static_cast<const TargetRegisterClass*>(0));
Bruno Cardoso Lopes225ca9c2008-07-05 19:05:21 +00003383 case 'f':
Owen Anderson825b72b2009-08-11 20:47:22 +00003384 if (VT == MVT::f32)
Craig Topper420761a2012-04-20 07:30:17 +00003385 return std::make_pair(0U, &Mips::FGR32RegClass);
Akira Hatanakacb9dd722012-01-04 02:45:01 +00003386 if ((VT == MVT::f64) && (!Subtarget->isSingleFloat())) {
3387 if (Subtarget->isFP64bit())
Craig Topper420761a2012-04-20 07:30:17 +00003388 return std::make_pair(0U, &Mips::FGR64RegClass);
3389 return std::make_pair(0U, &Mips::AFGR64RegClass);
Akira Hatanakacb9dd722012-01-04 02:45:01 +00003390 }
Eric Christopher1d5a3922012-05-07 06:25:10 +00003391 break;
3392 case 'c': // register suitable for indirect jump
3393 if (VT == MVT::i32)
3394 return std::make_pair((unsigned)Mips::T9, &Mips::CPURegsRegClass);
3395 assert(VT == MVT::i64 && "Unexpected type.");
3396 return std::make_pair((unsigned)Mips::T9_64, &Mips::CPU64RegsRegClass);
Eric Christopher4adbefe2012-05-07 06:25:15 +00003397 case 'l': // register suitable for indirect jump
3398 if (VT == MVT::i32)
3399 return std::make_pair((unsigned)Mips::LO, &Mips::HILORegClass);
3400 return std::make_pair((unsigned)Mips::LO64, &Mips::HILO64RegClass);
Eric Christopheraf97f732012-05-07 06:25:19 +00003401 case 'x': // register suitable for indirect jump
3402 // Fixme: Not triggering the use of both hi and low
3403 // This will generate an error message
3404 return std::make_pair(0u, static_cast<const TargetRegisterClass*>(0));
Bruno Cardoso Lopes84f47c52007-08-21 16:09:25 +00003405 }
3406 }
3407 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
3408}
3409
Eric Christopher50ab0392012-05-07 03:13:32 +00003410/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
3411/// vector. If it is invalid, don't add anything to Ops.
3412void MipsTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
3413 std::string &Constraint,
3414 std::vector<SDValue>&Ops,
3415 SelectionDAG &DAG) const {
3416 SDValue Result(0, 0);
3417
3418 // Only support length 1 constraints for now.
3419 if (Constraint.length() > 1) return;
3420
3421 char ConstraintLetter = Constraint[0];
3422 switch (ConstraintLetter) {
3423 default: break; // This will fall through to the generic implementation
3424 case 'I': // Signed 16 bit constant
3425 // If this fails, the parent routine will give an error
3426 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3427 EVT Type = Op.getValueType();
3428 int64_t Val = C->getSExtValue();
3429 if (isInt<16>(Val)) {
3430 Result = DAG.getTargetConstant(Val, Type);
3431 break;
3432 }
3433 }
3434 return;
Eric Christophere5076d42012-05-07 03:13:42 +00003435 case 'J': // integer zero
3436 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3437 EVT Type = Op.getValueType();
3438 int64_t Val = C->getZExtValue();
3439 if (Val == 0) {
3440 Result = DAG.getTargetConstant(0, Type);
3441 break;
3442 }
3443 }
3444 return;
Eric Christopherf49f8462012-05-07 05:46:29 +00003445 case 'K': // unsigned 16 bit immediate
3446 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3447 EVT Type = Op.getValueType();
3448 uint64_t Val = (uint64_t)C->getZExtValue();
3449 if (isUInt<16>(Val)) {
3450 Result = DAG.getTargetConstant(Val, Type);
3451 break;
3452 }
3453 }
3454 return;
Eric Christopher5ac47bb2012-05-07 05:46:37 +00003455 case 'L': // signed 32 bit immediate where lower 16 bits are 0
3456 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3457 EVT Type = Op.getValueType();
3458 int64_t Val = C->getSExtValue();
3459 if ((isInt<32>(Val)) && ((Val & 0xffff) == 0)){
3460 Result = DAG.getTargetConstant(Val, Type);
3461 break;
3462 }
3463 }
3464 return;
Eric Christopher60cfc792012-05-07 05:46:43 +00003465 case 'N': // immediate in the range of -65535 to -1 (inclusive)
3466 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3467 EVT Type = Op.getValueType();
3468 int64_t Val = C->getSExtValue();
3469 if ((Val >= -65535) && (Val <= -1)) {
3470 Result = DAG.getTargetConstant(Val, Type);
3471 break;
3472 }
3473 }
3474 return;
Eric Christopher1ce20342012-05-07 05:46:48 +00003475 case 'O': // signed 15 bit immediate
3476 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3477 EVT Type = Op.getValueType();
3478 int64_t Val = C->getSExtValue();
3479 if ((isInt<15>(Val))) {
3480 Result = DAG.getTargetConstant(Val, Type);
3481 break;
3482 }
3483 }
3484 return;
Eric Christopher54412a72012-05-07 06:25:02 +00003485 case 'P': // immediate in the range of 1 to 65535 (inclusive)
3486 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3487 EVT Type = Op.getValueType();
3488 int64_t Val = C->getSExtValue();
3489 if ((Val <= 65535) && (Val >= 1)) {
3490 Result = DAG.getTargetConstant(Val, Type);
3491 break;
3492 }
3493 }
3494 return;
Eric Christopher50ab0392012-05-07 03:13:32 +00003495 }
3496
3497 if (Result.getNode()) {
3498 Ops.push_back(Result);
3499 return;
3500 }
3501
3502 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
3503}
3504
Dan Gohman6520e202008-10-18 02:06:02 +00003505bool
3506MipsTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
3507 // The Mips target isn't yet aware of offsets.
3508 return false;
3509}
Evan Chengeb2f9692009-10-27 19:56:55 +00003510
Akira Hatanakae193b322012-06-13 19:33:32 +00003511EVT MipsTargetLowering::getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
3512 unsigned SrcAlign, bool IsZeroVal,
3513 bool MemcpyStrSrc,
3514 MachineFunction &MF) const {
3515 if (Subtarget->hasMips64())
3516 return MVT::i64;
3517
3518 return MVT::i32;
3519}
3520
Evan Chenga1eaa3c2009-10-28 01:43:28 +00003521bool MipsTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3522 if (VT != MVT::f32 && VT != MVT::f64)
3523 return false;
Bruno Cardoso Lopes6b902822011-01-18 19:41:41 +00003524 if (Imm.isNegZero())
3525 return false;
Evan Chengeb2f9692009-10-27 19:56:55 +00003526 return Imm.isZero();
3527}
Akira Hatanaka6c2cf8b2012-02-03 04:33:00 +00003528
3529unsigned MipsTargetLowering::getJumpTableEncoding() const {
3530 if (IsN64)
3531 return MachineJumpTableInfo::EK_GPRel64BlockAddress;
Jia Liubb481f82012-02-28 07:46:26 +00003532
Akira Hatanaka6c2cf8b2012-02-03 04:33:00 +00003533 return TargetLowering::getJumpTableEncoding();
3534}