blob: debf2f1b85c1be6fa4c5efda926b9624b54c506a [file] [log] [blame]
Jia Liuc5707112012-02-17 08:55:11 +00001//===-- DelaySlotFiller.cpp - Mips Delay Slot Filler ----------------------===//
Bruno Cardoso Lopes9684a692007-08-18 01:50:47 +00002//
3// The LLVM Compiler Infrastructure
4//
Chris Lattner4ee451d2007-12-29 20:36:04 +00005// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
Bruno Cardoso Lopes9684a692007-08-18 01:50:47 +00007//
Akira Hatanaka4552c9a2011-04-15 21:51:11 +00008//===----------------------------------------------------------------------===//
Bruno Cardoso Lopes9684a692007-08-18 01:50:47 +00009//
Akira Hatanakaa3defb02011-09-29 23:52:13 +000010// Simple pass to fills delay slots with useful instructions.
Bruno Cardoso Lopes9684a692007-08-18 01:50:47 +000011//
Akira Hatanaka4552c9a2011-04-15 21:51:11 +000012//===----------------------------------------------------------------------===//
Bruno Cardoso Lopes9684a692007-08-18 01:50:47 +000013
14#define DEBUG_TYPE "delay-slot-filler"
15
16#include "Mips.h"
17#include "MipsTargetMachine.h"
18#include "llvm/CodeGen/MachineFunctionPass.h"
19#include "llvm/CodeGen/MachineInstrBuilder.h"
Akira Hatanakaa3defb02011-09-29 23:52:13 +000020#include "llvm/Support/CommandLine.h"
21#include "llvm/Target/TargetMachine.h"
Bruno Cardoso Lopes9684a692007-08-18 01:50:47 +000022#include "llvm/Target/TargetInstrInfo.h"
Akira Hatanakaa3defb02011-09-29 23:52:13 +000023#include "llvm/Target/TargetRegisterInfo.h"
24#include "llvm/ADT/SmallSet.h"
Bruno Cardoso Lopes9684a692007-08-18 01:50:47 +000025#include "llvm/ADT/Statistic.h"
26
27using namespace llvm;
28
29STATISTIC(FilledSlots, "Number of delay slots filled");
Akira Hatanaka98f4d4d2011-10-05 01:19:13 +000030STATISTIC(UsefulSlots, "Number of delay slots filled with instructions that"
Akira Hatanaka176965f2011-10-05 02:22:49 +000031 " are not NOP.");
Bruno Cardoso Lopes9684a692007-08-18 01:50:47 +000032
Akira Hatanakaa3defb02011-09-29 23:52:13 +000033static cl::opt<bool> EnableDelaySlotFiller(
34 "enable-mips-delay-filler",
35 cl::init(false),
Akira Hatanaka6585b512011-10-05 01:06:57 +000036 cl::desc("Fill the Mips delay slots useful instructions."),
Akira Hatanakaa3defb02011-09-29 23:52:13 +000037 cl::Hidden);
38
Bruno Cardoso Lopes9684a692007-08-18 01:50:47 +000039namespace {
40 struct Filler : public MachineFunctionPass {
41
42 TargetMachine &TM;
43 const TargetInstrInfo *TII;
Akira Hatanaka53120e02011-10-05 01:30:09 +000044 MachineBasicBlock::iterator LastFiller;
Bruno Cardoso Lopes9684a692007-08-18 01:50:47 +000045
46 static char ID;
Bruno Cardoso Lopes90c59542010-12-09 17:31:11 +000047 Filler(TargetMachine &tm)
Owen Anderson90c579d2010-08-06 18:33:48 +000048 : MachineFunctionPass(ID), TM(tm), TII(tm.getInstrInfo()) { }
Bruno Cardoso Lopes9684a692007-08-18 01:50:47 +000049
50 virtual const char *getPassName() const {
51 return "Mips Delay Slot Filler";
52 }
53
54 bool runOnMachineBasicBlock(MachineBasicBlock &MBB);
55 bool runOnMachineFunction(MachineFunction &F) {
56 bool Changed = false;
57 for (MachineFunction::iterator FI = F.begin(), FE = F.end();
58 FI != FE; ++FI)
59 Changed |= runOnMachineBasicBlock(*FI);
60 return Changed;
61 }
62
Akira Hatanakaa3defb02011-09-29 23:52:13 +000063 bool isDelayFiller(MachineBasicBlock &MBB,
64 MachineBasicBlock::iterator candidate);
65
66 void insertCallUses(MachineBasicBlock::iterator MI,
67 SmallSet<unsigned, 32>& RegDefs,
68 SmallSet<unsigned, 32>& RegUses);
69
70 void insertDefsUses(MachineBasicBlock::iterator MI,
71 SmallSet<unsigned, 32>& RegDefs,
72 SmallSet<unsigned, 32>& RegUses);
73
74 bool IsRegInSet(SmallSet<unsigned, 32>& RegSet,
75 unsigned Reg);
76
77 bool delayHasHazard(MachineBasicBlock::iterator candidate,
78 bool &sawLoad, bool &sawStore,
79 SmallSet<unsigned, 32> &RegDefs,
80 SmallSet<unsigned, 32> &RegUses);
81
Akira Hatanaka6f818ab2011-10-05 01:23:39 +000082 bool
83 findDelayInstr(MachineBasicBlock &MBB, MachineBasicBlock::iterator slot,
84 MachineBasicBlock::iterator &Filler);
Akira Hatanakaa3defb02011-09-29 23:52:13 +000085
86
Bruno Cardoso Lopes9684a692007-08-18 01:50:47 +000087 };
88 char Filler::ID = 0;
89} // end of anonymous namespace
90
91/// runOnMachineBasicBlock - Fill in delay slots for the given basic block.
Akira Hatanakaa3defb02011-09-29 23:52:13 +000092/// We assume there is only one delay slot per delayed instruction.
Bruno Cardoso Lopes9684a692007-08-18 01:50:47 +000093bool Filler::
Akira Hatanakaa3defb02011-09-29 23:52:13 +000094runOnMachineBasicBlock(MachineBasicBlock &MBB) {
Bruno Cardoso Lopes9684a692007-08-18 01:50:47 +000095 bool Changed = false;
Akira Hatanaka53120e02011-10-05 01:30:09 +000096 LastFiller = MBB.end();
97
Akira Hatanakaa3defb02011-09-29 23:52:13 +000098 for (MachineBasicBlock::iterator I = MBB.begin(); I != MBB.end(); ++I)
Evan Cheng5a96b3d2011-12-07 07:15:52 +000099 if (I->hasDelaySlot()) {
Bruno Cardoso Lopes9684a692007-08-18 01:50:47 +0000100 ++FilledSlots;
101 Changed = true;
Bruno Cardoso Lopes90c59542010-12-09 17:31:11 +0000102
Akira Hatanaka6f818ab2011-10-05 01:23:39 +0000103 MachineBasicBlock::iterator D;
104
105 if (EnableDelaySlotFiller && findDelayInstr(MBB, I, D)) {
106 MBB.splice(llvm::next(I), &MBB, D);
107 ++UsefulSlots;
Jia Liubb481f82012-02-28 07:46:26 +0000108 } else
Akira Hatanaka6f818ab2011-10-05 01:23:39 +0000109 BuildMI(MBB, llvm::next(I), I->getDebugLoc(), TII->get(Mips::NOP));
110
Akira Hatanaka53120e02011-10-05 01:30:09 +0000111 // Record the filler instruction that filled the delay slot.
112 // The instruction after it will be visited in the next iteration.
113 LastFiller = ++I;
Akira Hatanakaa3defb02011-09-29 23:52:13 +0000114 }
Bruno Cardoso Lopes9684a692007-08-18 01:50:47 +0000115 return Changed;
Akira Hatanakaa3defb02011-09-29 23:52:13 +0000116
Bruno Cardoso Lopes9684a692007-08-18 01:50:47 +0000117}
118
119/// createMipsDelaySlotFillerPass - Returns a pass that fills in delay
120/// slots in Mips MachineFunctions
121FunctionPass *llvm::createMipsDelaySlotFillerPass(MipsTargetMachine &tm) {
122 return new Filler(tm);
123}
124
Akira Hatanaka6f818ab2011-10-05 01:23:39 +0000125bool Filler::findDelayInstr(MachineBasicBlock &MBB,
126 MachineBasicBlock::iterator slot,
127 MachineBasicBlock::iterator &Filler) {
Akira Hatanakaa3defb02011-09-29 23:52:13 +0000128 SmallSet<unsigned, 32> RegDefs;
129 SmallSet<unsigned, 32> RegUses;
Akira Hatanakaa3defb02011-09-29 23:52:13 +0000130
Akira Hatanaka0f0c59a02011-10-05 02:04:17 +0000131 insertDefsUses(slot, RegDefs, RegUses);
Akira Hatanakaa3defb02011-09-29 23:52:13 +0000132
Akira Hatanaka7d8e04d2011-10-05 01:57:46 +0000133 bool sawLoad = false;
134 bool sawStore = false;
Akira Hatanakaa3defb02011-09-29 23:52:13 +0000135
Akira Hatanaka7d8e04d2011-10-05 01:57:46 +0000136 for (MachineBasicBlock::reverse_iterator I(slot); I != MBB.rend(); ++I) {
Akira Hatanakaa3defb02011-09-29 23:52:13 +0000137 // skip debug value
138 if (I->isDebugValue())
139 continue;
140
Akira Hatanaka7d8e04d2011-10-05 01:57:46 +0000141 // Convert to forward iterator.
NAKAMURA Takumi4cbc5a12011-10-05 10:11:02 +0000142 MachineBasicBlock::iterator FI(llvm::next(I).base());
Akira Hatanaka7d8e04d2011-10-05 01:57:46 +0000143
Akira Hatanakaa3defb02011-09-29 23:52:13 +0000144 if (I->hasUnmodeledSideEffects()
145 || I->isInlineAsm()
146 || I->isLabel()
Akira Hatanaka7d8e04d2011-10-05 01:57:46 +0000147 || FI == LastFiller
Evan Cheng5a96b3d2011-12-07 07:15:52 +0000148 || I->isPseudo()
Akira Hatanakaa3defb02011-09-29 23:52:13 +0000149 //
150 // Should not allow:
151 // ERET, DERET or WAIT, PAUSE. Need to add these to instruction
152 // list. TBD.
153 )
154 break;
155
Akira Hatanaka7d8e04d2011-10-05 01:57:46 +0000156 if (delayHasHazard(FI, sawLoad, sawStore, RegDefs, RegUses)) {
157 insertDefsUses(FI, RegDefs, RegUses);
Akira Hatanakaa3defb02011-09-29 23:52:13 +0000158 continue;
159 }
160
Akira Hatanaka7d8e04d2011-10-05 01:57:46 +0000161 Filler = FI;
Akira Hatanaka6f818ab2011-10-05 01:23:39 +0000162 return true;
Akira Hatanakaa3defb02011-09-29 23:52:13 +0000163 }
Akira Hatanaka6f818ab2011-10-05 01:23:39 +0000164
165 return false;
Akira Hatanakaa3defb02011-09-29 23:52:13 +0000166}
167
168bool Filler::delayHasHazard(MachineBasicBlock::iterator candidate,
Akira Hatanaka82099682011-12-19 19:52:25 +0000169 bool &sawLoad, bool &sawStore,
Akira Hatanakaa3defb02011-09-29 23:52:13 +0000170 SmallSet<unsigned, 32> &RegDefs,
171 SmallSet<unsigned, 32> &RegUses) {
172 if (candidate->isImplicitDef() || candidate->isKill())
173 return true;
174
Akira Hatanakacfc3fb52011-10-05 01:09:37 +0000175 // Loads or stores cannot be moved past a store to the delay slot
Jia Liubb481f82012-02-28 07:46:26 +0000176 // and stores cannot be moved past a load.
Evan Cheng5a96b3d2011-12-07 07:15:52 +0000177 if (candidate->mayLoad()) {
Akira Hatanakaa3defb02011-09-29 23:52:13 +0000178 if (sawStore)
179 return true;
Akira Hatanakacfc3fb52011-10-05 01:09:37 +0000180 sawLoad = true;
Akira Hatanakaa3defb02011-09-29 23:52:13 +0000181 }
182
Evan Cheng5a96b3d2011-12-07 07:15:52 +0000183 if (candidate->mayStore()) {
Akira Hatanakaa3defb02011-09-29 23:52:13 +0000184 if (sawStore)
185 return true;
186 sawStore = true;
187 if (sawLoad)
188 return true;
189 }
190
Evan Cheng5a96b3d2011-12-07 07:15:52 +0000191 assert((!candidate->isCall() && !candidate->isReturn()) &&
Akira Hatanaka42be2802011-10-05 18:17:49 +0000192 "Cannot put calls or returns in delay slot.");
Akira Hatanaka0c419a72011-10-05 02:18:58 +0000193
Akira Hatanakaa3defb02011-09-29 23:52:13 +0000194 for (unsigned i = 0, e = candidate->getNumOperands(); i!= e; ++i) {
195 const MachineOperand &MO = candidate->getOperand(i);
Akira Hatanaka0c419a72011-10-05 02:18:58 +0000196 unsigned Reg;
Akira Hatanakaa3defb02011-09-29 23:52:13 +0000197
Akira Hatanaka0c419a72011-10-05 02:18:58 +0000198 if (!MO.isReg() || !(Reg = MO.getReg()))
199 continue; // skip
Akira Hatanakaa3defb02011-09-29 23:52:13 +0000200
201 if (MO.isDef()) {
202 // check whether Reg is defined or used before delay slot.
203 if (IsRegInSet(RegDefs, Reg) || IsRegInSet(RegUses, Reg))
204 return true;
205 }
206 if (MO.isUse()) {
207 // check whether Reg is defined before delay slot.
208 if (IsRegInSet(RegDefs, Reg))
209 return true;
210 }
211 }
212 return false;
213}
214
Akira Hatanakaa3defb02011-09-29 23:52:13 +0000215// Insert Defs and Uses of MI into the sets RegDefs and RegUses.
216void Filler::insertDefsUses(MachineBasicBlock::iterator MI,
217 SmallSet<unsigned, 32>& RegDefs,
218 SmallSet<unsigned, 32>& RegUses) {
Akira Hatanaka0c419a72011-10-05 02:18:58 +0000219 // If MI is a call or return, just examine the explicit non-variadic operands.
Akira Hatanaka6e4e6482011-10-05 02:21:58 +0000220 MCInstrDesc MCID = MI->getDesc();
Evan Cheng5a96b3d2011-12-07 07:15:52 +0000221 unsigned e = MI->isCall() || MI->isReturn() ? MCID.getNumOperands() :
222 MI->getNumOperands();
Jia Liubb481f82012-02-28 07:46:26 +0000223
224 // Add RA to RegDefs to prevent users of RA from going into delay slot.
Evan Cheng5a96b3d2011-12-07 07:15:52 +0000225 if (MI->isCall())
Akira Hatanaka2f523382011-10-05 18:11:44 +0000226 RegDefs.insert(Mips::RA);
Akira Hatanaka0f0c59a02011-10-05 02:04:17 +0000227
228 for (unsigned i = 0; i != e; ++i) {
Akira Hatanakaa3defb02011-09-29 23:52:13 +0000229 const MachineOperand &MO = MI->getOperand(i);
Akira Hatanaka0f0c59a02011-10-05 02:04:17 +0000230 unsigned Reg;
231
232 if (!MO.isReg() || !(Reg = MO.getReg()))
Akira Hatanakaa3defb02011-09-29 23:52:13 +0000233 continue;
234
Akira Hatanakaa3defb02011-09-29 23:52:13 +0000235 if (MO.isDef())
236 RegDefs.insert(Reg);
Akira Hatanaka0f0c59a02011-10-05 02:04:17 +0000237 else if (MO.isUse())
Akira Hatanakaa3defb02011-09-29 23:52:13 +0000238 RegUses.insert(Reg);
239 }
240}
241
242//returns true if the Reg or its alias is in the RegSet.
243bool Filler::IsRegInSet(SmallSet<unsigned, 32>& RegSet, unsigned Reg) {
244 if (RegSet.count(Reg))
245 return true;
246 // check Aliased Registers
Craig Toppere4fd9072012-03-04 10:43:23 +0000247 for (const uint16_t *Alias = TM.getRegisterInfo()->getAliasSet(Reg);
Akira Hatanakaa3defb02011-09-29 23:52:13 +0000248 *Alias; ++Alias)
249 if (RegSet.count(*Alias))
250 return true;
251
252 return false;
253}