| Bob Wilson | e60fee0 | 2009-06-22 23:27:02 +0000 | [diff] [blame^] | 1 | ; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t |
| 2 | ; RUN: grep {vpaddl\\.s8} %t | count 2 |
| 3 | ; RUN: grep {vpaddl\\.s16} %t | count 2 |
| 4 | ; RUN: grep {vpaddl\\.s32} %t | count 2 |
| 5 | ; RUN: grep {vpaddl\\.u8} %t | count 2 |
| 6 | ; RUN: grep {vpaddl\\.u16} %t | count 2 |
| 7 | ; RUN: grep {vpaddl\\.u32} %t | count 2 |
| 8 | |
| 9 | define <4 x i16> @vpaddls8(<8 x i8>* %A) nounwind { |
| 10 | %tmp1 = load <8 x i8>* %A |
| 11 | %tmp2 = call <4 x i16> @llvm.arm.neon.vpaddls.v4i16.v8i8(<8 x i8> %tmp1) |
| 12 | ret <4 x i16> %tmp2 |
| 13 | } |
| 14 | |
| 15 | define <2 x i32> @vpaddls16(<4 x i16>* %A) nounwind { |
| 16 | %tmp1 = load <4 x i16>* %A |
| 17 | %tmp2 = call <2 x i32> @llvm.arm.neon.vpaddls.v2i32.v4i16(<4 x i16> %tmp1) |
| 18 | ret <2 x i32> %tmp2 |
| 19 | } |
| 20 | |
| 21 | define <1 x i64> @vpaddls32(<2 x i32>* %A) nounwind { |
| 22 | %tmp1 = load <2 x i32>* %A |
| 23 | %tmp2 = call <1 x i64> @llvm.arm.neon.vpaddls.v1i64.v2i32(<2 x i32> %tmp1) |
| 24 | ret <1 x i64> %tmp2 |
| 25 | } |
| 26 | |
| 27 | define <4 x i16> @vpaddlu8(<8 x i8>* %A) nounwind { |
| 28 | %tmp1 = load <8 x i8>* %A |
| 29 | %tmp2 = call <4 x i16> @llvm.arm.neon.vpaddlu.v4i16.v8i8(<8 x i8> %tmp1) |
| 30 | ret <4 x i16> %tmp2 |
| 31 | } |
| 32 | |
| 33 | define <2 x i32> @vpaddlu16(<4 x i16>* %A) nounwind { |
| 34 | %tmp1 = load <4 x i16>* %A |
| 35 | %tmp2 = call <2 x i32> @llvm.arm.neon.vpaddlu.v2i32.v4i16(<4 x i16> %tmp1) |
| 36 | ret <2 x i32> %tmp2 |
| 37 | } |
| 38 | |
| 39 | define <1 x i64> @vpaddlu32(<2 x i32>* %A) nounwind { |
| 40 | %tmp1 = load <2 x i32>* %A |
| 41 | %tmp2 = call <1 x i64> @llvm.arm.neon.vpaddlu.v1i64.v2i32(<2 x i32> %tmp1) |
| 42 | ret <1 x i64> %tmp2 |
| 43 | } |
| 44 | |
| 45 | define <8 x i16> @vpaddlQs8(<16 x i8>* %A) nounwind { |
| 46 | %tmp1 = load <16 x i8>* %A |
| 47 | %tmp2 = call <8 x i16> @llvm.arm.neon.vpaddls.v8i16.v16i8(<16 x i8> %tmp1) |
| 48 | ret <8 x i16> %tmp2 |
| 49 | } |
| 50 | |
| 51 | define <4 x i32> @vpaddlQs16(<8 x i16>* %A) nounwind { |
| 52 | %tmp1 = load <8 x i16>* %A |
| 53 | %tmp2 = call <4 x i32> @llvm.arm.neon.vpaddls.v4i32.v8i16(<8 x i16> %tmp1) |
| 54 | ret <4 x i32> %tmp2 |
| 55 | } |
| 56 | |
| 57 | define <2 x i64> @vpaddlQs32(<4 x i32>* %A) nounwind { |
| 58 | %tmp1 = load <4 x i32>* %A |
| 59 | %tmp2 = call <2 x i64> @llvm.arm.neon.vpaddls.v2i64.v4i32(<4 x i32> %tmp1) |
| 60 | ret <2 x i64> %tmp2 |
| 61 | } |
| 62 | |
| 63 | define <8 x i16> @vpaddlQu8(<16 x i8>* %A) nounwind { |
| 64 | %tmp1 = load <16 x i8>* %A |
| 65 | %tmp2 = call <8 x i16> @llvm.arm.neon.vpaddlu.v8i16.v16i8(<16 x i8> %tmp1) |
| 66 | ret <8 x i16> %tmp2 |
| 67 | } |
| 68 | |
| 69 | define <4 x i32> @vpaddlQu16(<8 x i16>* %A) nounwind { |
| 70 | %tmp1 = load <8 x i16>* %A |
| 71 | %tmp2 = call <4 x i32> @llvm.arm.neon.vpaddlu.v4i32.v8i16(<8 x i16> %tmp1) |
| 72 | ret <4 x i32> %tmp2 |
| 73 | } |
| 74 | |
| 75 | define <2 x i64> @vpaddlQu32(<4 x i32>* %A) nounwind { |
| 76 | %tmp1 = load <4 x i32>* %A |
| 77 | %tmp2 = call <2 x i64> @llvm.arm.neon.vpaddlu.v2i64.v4i32(<4 x i32> %tmp1) |
| 78 | ret <2 x i64> %tmp2 |
| 79 | } |
| 80 | |
| 81 | declare <4 x i16> @llvm.arm.neon.vpaddls.v4i16.v8i8(<8 x i8>) nounwind readnone |
| 82 | declare <2 x i32> @llvm.arm.neon.vpaddls.v2i32.v4i16(<4 x i16>) nounwind readnone |
| 83 | declare <1 x i64> @llvm.arm.neon.vpaddls.v1i64.v2i32(<2 x i32>) nounwind readnone |
| 84 | |
| 85 | declare <4 x i16> @llvm.arm.neon.vpaddlu.v4i16.v8i8(<8 x i8>) nounwind readnone |
| 86 | declare <2 x i32> @llvm.arm.neon.vpaddlu.v2i32.v4i16(<4 x i16>) nounwind readnone |
| 87 | declare <1 x i64> @llvm.arm.neon.vpaddlu.v1i64.v2i32(<2 x i32>) nounwind readnone |
| 88 | |
| 89 | declare <8 x i16> @llvm.arm.neon.vpaddls.v8i16.v16i8(<16 x i8>) nounwind readnone |
| 90 | declare <4 x i32> @llvm.arm.neon.vpaddls.v4i32.v8i16(<8 x i16>) nounwind readnone |
| 91 | declare <2 x i64> @llvm.arm.neon.vpaddls.v2i64.v4i32(<4 x i32>) nounwind readnone |
| 92 | |
| 93 | declare <8 x i16> @llvm.arm.neon.vpaddlu.v8i16.v16i8(<16 x i8>) nounwind readnone |
| 94 | declare <4 x i32> @llvm.arm.neon.vpaddlu.v4i32.v8i16(<8 x i16>) nounwind readnone |
| 95 | declare <2 x i64> @llvm.arm.neon.vpaddlu.v2i64.v4i32(<4 x i32>) nounwind readnone |