blob: 10529f61b56f2912d742300c12bc75c182aa8e49 [file] [log] [blame]
Bob Wilsone60fee02009-06-22 23:27:02 +00001; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t
2; RUN: grep {vrsqrte\\.u32} %t | count 2
3; RUN: grep {vrsqrte\\.f32} %t | count 2
4
5define <2 x i32> @vrsqrtei32(<2 x i32>* %A) nounwind {
6 %tmp1 = load <2 x i32>* %A
7 %tmp2 = call <2 x i32> @llvm.arm.neon.vrsqrte.v2i32(<2 x i32> %tmp1)
8 ret <2 x i32> %tmp2
9}
10
11define <4 x i32> @vrsqrteQi32(<4 x i32>* %A) nounwind {
12 %tmp1 = load <4 x i32>* %A
13 %tmp2 = call <4 x i32> @llvm.arm.neon.vrsqrte.v4i32(<4 x i32> %tmp1)
14 ret <4 x i32> %tmp2
15}
16
17define <2 x float> @vrsqrtef32(<2 x float>* %A) nounwind {
18 %tmp1 = load <2 x float>* %A
19 %tmp2 = call <2 x float> @llvm.arm.neon.vrsqrtef.v2f32(<2 x float> %tmp1)
20 ret <2 x float> %tmp2
21}
22
23define <4 x float> @vrsqrteQf32(<4 x float>* %A) nounwind {
24 %tmp1 = load <4 x float>* %A
25 %tmp2 = call <4 x float> @llvm.arm.neon.vrsqrtef.v4f32(<4 x float> %tmp1)
26 ret <4 x float> %tmp2
27}
28
29declare <2 x i32> @llvm.arm.neon.vrsqrte.v2i32(<2 x i32>) nounwind readnone
30declare <4 x i32> @llvm.arm.neon.vrsqrte.v4i32(<4 x i32>) nounwind readnone
31
32declare <2 x float> @llvm.arm.neon.vrsqrtef.v2f32(<2 x float>) nounwind readnone
33declare <4 x float> @llvm.arm.neon.vrsqrtef.v4f32(<4 x float>) nounwind readnone