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gerrit-public.fairphone.software / fp2-dev / platform / external / llvm / e721f5c8d3ea2cc2cc8c3c308ce8bdd8a3fc3b32 / . / lib / Target / ARM / ARMISelLowering.h
blob: 980fb404887e047f286974dda08629d835d290d1 [file] [log] [blame]
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]1//===-- ARMISelLowering.h - ARM DAG Lowering Interface ----------*- C++ -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
Chris Lattner4ee451d2007-12-29 20:36:04 +0000[diff] [blame]5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the interfaces that ARM uses to lower LLVM code into a
11// selection DAG.
12//
13//===----------------------------------------------------------------------===//
14
15#ifndef ARMISELLOWERING_H
16#define ARMISELLOWERING_H
17
Rafael Espindolaf1ba1ca2007-11-05 23:12:20 +0000[diff] [blame]18#include "ARMSubtarget.h"
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]19#include "llvm/Target/TargetLowering.h"
Evan Cheng31446872010-07-23 22:39:59 +0000[diff] [blame]20#include "llvm/Target/TargetRegisterInfo.h"
Eric Christopherab695882010-07-21 22:26:11 +0000[diff] [blame]21#include "llvm/CodeGen/FastISel.h"
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]22#include "llvm/CodeGen/SelectionDAG.h"
Bob Wilson1f595bb2009-04-17 19:07:39 +0000[diff] [blame]23#include "llvm/CodeGen/CallingConvLower.h"
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]24#include <vector>
25
26namespace llvm {
27 class ARMConstantPoolValue;
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]28
29 namespace ARMISD {
30 // ARM Specific DAG Nodes
31 enum NodeType {
Jim Grosbach6aa71972009-05-13 22:32:43 +0000[diff] [blame]32 // Start the numbering where the builtin ops and target ops leave off.
Dan Gohman0ba2bcf2008-09-23 18:42:32 +0000[diff] [blame]33 FIRST_NUMBER = ISD::BUILTIN_OP_END,
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]34
35 Wrapper, // Wrapper - A wrapper node for TargetConstantPool,
36 // TargetExternalSymbol, and TargetGlobalAddress.
Evan Cheng53519f02011-01-21 18:55:51 +0000[diff] [blame]37 WrapperDYN, // WrapperDYN - A wrapper node for TargetGlobalAddress in
38 // DYN mode.
Evan Cheng5de5d4b2011-01-17 08:03:18 +0000[diff] [blame]39 WrapperPIC, // WrapperPIC - A wrapper node for TargetGlobalAddress in
40 // PIC mode.
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]41 WrapperJT, // WrapperJT - A wrapper node for TargetJumpTable
Jim Grosbach6aa71972009-05-13 22:32:43 +0000[diff] [blame]42
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]43 CALL, // Function call.
Evan Cheng277f0742007-06-19 21:05:09 +0000[diff] [blame]44 CALL_PRED, // Function call that's predicable.
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]45 CALL_NOLINK, // Function call with branch not branch-and-link.
46 tCALL, // Thumb function call.
47 BRCOND, // Conditional branch.
48 BR_JT, // Jumptable branch.
Evan Cheng5657c012009-07-29 02:18:14 +0000[diff] [blame]49 BR2_JT, // Jumptable branch (2 level - jumptable entry is a jump).
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]50 RET_FLAG, // Return with a flag operand.
51
52 PIC_ADD, // Add with a PC operand and a PIC label.
53
54 CMP, // ARM compare instructions.
David Goodwinc0309b42009-06-29 15:33:01 +0000[diff] [blame]55 CMPZ, // ARM compare that sets only Z flag.
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]56 CMPFP, // ARM VFP compare instruction, sets FPSCR.
57 CMPFPw0, // ARM VFP compare against zero instruction, sets FPSCR.
58 FMSTAT, // ARM fmstat instruction.
59 CMOV, // ARM conditional move instructions.
Jim Grosbach6aa71972009-05-13 22:32:43 +0000[diff] [blame]60
Evan Cheng218977b2010-07-13 19:27:42 +0000[diff] [blame]61 BCC_i64,
62
Jim Grosbach3482c802010-01-18 19:58:49 +0000[diff] [blame]63 RBIT, // ARM bitreverse instruction
64
Bob Wilson76a312b2010-03-19 22:51:32 +0000[diff] [blame]65 FTOSI, // FP to sint within a FP register.
66 FTOUI, // FP to uint within a FP register.
67 SITOF, // sint to FP within a FP register.
68 UITOF, // uint to FP within a FP register.
69
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]70 SRL_FLAG, // V,Flag = srl_flag X -> srl X, 1 + save carry out.
71 SRA_FLAG, // V,Flag = sra_flag X -> sra X, 1 + save carry out.
72 RRX, // V = RRX X, Flag -> srl X, 1 + shift in carry flag.
Jim Grosbach6aa71972009-05-13 22:32:43 +0000[diff] [blame]73
Jim Grosbache5165492009-11-09 00:11:35 +0000[diff] [blame]74 VMOVRRD, // double to two gprs.
75 VMOVDRR, // Two gprs to double.
Lauro Ramos Venancio64f4fa52007-04-27 13:54:47 +0000[diff] [blame]76
Jim Grosbache4ad3872010-10-19 23:27:08 +0000[diff] [blame]77 EH_SJLJ_SETJMP, // SjLj exception handling setjmp.
78 EH_SJLJ_LONGJMP, // SjLj exception handling longjmp.
79 EH_SJLJ_DISPATCHSETUP, // SjLj exception handling dispatch setup.
Jim Grosbach0e0da732009-05-12 23:59:14 +0000[diff] [blame]80
Dale Johannesen51e28e62010-06-03 21:09:53 +0000[diff] [blame]81 TC_RETURN, // Tail call return pseudo.
82
Bob Wilson5bafff32009-06-22 23:27:02 +0000[diff] [blame]83 THREAD_POINTER,
84
Evan Cheng86198642009-08-07 00:34:42 +0000[diff] [blame]85 DYN_ALLOC, // Dynamic allocation on the stack.
86
Bob Wilsonf74a4292010-10-30 00:54:37 +0000[diff] [blame]87 MEMBARRIER, // Memory barrier (DMB)
88 MEMBARRIER_MCR, // Memory barrier (MCR)
Evan Chengdfed19f2010-11-03 06:34:55 +0000[diff] [blame]89
90 PRELOAD, // Preload
Andrew Trick5adfba22011-04-23 03:24:11 +0000[diff] [blame]91
Bob Wilson5bafff32009-06-22 23:27:02 +0000[diff] [blame]92 VCEQ, // Vector compare equal.
Owen Andersonc24cb352010-11-08 23:21:22 +0000[diff] [blame]93 VCEQZ, // Vector compare equal to zero.
Bob Wilson5bafff32009-06-22 23:27:02 +0000[diff] [blame]94 VCGE, // Vector compare greater than or equal.
Owen Andersonc24cb352010-11-08 23:21:22 +0000[diff] [blame]95 VCGEZ, // Vector compare greater than or equal to zero.
96 VCLEZ, // Vector compare less than or equal to zero.
Bob Wilson5bafff32009-06-22 23:27:02 +0000[diff] [blame]97 VCGEU, // Vector compare unsigned greater than or equal.
98 VCGT, // Vector compare greater than.
Owen Andersonc24cb352010-11-08 23:21:22 +0000[diff] [blame]99 VCGTZ, // Vector compare greater than zero.
100 VCLTZ, // Vector compare less than zero.
Bob Wilson5bafff32009-06-22 23:27:02 +0000[diff] [blame]101 VCGTU, // Vector compare unsigned greater than.
102 VTST, // Vector test bits.
103
104 // Vector shift by immediate:
105 VSHL, // ...left
106 VSHRs, // ...right (signed)
107 VSHRu, // ...right (unsigned)
108 VSHLLs, // ...left long (signed)
109 VSHLLu, // ...left long (unsigned)
110 VSHLLi, // ...left long (with maximum shift count)
111 VSHRN, // ...right narrow
112
113 // Vector rounding shift by immediate:
114 VRSHRs, // ...right (signed)
115 VRSHRu, // ...right (unsigned)
116 VRSHRN, // ...right narrow
117
118 // Vector saturating shift by immediate:
119 VQSHLs, // ...left (signed)
120 VQSHLu, // ...left (unsigned)
121 VQSHLsu, // ...left (signed to unsigned)
122 VQSHRNs, // ...right narrow (signed)
123 VQSHRNu, // ...right narrow (unsigned)
124 VQSHRNsu, // ...right narrow (signed to unsigned)
125
126 // Vector saturating rounding shift by immediate:
127 VQRSHRNs, // ...right narrow (signed)
128 VQRSHRNu, // ...right narrow (unsigned)
129 VQRSHRNsu, // ...right narrow (signed to unsigned)
130
131 // Vector shift and insert:
132 VSLI, // ...left
133 VSRI, // ...right
134
135 // Vector get lane (VMOV scalar to ARM core register)
136 // (These are used for 8- and 16-bit element types only.)
137 VGETLANEu, // zero-extend vector extract element
138 VGETLANEs, // sign-extend vector extract element
139
Bob Wilson7e3f0d22010-07-14 06:31:50 +0000[diff] [blame]140 // Vector move immediate and move negated immediate:
Bob Wilsoncba270d2010-07-13 21:16:48 +0000[diff] [blame]141 VMOVIMM,
Bob Wilson7e3f0d22010-07-14 06:31:50 +0000[diff] [blame]142 VMVNIMM,
143
144 // Vector duplicate:
Bob Wilsonc1d287b2009-08-14 05:13:08 +0000[diff] [blame]145 VDUP,
Bob Wilson0ce37102009-08-14 05:08:32 +0000[diff] [blame]146 VDUPLANE,
Bob Wilsona599bff2009-08-04 00:36:16 +0000[diff] [blame]147
Bob Wilsond8e17572009-08-12 22:31:50 +0000[diff] [blame]148 // Vector shuffles:
Bob Wilsonde95c1b82009-08-19 17:03:43 +0000[diff] [blame]149 VEXT, // extract
Bob Wilsond8e17572009-08-12 22:31:50 +0000[diff] [blame]150 VREV64, // reverse elements within 64-bit doublewords
151 VREV32, // reverse elements within 32-bit words
Anton Korobeynikov1c8e5812009-08-21 12:41:24 +0000[diff] [blame]152 VREV16, // reverse elements within 16-bit halfwords
Bob Wilsonc692cb72009-08-21 20:54:19 +0000[diff] [blame]153 VZIP, // zip (interleave)
154 VUZP, // unzip (deinterleave)
Bob Wilson9f6c4c12010-02-18 06:05:53 +0000[diff] [blame]155 VTRN, // transpose
Bill Wendling69a05a72011-03-14 23:02:38 +0000[diff] [blame]156 VTBL1, // 1-register shuffle with mask
157 VTBL2, // 2-register shuffle with mask
Bob Wilson9f6c4c12010-02-18 06:05:53 +0000[diff] [blame]158
Bob Wilsond0b69cf2010-09-01 23:50:19 +0000[diff] [blame]159 // Vector multiply long:
160 VMULLs, // ...signed
161 VMULLu, // ...unsigned
162
Bob Wilson40cbe7d2010-06-04 00:04:02 +0000[diff] [blame]163 // Operands of the standard BUILD_VECTOR node are not legalized, which
164 // is fine if BUILD_VECTORs are always lowered to shuffles or other
165 // operations, but for ARM some BUILD_VECTORs are legal as-is and their
166 // operands need to be legalized. Define an ARM-specific version of
167 // BUILD_VECTOR for this purpose.
168 BUILD_VECTOR,
169
Bob Wilson9f6c4c12010-02-18 06:05:53 +0000[diff] [blame]170 // Floating-point max and min:
171 FMAX,
Jim Grosbach469bbdb2010-07-16 23:05:05 +0000[diff] [blame]172 FMIN,
173
174 // Bit-field insert
Owen Andersond9668172010-11-03 22:44:51 +0000[diff] [blame]175 BFI,
Andrew Trick5adfba22011-04-23 03:24:11 +0000[diff] [blame]176
Owen Andersond9668172010-11-03 22:44:51 +0000[diff] [blame]177 // Vector OR with immediate
Owen Anderson080c0922010-11-05 19:27:46 +0000[diff] [blame]178 VORRIMM,
179 // Vector AND with NOT of immediate
Bob Wilsonb1dfa7a2010-11-28 06:51:26 +0000[diff] [blame]180 VBICIMM,
181
Cameron Zwarichc0e6d782011-03-30 23:01:21 +0000[diff] [blame]182 // Vector bitwise select
183 VBSL,
184
Bob Wilsonb1dfa7a2010-11-28 06:51:26 +0000[diff] [blame]185 // Vector load N-element structure to all lanes:
186 VLD2DUP = ISD::FIRST_TARGET_MEMORY_OPCODE,
187 VLD3DUP,
Bob Wilson1c3ef902011-02-07 17:43:21 +0000[diff] [blame]188 VLD4DUP,
189
190 // NEON loads with post-increment base updates:
191 VLD1_UPD,
192 VLD2_UPD,
193 VLD3_UPD,
194 VLD4_UPD,
195 VLD2LN_UPD,
196 VLD3LN_UPD,
197 VLD4LN_UPD,
198 VLD2DUP_UPD,
199 VLD3DUP_UPD,
200 VLD4DUP_UPD,
201
202 // NEON stores with post-increment base updates:
203 VST1_UPD,
204 VST2_UPD,
205 VST3_UPD,
206 VST4_UPD,
207 VST2LN_UPD,
208 VST3LN_UPD,
209 VST4LN_UPD
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]210 };
211 }
212
Bob Wilson5bafff32009-06-22 23:27:02 +0000[diff] [blame]213 /// Define some predicates that are used for node matching.
214 namespace ARM {
Evan Cheng39382422009-10-28 01:44:26 +0000[diff] [blame]215 /// getVFPf32Imm / getVFPf64Imm - If the given fp immediate can be
216 /// materialized with a VMOV.f32 / VMOV.f64 (i.e. fconsts / fconstd)
217 /// instruction, returns its 8-bit integer representation. Otherwise,
218 /// returns -1.
219 int getVFPf32Imm(const APFloat &FPImm);
220 int getVFPf64Imm(const APFloat &FPImm);
Jim Grosbach469bbdb2010-07-16 23:05:05 +0000[diff] [blame]221 bool isBitFieldInvertedMask(unsigned v);
Bob Wilson5bafff32009-06-22 23:27:02 +0000[diff] [blame]222 }
223
Bob Wilson261f2a22009-05-20 16:30:25 +0000[diff] [blame]224 //===--------------------------------------------------------------------===//
Dale Johannesen80dae192007-03-20 00:30:56 +0000[diff] [blame]225 // ARMTargetLowering - ARM Implementation of the TargetLowering interface
Jim Grosbach6aa71972009-05-13 22:32:43 +0000[diff] [blame]226
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]227 class ARMTargetLowering : public TargetLowering {
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]228 public:
Dan Gohman61e729e2007-08-02 21:21:54 +0000[diff] [blame]229 explicit ARMTargetLowering(TargetMachine &TM);
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]230
Jim Grosbache1102ca2010-07-19 17:20:38 +0000[diff] [blame]231 virtual unsigned getJumpTableEncoding(void) const;
232
Dan Gohmand858e902010-04-17 15:26:15 +0000[diff] [blame]233 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
Duncan Sands1607f052008-12-01 11:39:25 +0000[diff] [blame]234
235 /// ReplaceNodeResults - Replace the results of node with an illegal result
236 /// type with new values built out of custom code.
237 ///
238 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
Dan Gohmand858e902010-04-17 15:26:15 +0000[diff] [blame]239 SelectionDAG &DAG) const;
Duncan Sands1607f052008-12-01 11:39:25 +0000[diff] [blame]240
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]241 virtual const char *getTargetNodeName(unsigned Opcode) const;
242
Dan Gohmanaf1d8ca2010-05-01 00:01:06 +0000[diff] [blame]243 virtual MachineBasicBlock *
244 EmitInstrWithCustomInserter(MachineInstr *MI,
245 MachineBasicBlock *MBB) const;
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]246
Evan Chenge721f5c2011-07-13 00:42:17 +0000[diff] [blame^]247 SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG) const;
Evan Cheng31959b12011-02-02 01:06:55 +0000[diff] [blame]248 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
249
250 bool isDesirableToTransformToIntegerOp(unsigned Opc, EVT VT) const;
251
Bill Wendlingaf566342009-08-15 21:21:19 +0000[diff] [blame]252 /// allowsUnalignedMemoryAccesses - Returns true if the target allows
253 /// unaligned memory accesses. of the specified type.
254 /// FIXME: Add getOptimalMemOpType to implement memcpy with NEON?
255 virtual bool allowsUnalignedMemoryAccesses(EVT VT) const;
256
Chris Lattnerc9addb72007-03-30 23:15:24 +0000[diff] [blame]257 /// isLegalAddressingMode - Return true if the addressing mode represented
258 /// by AM is legal for this target, for a load/store of the specified type.
259 virtual bool isLegalAddressingMode(const AddrMode &AM, const Type *Ty)const;
Evan Chenge6c835f2009-08-14 20:09:37 +0000[diff] [blame]260 bool isLegalT2ScaledAddressingMode(const AddrMode &AM, EVT VT) const;
Jim Grosbach6aa71972009-05-13 22:32:43 +0000[diff] [blame]261
Evan Cheng77e47512009-11-11 19:05:52 +0000[diff] [blame]262 /// isLegalICmpImmediate - Return true if the specified immediate is legal
Jim Grosbach18f30e62010-06-02 21:53:11 +0000[diff] [blame]263 /// icmp immediate, that is the target has icmp instructions which can
264 /// compare a register against the immediate without having to materialize
265 /// the immediate into a register.
Evan Cheng06b53c02009-11-12 07:13:11 +0000[diff] [blame]266 virtual bool isLegalICmpImmediate(int64_t Imm) const;
Evan Cheng77e47512009-11-11 19:05:52 +0000[diff] [blame]267
Dan Gohmancca82142011-05-03 00:46:49 +0000[diff] [blame]268 /// isLegalAddImmediate - Return true if the specified immediate is legal
269 /// add immediate, that is the target has add instructions which can
270 /// add a register and the immediate without having to materialize
271 /// the immediate into a register.
272 virtual bool isLegalAddImmediate(int64_t Imm) const;
273
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]274 /// getPreIndexedAddressParts - returns true by value, base pointer and
275 /// offset pointer and addressing mode by reference if the node's address
276 /// can be legally represented as pre-indexed load / store address.
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]277 virtual bool getPreIndexedAddressParts(SDNode *N, SDValue &Base,
278 SDValue &Offset,
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]279 ISD::MemIndexedMode &AM,
Dan Gohman73e09142009-01-15 16:29:45 +0000[diff] [blame]280 SelectionDAG &DAG) const;
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]281
282 /// getPostIndexedAddressParts - returns true by value, base pointer and
283 /// offset pointer and addressing mode by reference if this node can be
284 /// combined with a load / store to form a post-indexed load / store.
285 virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op,
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]286 SDValue &Base, SDValue &Offset,
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]287 ISD::MemIndexedMode &AM,
Dan Gohman73e09142009-01-15 16:29:45 +0000[diff] [blame]288 SelectionDAG &DAG) const;
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]289
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]290 virtual void computeMaskedBitsForTargetNode(const SDValue Op,
Dan Gohman977a76f2008-02-13 22:28:48 +0000[diff] [blame]291 const APInt &Mask,
Jim Grosbach6aa71972009-05-13 22:32:43 +0000[diff] [blame]292 APInt &KnownZero,
Dan Gohmanfd29e0e2008-02-13 00:35:47 +0000[diff] [blame]293 APInt &KnownOne,
Dan Gohmanea859be2007-06-22 14:59:07 +0000[diff] [blame]294 const SelectionDAG &DAG,
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]295 unsigned Depth) const;
Bill Wendlingaf566342009-08-15 21:21:19 +0000[diff] [blame]296
297
Evan Cheng55d42002011-01-08 01:24:27 +0000[diff] [blame]298 virtual bool ExpandInlineAsm(CallInst *CI) const;
299
Chris Lattner4234f572007-03-25 02:14:49 +0000[diff] [blame]300 ConstraintType getConstraintType(const std::string &Constraint) const;
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]301
302 /// Examine constraint string and operand type and determine a weight value.
303 /// The operand object must already have been set up with the operand type.
304 ConstraintWeight getSingleConstraintMatchWeight(
305 AsmOperandInfo &info, const char *constraint) const;
306
Jim Grosbach6aa71972009-05-13 22:32:43 +0000[diff] [blame]307 std::pair<unsigned, const TargetRegisterClass*>
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]308 getRegForInlineAsmConstraint(const std::string &Constraint,
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]309 EVT VT) const;
Rafael Espindolaf1ba1ca2007-11-05 23:12:20 +0000[diff] [blame]310
Bob Wilsonbf6396b2009-04-01 17:58:54 +0000[diff] [blame]311 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
312 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is
313 /// true it means one of the asm constraint of the inline asm instruction
314 /// being processed is 'm'.
315 virtual void LowerAsmOperandForConstraint(SDValue Op,
Eric Christopher100c8332011-06-02 23:16:42 +0000[diff] [blame]316 std::string &Constraint,
Bob Wilsonbf6396b2009-04-01 17:58:54 +0000[diff] [blame]317 std::vector<SDValue> &Ops,
318 SelectionDAG &DAG) const;
Jim Grosbach6aa71972009-05-13 22:32:43 +0000[diff] [blame]319
Dan Gohman419e4f92010-05-11 16:21:03 +0000[diff] [blame]320 const ARMSubtarget* getSubtarget() const {
Dan Gohman707e0182008-04-12 04:36:06 +0000[diff] [blame]321 return Subtarget;
Rafael Espindolaf1ba1ca2007-11-05 23:12:20 +0000[diff] [blame]322 }
323
Evan Cheng06b666c2010-05-15 02:18:07 +0000[diff] [blame]324 /// getRegClassFor - Return the register class that should be used for the
325 /// specified value type.
326 virtual TargetRegisterClass *getRegClassFor(EVT VT) const;
327
Anton Korobeynikovcec36f42010-07-24 21:52:08 +0000[diff] [blame]328 /// getMaximalGlobalOffset - Returns the maximal possible offset which can
329 /// be used for loads / stores from the global.
330 virtual unsigned getMaximalGlobalOffset() const;
331
Eric Christopherab695882010-07-21 22:26:11 +0000[diff] [blame]332 /// createFastISel - This method returns a target specific FastISel object,
333 /// or null if the target does not support "fast" ISel.
334 virtual FastISel *createFastISel(FunctionLoweringInfo &funcInfo) const;
335
Evan Cheng1cc39842010-05-20 23:26:43 +0000[diff] [blame]336 Sched::Preference getSchedulingPreference(SDNode *N) const;
337
Anton Korobeynikovd0ac2342009-08-21 12:40:07 +0000[diff] [blame]338 bool isShuffleMaskLegal(const SmallVectorImpl<int> &M, EVT VT) const;
Anton Korobeynikov48e19352009-09-23 19:04:09 +0000[diff] [blame]339 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
Evan Cheng39382422009-10-28 01:44:26 +0000[diff] [blame]340
341 /// isFPImmLegal - Returns true if the target can instruction select the
342 /// specified FP immediate natively. If false, the legalizer will
343 /// materialize the FP immediate as a load from a constant pool.
344 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
345
Bob Wilson65ffec42010-09-21 17:56:22 +0000[diff] [blame]346 virtual bool getTgtMemIntrinsic(IntrinsicInfo &Info,
347 const CallInst &I,
348 unsigned Intrinsic) const;
Evan Chengd70f57b2010-07-19 22:15:08 +0000[diff] [blame]349 protected:
Evan Cheng4f6b4672010-07-21 06:09:07 +0000[diff] [blame]350 std::pair<const TargetRegisterClass*, uint8_t>
351 findRepresentativeClass(EVT VT) const;
Evan Chengd70f57b2010-07-19 22:15:08 +0000[diff] [blame]352
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]353 private:
354 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
355 /// make the right decision when generating code for different targets.
356 const ARMSubtarget *Subtarget;
357
Evan Cheng31446872010-07-23 22:39:59 +0000[diff] [blame]358 const TargetRegisterInfo *RegInfo;
359
Evan Cheng3ef1c872010-09-10 01:29:16 +0000[diff] [blame]360 const InstrItineraryData *Itins;
361
Bob Wilsond2559bf2009-07-13 18:11:36 +0000[diff] [blame]362 /// ARMPCLabelIndex - Keep track of the number of ARM PC labels created.
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]363 ///
364 unsigned ARMPCLabelIndex;
365
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]366 void addTypeForNEON(EVT VT, EVT PromotedLdStVT, EVT PromotedBitwiseVT);
367 void addDRTypeForNEON(EVT VT);
368 void addQRTypeForNEON(EVT VT);
Bob Wilson5bafff32009-06-22 23:27:02 +0000[diff] [blame]369
370 typedef SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPassVector;
Dan Gohman98ca4f22009-08-05 01:29:28 +0000[diff] [blame]371 void PassF64ArgInRegs(DebugLoc dl, SelectionDAG &DAG,
Bob Wilson5bafff32009-06-22 23:27:02 +0000[diff] [blame]372 SDValue Chain, SDValue &Arg,
373 RegsToPassVector &RegsToPass,
374 CCValAssign &VA, CCValAssign &NextVA,
375 SDValue &StackPtr,
376 SmallVector<SDValue, 8> &MemOpChains,
Dan Gohmand858e902010-04-17 15:26:15 +0000[diff] [blame]377 ISD::ArgFlagsTy Flags) const;
Bob Wilson5bafff32009-06-22 23:27:02 +0000[diff] [blame]378 SDValue GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
Dan Gohmand858e902010-04-17 15:26:15 +0000[diff] [blame]379 SDValue &Root, SelectionDAG &DAG,
380 DebugLoc dl) const;
Bob Wilson5bafff32009-06-22 23:27:02 +0000[diff] [blame]381
Jim Grosbach18f30e62010-06-02 21:53:11 +0000[diff] [blame]382 CCAssignFn *CCAssignFnForNode(CallingConv::ID CC, bool Return,
383 bool isVarArg) const;
Dan Gohman98ca4f22009-08-05 01:29:28 +0000[diff] [blame]384 SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg,
385 DebugLoc dl, SelectionDAG &DAG,
386 const CCValAssign &VA,
Dan Gohmand858e902010-04-17 15:26:15 +0000[diff] [blame]387 ISD::ArgFlagsTy Flags) const;
Jim Grosbach23ff7cf2010-05-26 20:22:18 +0000[diff] [blame]388 SDValue LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const;
Jim Grosbach5eb19512010-05-22 01:06:18 +0000[diff] [blame]389 SDValue LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const;
Jim Grosbache4ad3872010-10-19 23:27:08 +0000[diff] [blame]390 SDValue LowerEH_SJLJ_DISPATCHSETUP(SDValue Op, SelectionDAG &DAG) const;
Jim Grosbacha87ded22010-02-08 23:22:00 +0000[diff] [blame]391 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG,
Dan Gohmand858e902010-04-17 15:26:15 +0000[diff] [blame]392 const ARMSubtarget *Subtarget) const;
393 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
394 SDValue LowerGlobalAddressDarwin(SDValue Op, SelectionDAG &DAG) const;
395 SDValue LowerGlobalAddressELF(SDValue Op, SelectionDAG &DAG) const;
396 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]397 SDValue LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
Dan Gohmand858e902010-04-17 15:26:15 +0000[diff] [blame]398 SelectionDAG &DAG) const;
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]399 SDValue LowerToTLSExecModels(GlobalAddressSDNode *GA,
Dan Gohmand858e902010-04-17 15:26:15 +0000[diff] [blame]400 SelectionDAG &DAG) const;
401 SDValue LowerGLOBAL_OFFSET_TABLE(SDValue Op, SelectionDAG &DAG) const;
402 SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
Bill Wendlingde2b1512010-08-11 08:43:16 +0000[diff] [blame]403 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
Dan Gohmand858e902010-04-17 15:26:15 +0000[diff] [blame]404 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
405 SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
Evan Cheng515fe3a2010-07-08 02:08:50 +0000[diff] [blame]406 SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
Evan Cheng2457f2c2010-05-22 01:47:14 +0000[diff] [blame]407 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
Dan Gohmand858e902010-04-17 15:26:15 +0000[diff] [blame]408 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
Dan Gohmand858e902010-04-17 15:26:15 +0000[diff] [blame]409 SDValue LowerShiftRightParts(SDValue Op, SelectionDAG &DAG) const;
410 SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const;
Nate Begemand1fb5832010-08-03 21:31:55 +0000[diff] [blame]411 SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
Andrew Trick5adfba22011-04-23 03:24:11 +0000[diff] [blame]412 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
Bob Wilson11a1dff2011-01-07 21:37:30 +0000[diff] [blame]413 const ARMSubtarget *ST) const;
414
415 SDValue ReconstructShuffle(SDValue Op, SelectionDAG &DAG) const;
Rafael Espindola7b73a5d2007-10-19 14:35:17 +0000[diff] [blame]416
Dan Gohman98ca4f22009-08-05 01:29:28 +0000[diff] [blame]417 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
Sandeep Patel65c3c8f2009-09-02 08:44:58 +0000[diff] [blame]418 CallingConv::ID CallConv, bool isVarArg,
Dan Gohman98ca4f22009-08-05 01:29:28 +0000[diff] [blame]419 const SmallVectorImpl<ISD::InputArg> &Ins,
420 DebugLoc dl, SelectionDAG &DAG,
Dan Gohmand858e902010-04-17 15:26:15 +0000[diff] [blame]421 SmallVectorImpl<SDValue> &InVals) const;
Dan Gohman98ca4f22009-08-05 01:29:28 +0000[diff] [blame]422
423 virtual SDValue
424 LowerFormalArguments(SDValue Chain,
Sandeep Patel65c3c8f2009-09-02 08:44:58 +0000[diff] [blame]425 CallingConv::ID CallConv, bool isVarArg,
Dan Gohman98ca4f22009-08-05 01:29:28 +0000[diff] [blame]426 const SmallVectorImpl<ISD::InputArg> &Ins,
427 DebugLoc dl, SelectionDAG &DAG,
Dan Gohmand858e902010-04-17 15:26:15 +0000[diff] [blame]428 SmallVectorImpl<SDValue> &InVals) const;
Dan Gohman98ca4f22009-08-05 01:29:28 +0000[diff] [blame]429
Stuart Hastingsc7315872011-04-20 16:47:52 +0000[diff] [blame]430 void VarArgStyleRegisters(CCState &CCInfo, SelectionDAG &DAG,
431 DebugLoc dl, SDValue &Chain, unsigned ArgOffset)
432 const;
433
434 void computeRegArea(CCState &CCInfo, MachineFunction &MF,
435 unsigned &VARegSize, unsigned &VARegSaveSize) const;
436
Dan Gohman98ca4f22009-08-05 01:29:28 +0000[diff] [blame]437 virtual SDValue
Evan Cheng022d9e12010-02-02 23:55:14 +0000[diff] [blame]438 LowerCall(SDValue Chain, SDValue Callee,
Sandeep Patel65c3c8f2009-09-02 08:44:58 +0000[diff] [blame]439 CallingConv::ID CallConv, bool isVarArg,
Evan Cheng0c439eb2010-01-27 00:07:07 +0000[diff] [blame]440 bool &isTailCall,
Dan Gohman98ca4f22009-08-05 01:29:28 +0000[diff] [blame]441 const SmallVectorImpl<ISD::OutputArg> &Outs,
Dan Gohmanc9403652010-07-07 15:54:55 +0000[diff] [blame]442 const SmallVectorImpl<SDValue> &OutVals,
Dan Gohman98ca4f22009-08-05 01:29:28 +0000[diff] [blame]443 const SmallVectorImpl<ISD::InputArg> &Ins,
444 DebugLoc dl, SelectionDAG &DAG,
Dan Gohmand858e902010-04-17 15:26:15 +0000[diff] [blame]445 SmallVectorImpl<SDValue> &InVals) const;
Dan Gohman98ca4f22009-08-05 01:29:28 +0000[diff] [blame]446
Stuart Hastingsf222e592011-02-28 17:17:53 +0000[diff] [blame]447 /// HandleByVal - Target-specific cleanup for ByVal support.
Stuart Hastingsc7315872011-04-20 16:47:52 +0000[diff] [blame]448 virtual void HandleByVal(CCState *, unsigned &) const;
Stuart Hastingsf222e592011-02-28 17:17:53 +0000[diff] [blame]449
Dale Johannesen51e28e62010-06-03 21:09:53 +0000[diff] [blame]450 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
451 /// for tail call optimization. Targets which want to do tail call
452 /// optimization should implement this function.
453 bool IsEligibleForTailCallOptimization(SDValue Callee,
454 CallingConv::ID CalleeCC,
455 bool isVarArg,
456 bool isCalleeStructRet,
457 bool isCallerStructRet,
458 const SmallVectorImpl<ISD::OutputArg> &Outs,
Dan Gohmanc9403652010-07-07 15:54:55 +0000[diff] [blame]459 const SmallVectorImpl<SDValue> &OutVals,
Dale Johannesen51e28e62010-06-03 21:09:53 +0000[diff] [blame]460 const SmallVectorImpl<ISD::InputArg> &Ins,
461 SelectionDAG& DAG) const;
Dan Gohman98ca4f22009-08-05 01:29:28 +0000[diff] [blame]462 virtual SDValue
463 LowerReturn(SDValue Chain,
Sandeep Patel65c3c8f2009-09-02 08:44:58 +0000[diff] [blame]464 CallingConv::ID CallConv, bool isVarArg,
Dan Gohman98ca4f22009-08-05 01:29:28 +0000[diff] [blame]465 const SmallVectorImpl<ISD::OutputArg> &Outs,
Dan Gohmanc9403652010-07-07 15:54:55 +0000[diff] [blame]466 const SmallVectorImpl<SDValue> &OutVals,
Dan Gohmand858e902010-04-17 15:26:15 +0000[diff] [blame]467 DebugLoc dl, SelectionDAG &DAG) const;
Evan Cheng06b53c02009-11-12 07:13:11 +0000[diff] [blame]468
Evan Cheng3d2125c2010-11-30 23:55:39 +0000[diff] [blame]469 virtual bool isUsedByReturnOnly(SDNode *N) const;
470
Evan Cheng485fafc2011-03-21 01:19:09 +0000[diff] [blame]471 virtual bool mayBeEmittedAsTailCall(CallInst *CI) const;
472
Evan Cheng06b53c02009-11-12 07:13:11 +0000[diff] [blame]473 SDValue getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
Evan Cheng218977b2010-07-13 19:27:42 +0000[diff] [blame]474 SDValue &ARMcc, SelectionDAG &DAG, DebugLoc dl) const;
475 SDValue getVFPCmp(SDValue LHS, SDValue RHS,
476 SelectionDAG &DAG, DebugLoc dl) const;
Bob Wilson79f56c92011-03-08 01:17:20 +0000[diff] [blame]477 SDValue duplicateCmp(SDValue Cmp, SelectionDAG &DAG) const;
Evan Cheng218977b2010-07-13 19:27:42 +0000[diff] [blame]478
479 SDValue OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const;
Jim Grosbach5278eb82009-12-11 01:42:04 +0000[diff] [blame]480
Jim Grosbache801dc42009-12-12 01:40:06 +0000[diff] [blame]481 MachineBasicBlock *EmitAtomicCmpSwap(MachineInstr *MI,
482 MachineBasicBlock *BB,
483 unsigned Size) const;
484 MachineBasicBlock *EmitAtomicBinary(MachineInstr *MI,
485 MachineBasicBlock *BB,
486 unsigned Size,
487 unsigned BinOpcode) const;
Jim Grosbachf7da8822011-04-26 19:44:18 +0000[diff] [blame]488 MachineBasicBlock * EmitAtomicBinaryMinMax(MachineInstr *MI,
489 MachineBasicBlock *BB,
490 unsigned Size,
491 bool signExtend,
492 ARMCC::CondCodes Cond) const;
Jim Grosbach5278eb82009-12-11 01:42:04 +0000[diff] [blame]493
Andrew Trick1c3af772011-04-23 03:55:32 +0000[diff] [blame]494 bool RemapAddSubWithFlags(MachineInstr *MI, MachineBasicBlock *BB) const;
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]495 };
Andrew Trick5adfba22011-04-23 03:24:11 +0000[diff] [blame]496
Owen Anderson36fa3ea2010-11-05 21:57:54 +0000[diff] [blame]497 enum NEONModImmType {
498 VMOVModImm,
499 VMVNModImm,
500 OtherModImm
501 };
Andrew Trick5adfba22011-04-23 03:24:11 +0000[diff] [blame]502
503
Eric Christopherab695882010-07-21 22:26:11 +0000[diff] [blame]504 namespace ARM {
505 FastISel *createFastISel(FunctionLoweringInfo &funcInfo);
506 }
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]507}
508
509#endif // ARMISELLOWERING_H