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Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +00001//===-- llvm/CodeGen/VirtRegMap.cpp - Virtual Register Map ----------------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file was developed by the LLVM research group and is distributed under
6// the University of Illinois Open Source License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
Chris Lattner8c4d88d2004-09-30 01:54:45 +000010// This file implements the VirtRegMap class.
11//
12// It also contains implementations of the the Spiller interface, which, given a
13// virtual register map and a machine function, eliminates all virtual
14// references by replacing them with physical register references - adding spill
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +000015// code as necessary.
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000016//
17//===----------------------------------------------------------------------===//
18
Chris Lattner8c4d88d2004-09-30 01:54:45 +000019#define DEBUG_TYPE "spiller"
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000020#include "VirtRegMap.h"
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +000021#include "llvm/Function.h"
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000022#include "llvm/CodeGen/MachineFrameInfo.h"
Chris Lattner8c4d88d2004-09-30 01:54:45 +000023#include "llvm/CodeGen/MachineFunction.h"
24#include "llvm/CodeGen/SSARegMap.h"
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000025#include "llvm/Target/TargetMachine.h"
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +000026#include "llvm/Target/TargetInstrInfo.h"
Reid Spencer551ccae2004-09-01 22:55:40 +000027#include "llvm/Support/CommandLine.h"
28#include "llvm/Support/Debug.h"
Chris Lattnera4f0b3a2006-08-27 12:54:02 +000029#include "llvm/Support/Compiler.h"
Evan Cheng957840b2007-02-21 02:22:03 +000030#include "llvm/ADT/BitVector.h"
Reid Spencer551ccae2004-09-01 22:55:40 +000031#include "llvm/ADT/Statistic.h"
32#include "llvm/ADT/STLExtras.h"
Chris Lattner08a4d5a2007-01-23 00:59:48 +000033#include "llvm/ADT/SmallSet.h"
Chris Lattner27f29162004-10-26 15:35:58 +000034#include <algorithm>
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000035using namespace llvm;
36
Chris Lattnercd3245a2006-12-19 22:41:21 +000037STATISTIC(NumSpills, "Number of register spills");
Evan Cheng2638e1a2007-03-20 08:13:50 +000038STATISTIC(NumReMats, "Number of re-materialization");
Chris Lattnercd3245a2006-12-19 22:41:21 +000039STATISTIC(NumStores, "Number of stores added");
40STATISTIC(NumLoads , "Number of loads added");
41STATISTIC(NumReused, "Number of values reused");
42STATISTIC(NumDSE , "Number of dead stores elided");
43STATISTIC(NumDCE , "Number of copies elided");
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +000044
Chris Lattnercd3245a2006-12-19 22:41:21 +000045namespace {
Chris Lattner8c4d88d2004-09-30 01:54:45 +000046 enum SpillerName { simple, local };
Alkis Evlogimenosdd420e02004-03-01 23:18:15 +000047
Andrew Lenharthed41f1b2006-07-20 17:28:38 +000048 static cl::opt<SpillerName>
Chris Lattner8c4d88d2004-09-30 01:54:45 +000049 SpillerOpt("spiller",
Chris Lattner7fb64342004-10-01 19:04:51 +000050 cl::desc("Spiller to use: (default: local)"),
Chris Lattner8c4d88d2004-09-30 01:54:45 +000051 cl::Prefix,
52 cl::values(clEnumVal(simple, " simple spiller"),
53 clEnumVal(local, " local spiller"),
54 clEnumValEnd),
Chris Lattner7fb64342004-10-01 19:04:51 +000055 cl::init(local));
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000056}
57
Chris Lattner8c4d88d2004-09-30 01:54:45 +000058//===----------------------------------------------------------------------===//
59// VirtRegMap implementation
60//===----------------------------------------------------------------------===//
61
Chris Lattner29268692006-09-05 02:12:02 +000062VirtRegMap::VirtRegMap(MachineFunction &mf)
63 : TII(*mf.getTarget().getInstrInfo()), MF(mf),
Evan Cheng2638e1a2007-03-20 08:13:50 +000064 Virt2PhysMap(NO_PHYS_REG), Virt2StackSlotMap(NO_STACK_SLOT),
65 ReMatId(MAX_STACK_SLOT+1) {
Chris Lattner29268692006-09-05 02:12:02 +000066 grow();
67}
68
Chris Lattner8c4d88d2004-09-30 01:54:45 +000069void VirtRegMap::grow() {
Chris Lattner7f690e62004-09-30 02:15:18 +000070 Virt2PhysMap.grow(MF.getSSARegMap()->getLastVirtReg());
71 Virt2StackSlotMap.grow(MF.getSSARegMap()->getLastVirtReg());
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000072}
73
Chris Lattner8c4d88d2004-09-30 01:54:45 +000074int VirtRegMap::assignVirt2StackSlot(unsigned virtReg) {
75 assert(MRegisterInfo::isVirtualRegister(virtReg));
Chris Lattner7f690e62004-09-30 02:15:18 +000076 assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT &&
Chris Lattner8c4d88d2004-09-30 01:54:45 +000077 "attempt to assign stack slot to already spilled register");
Chris Lattner7f690e62004-09-30 02:15:18 +000078 const TargetRegisterClass* RC = MF.getSSARegMap()->getRegClass(virtReg);
79 int frameIndex = MF.getFrameInfo()->CreateStackObject(RC->getSize(),
80 RC->getAlignment());
81 Virt2StackSlotMap[virtReg] = frameIndex;
Chris Lattner8c4d88d2004-09-30 01:54:45 +000082 ++NumSpills;
83 return frameIndex;
84}
85
86void VirtRegMap::assignVirt2StackSlot(unsigned virtReg, int frameIndex) {
87 assert(MRegisterInfo::isVirtualRegister(virtReg));
Chris Lattner7f690e62004-09-30 02:15:18 +000088 assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT &&
Chris Lattner8c4d88d2004-09-30 01:54:45 +000089 "attempt to assign stack slot to already spilled register");
Evan Cheng91935142007-04-04 07:40:01 +000090 assert((frameIndex >= 0 ||
91 (frameIndex >= MF.getFrameInfo()->getObjectIndexBegin())) &&
92 "illegal fixed frame index");
Chris Lattner7f690e62004-09-30 02:15:18 +000093 Virt2StackSlotMap[virtReg] = frameIndex;
Alkis Evlogimenos38af59a2004-05-29 20:38:05 +000094}
95
Evan Cheng2638e1a2007-03-20 08:13:50 +000096int VirtRegMap::assignVirtReMatId(unsigned virtReg) {
97 assert(MRegisterInfo::isVirtualRegister(virtReg));
98 assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT &&
99 "attempt to assign re-mat id to already spilled register");
Evan Cheng91935142007-04-04 07:40:01 +0000100 const MachineInstr *DefMI = getReMaterializedMI(virtReg);
101 int FrameIdx;
102 if (TII.isLoadFromStackSlot((MachineInstr*)DefMI, FrameIdx)) {
103 // Load from stack slot is re-materialize as reload from the stack slot!
104 Virt2StackSlotMap[virtReg] = FrameIdx;
105 return FrameIdx;
106 }
Evan Cheng2638e1a2007-03-20 08:13:50 +0000107 Virt2StackSlotMap[virtReg] = ReMatId;
Evan Cheng2638e1a2007-03-20 08:13:50 +0000108 return ReMatId++;
109}
110
Chris Lattnerbec6a9e2004-10-01 23:15:36 +0000111void VirtRegMap::virtFolded(unsigned VirtReg, MachineInstr *OldMI,
Chris Lattner35f27052006-05-01 21:16:03 +0000112 unsigned OpNo, MachineInstr *NewMI) {
Chris Lattnerbec6a9e2004-10-01 23:15:36 +0000113 // Move previous memory references folded to new instruction.
114 MI2VirtMapTy::iterator IP = MI2VirtMap.lower_bound(NewMI);
Misha Brukmanedf128a2005-04-21 22:36:52 +0000115 for (MI2VirtMapTy::iterator I = MI2VirtMap.lower_bound(OldMI),
Chris Lattnerbec6a9e2004-10-01 23:15:36 +0000116 E = MI2VirtMap.end(); I != E && I->first == OldMI; ) {
117 MI2VirtMap.insert(IP, std::make_pair(NewMI, I->second));
Chris Lattnerdbea9732004-09-30 16:35:08 +0000118 MI2VirtMap.erase(I++);
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000119 }
Chris Lattnerdbea9732004-09-30 16:35:08 +0000120
Chris Lattnerbec6a9e2004-10-01 23:15:36 +0000121 ModRef MRInfo;
Evan Cheng5c2a4602006-12-08 08:02:34 +0000122 const TargetInstrDescriptor *TID = OldMI->getInstrDescriptor();
123 if (TID->getOperandConstraint(OpNo, TOI::TIED_TO) != -1 ||
Evan Chengcc22a7a2006-12-08 18:45:48 +0000124 TID->findTiedToSrcOperand(OpNo) != -1) {
Chris Lattner29268692006-09-05 02:12:02 +0000125 // Folded a two-address operand.
126 MRInfo = isModRef;
127 } else if (OldMI->getOperand(OpNo).isDef()) {
128 MRInfo = isMod;
Chris Lattnerbec6a9e2004-10-01 23:15:36 +0000129 } else {
Chris Lattner29268692006-09-05 02:12:02 +0000130 MRInfo = isRef;
Chris Lattnerbec6a9e2004-10-01 23:15:36 +0000131 }
Alkis Evlogimenos5f375022004-03-01 20:05:10 +0000132
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000133 // add new memory reference
Chris Lattnerbec6a9e2004-10-01 23:15:36 +0000134 MI2VirtMap.insert(IP, std::make_pair(NewMI, std::make_pair(VirtReg, MRInfo)));
Alkis Evlogimenos5f375022004-03-01 20:05:10 +0000135}
136
Chris Lattner7f690e62004-09-30 02:15:18 +0000137void VirtRegMap::print(std::ostream &OS) const {
138 const MRegisterInfo* MRI = MF.getTarget().getRegisterInfo();
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +0000139
Chris Lattner7f690e62004-09-30 02:15:18 +0000140 OS << "********** REGISTER MAP **********\n";
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000141 for (unsigned i = MRegisterInfo::FirstVirtualRegister,
Chris Lattner7f690e62004-09-30 02:15:18 +0000142 e = MF.getSSARegMap()->getLastVirtReg(); i <= e; ++i) {
143 if (Virt2PhysMap[i] != (unsigned)VirtRegMap::NO_PHYS_REG)
144 OS << "[reg" << i << " -> " << MRI->getName(Virt2PhysMap[i]) << "]\n";
Misha Brukmanedf128a2005-04-21 22:36:52 +0000145
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000146 }
147
148 for (unsigned i = MRegisterInfo::FirstVirtualRegister,
Chris Lattner7f690e62004-09-30 02:15:18 +0000149 e = MF.getSSARegMap()->getLastVirtReg(); i <= e; ++i)
150 if (Virt2StackSlotMap[i] != VirtRegMap::NO_STACK_SLOT)
151 OS << "[reg" << i << " -> fi#" << Virt2StackSlotMap[i] << "]\n";
152 OS << '\n';
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +0000153}
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +0000154
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000155void VirtRegMap::dump() const {
Bill Wendling5c7e3262006-12-17 05:15:13 +0000156 print(DOUT);
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000157}
Alkis Evlogimenosdd420e02004-03-01 23:18:15 +0000158
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000159
160//===----------------------------------------------------------------------===//
161// Simple Spiller Implementation
162//===----------------------------------------------------------------------===//
163
164Spiller::~Spiller() {}
Alkis Evlogimenosdd420e02004-03-01 23:18:15 +0000165
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +0000166namespace {
Chris Lattnerf8c68f62006-06-28 22:17:39 +0000167 struct VISIBILITY_HIDDEN SimpleSpiller : public Spiller {
Chris Lattner35f27052006-05-01 21:16:03 +0000168 bool runOnMachineFunction(MachineFunction& mf, VirtRegMap &VRM);
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000169 };
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +0000170}
171
Chris Lattner35f27052006-05-01 21:16:03 +0000172bool SimpleSpiller::runOnMachineFunction(MachineFunction &MF, VirtRegMap &VRM) {
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000173 DOUT << "********** REWRITE MACHINE CODE **********\n";
174 DOUT << "********** Function: " << MF.getFunction()->getName() << '\n';
Chris Lattnerb0f31bf2005-01-23 22:45:13 +0000175 const TargetMachine &TM = MF.getTarget();
176 const MRegisterInfo &MRI = *TM.getRegisterInfo();
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000177
Chris Lattner4ea1b822004-09-30 02:33:48 +0000178 // LoadedRegs - Keep track of which vregs are loaded, so that we only load
179 // each vreg once (in the case where a spilled vreg is used by multiple
180 // operands). This is always smaller than the number of operands to the
181 // current machine instr, so it should be small.
182 std::vector<unsigned> LoadedRegs;
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000183
Chris Lattner0fc27cc2004-09-30 02:59:33 +0000184 for (MachineFunction::iterator MBBI = MF.begin(), E = MF.end();
185 MBBI != E; ++MBBI) {
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000186 DOUT << MBBI->getBasicBlock()->getName() << ":\n";
Chris Lattner0fc27cc2004-09-30 02:59:33 +0000187 MachineBasicBlock &MBB = *MBBI;
188 for (MachineBasicBlock::iterator MII = MBB.begin(),
189 E = MBB.end(); MII != E; ++MII) {
190 MachineInstr &MI = *MII;
191 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
Chris Lattner7fb64342004-10-01 19:04:51 +0000192 MachineOperand &MO = MI.getOperand(i);
Chris Lattner886dd912005-04-04 21:35:34 +0000193 if (MO.isRegister() && MO.getReg())
194 if (MRegisterInfo::isVirtualRegister(MO.getReg())) {
195 unsigned VirtReg = MO.getReg();
196 unsigned PhysReg = VRM.getPhys(VirtReg);
197 if (VRM.hasStackSlot(VirtReg)) {
198 int StackSlot = VRM.getStackSlot(VirtReg);
Chris Lattnerbf9716b2005-09-30 01:29:00 +0000199 const TargetRegisterClass* RC =
200 MF.getSSARegMap()->getRegClass(VirtReg);
Misha Brukmanedf128a2005-04-21 22:36:52 +0000201
Chris Lattner886dd912005-04-04 21:35:34 +0000202 if (MO.isUse() &&
203 std::find(LoadedRegs.begin(), LoadedRegs.end(), VirtReg)
204 == LoadedRegs.end()) {
Chris Lattnerbf9716b2005-09-30 01:29:00 +0000205 MRI.loadRegFromStackSlot(MBB, &MI, PhysReg, StackSlot, RC);
Chris Lattner886dd912005-04-04 21:35:34 +0000206 LoadedRegs.push_back(VirtReg);
207 ++NumLoads;
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000208 DOUT << '\t' << *prior(MII);
Chris Lattner886dd912005-04-04 21:35:34 +0000209 }
Misha Brukmanedf128a2005-04-21 22:36:52 +0000210
Chris Lattner886dd912005-04-04 21:35:34 +0000211 if (MO.isDef()) {
Chris Lattnerbf9716b2005-09-30 01:29:00 +0000212 MRI.storeRegToStackSlot(MBB, next(MII), PhysReg, StackSlot, RC);
Chris Lattner886dd912005-04-04 21:35:34 +0000213 ++NumStores;
214 }
Chris Lattner0fc27cc2004-09-30 02:59:33 +0000215 }
Evan Cheng6c087e52007-04-25 22:13:27 +0000216 MF.setPhysRegUsed(PhysReg);
Chris Lattnere53f4a02006-05-04 17:52:23 +0000217 MI.getOperand(i).setReg(PhysReg);
Chris Lattner886dd912005-04-04 21:35:34 +0000218 } else {
Evan Cheng6c087e52007-04-25 22:13:27 +0000219 MF.setPhysRegUsed(MO.getReg());
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000220 }
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000221 }
Chris Lattner886dd912005-04-04 21:35:34 +0000222
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000223 DOUT << '\t' << MI;
Chris Lattner4ea1b822004-09-30 02:33:48 +0000224 LoadedRegs.clear();
Alkis Evlogimenosdd420e02004-03-01 23:18:15 +0000225 }
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000226 }
227 return true;
228}
229
230//===----------------------------------------------------------------------===//
231// Local Spiller Implementation
232//===----------------------------------------------------------------------===//
233
234namespace {
Chris Lattner7fb64342004-10-01 19:04:51 +0000235 /// LocalSpiller - This spiller does a simple pass over the machine basic
236 /// block to attempt to keep spills in registers as much as possible for
237 /// blocks that have low register pressure (the vreg may be spilled due to
238 /// register pressure in other blocks).
Chris Lattnerf8c68f62006-06-28 22:17:39 +0000239 class VISIBILITY_HIDDEN LocalSpiller : public Spiller {
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000240 const MRegisterInfo *MRI;
Chris Lattner7fb64342004-10-01 19:04:51 +0000241 const TargetInstrInfo *TII;
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000242 public:
Chris Lattner35f27052006-05-01 21:16:03 +0000243 bool runOnMachineFunction(MachineFunction &MF, VirtRegMap &VRM) {
Chris Lattner7fb64342004-10-01 19:04:51 +0000244 MRI = MF.getTarget().getRegisterInfo();
245 TII = MF.getTarget().getInstrInfo();
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000246 DOUT << "\n**** Local spiller rewriting function '"
247 << MF.getFunction()->getName() << "':\n";
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000248
Evan Cheng2638e1a2007-03-20 08:13:50 +0000249 std::vector<MachineInstr *> ReMatedMIs;
Chris Lattner7fb64342004-10-01 19:04:51 +0000250 for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
251 MBB != E; ++MBB)
Evan Cheng2638e1a2007-03-20 08:13:50 +0000252 RewriteMBB(*MBB, VRM, ReMatedMIs);
253 for (unsigned i = 0, e = ReMatedMIs.size(); i != e; ++i)
254 delete ReMatedMIs[i];
Chris Lattner7fb64342004-10-01 19:04:51 +0000255 return true;
256 }
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000257 private:
Evan Cheng2638e1a2007-03-20 08:13:50 +0000258 void RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM,
259 std::vector<MachineInstr*> &ReMatedMIs);
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000260 };
261}
262
Chris Lattner66cf80f2006-02-03 23:13:58 +0000263/// AvailableSpills - As the local spiller is scanning and rewriting an MBB from
264/// top down, keep track of which spills slots are available in each register.
Chris Lattner593c9582006-02-03 23:28:46 +0000265///
266/// Note that not all physregs are created equal here. In particular, some
267/// physregs are reloads that we are allowed to clobber or ignore at any time.
268/// Other physregs are values that the register allocated program is using that
269/// we cannot CHANGE, but we can read if we like. We keep track of this on a
270/// per-stack-slot basis as the low bit in the value of the SpillSlotsAvailable
271/// entries. The predicate 'canClobberPhysReg()' checks this bit and
272/// addAvailable sets it if.
Chris Lattnerf8c68f62006-06-28 22:17:39 +0000273namespace {
274class VISIBILITY_HIDDEN AvailableSpills {
Chris Lattner66cf80f2006-02-03 23:13:58 +0000275 const MRegisterInfo *MRI;
276 const TargetInstrInfo *TII;
277
278 // SpillSlotsAvailable - This map keeps track of all of the spilled virtual
279 // register values that are still available, due to being loaded or stored to,
Evan Cheng6b448092007-03-02 08:52:00 +0000280 // but not invalidated yet. It also tracks the instructions that defined
Evan Chengde4e9422007-02-25 09:51:27 +0000281 // or used the register.
Evan Cheng6b448092007-03-02 08:52:00 +0000282 typedef std::pair<unsigned, std::vector<MachineInstr*> > SSInfo;
Evan Cheng91e23902007-02-23 01:13:26 +0000283 std::map<int, SSInfo> SpillSlotsAvailable;
Chris Lattner66cf80f2006-02-03 23:13:58 +0000284
285 // PhysRegsAvailable - This is the inverse of SpillSlotsAvailable, indicating
286 // which stack slot values are currently held by a physreg. This is used to
287 // invalidate entries in SpillSlotsAvailable when a physreg is modified.
288 std::multimap<unsigned, int> PhysRegsAvailable;
289
Evan Cheng7a0d51c2006-12-14 07:54:05 +0000290 void disallowClobberPhysRegOnly(unsigned PhysReg);
291
Chris Lattner66cf80f2006-02-03 23:13:58 +0000292 void ClobberPhysRegOnly(unsigned PhysReg);
293public:
294 AvailableSpills(const MRegisterInfo *mri, const TargetInstrInfo *tii)
295 : MRI(mri), TII(tii) {
296 }
297
Evan Cheng91e23902007-02-23 01:13:26 +0000298 const MRegisterInfo *getRegInfo() const { return MRI; }
299
Chris Lattner66cf80f2006-02-03 23:13:58 +0000300 /// getSpillSlotPhysReg - If the specified stack slot is available in a
Evan Cheng91e23902007-02-23 01:13:26 +0000301 /// physical register, return that PhysReg, otherwise return 0. It also
302 /// returns by reference the instruction that either defines or last uses
303 /// the register.
304 unsigned getSpillSlotPhysReg(int Slot, MachineInstr *&SSMI) const {
305 std::map<int, SSInfo>::const_iterator I = SpillSlotsAvailable.find(Slot);
306 if (I != SpillSlotsAvailable.end()) {
Evan Cheng6b448092007-03-02 08:52:00 +0000307 if (!I->second.second.empty())
308 SSMI = I->second.second.back();
Evan Cheng91e23902007-02-23 01:13:26 +0000309 return I->second.first >> 1; // Remove the CanClobber bit.
310 }
Chris Lattner66cf80f2006-02-03 23:13:58 +0000311 return 0;
312 }
Evan Chengde4e9422007-02-25 09:51:27 +0000313
Evan Cheng6b448092007-03-02 08:52:00 +0000314 /// addLastUse - Add the last use information of all stack slots whose
Evan Chengde4e9422007-02-25 09:51:27 +0000315 /// values are available in the specific register.
Evan Cheng6b448092007-03-02 08:52:00 +0000316 void addLastUse(unsigned PhysReg, MachineInstr *Use) {
Evan Chengde4e9422007-02-25 09:51:27 +0000317 std::multimap<unsigned, int>::iterator I =
318 PhysRegsAvailable.lower_bound(PhysReg);
319 while (I != PhysRegsAvailable.end() && I->first == PhysReg) {
320 int Slot = I->second;
321 I++;
322
323 std::map<int, SSInfo>::iterator II = SpillSlotsAvailable.find(Slot);
324 assert(II != SpillSlotsAvailable.end() && "Slot not available!");
325 unsigned Val = II->second.first;
326 assert((Val >> 1) == PhysReg && "Bidirectional map mismatch!");
Evan Cheng7cb33c82007-03-30 20:21:35 +0000327 // This can be true if there are multiple uses of the same register.
328 if (II->second.second.back() != Use)
329 II->second.second.push_back(Use);
Evan Cheng6b448092007-03-02 08:52:00 +0000330 }
331 }
332
333 /// removeLastUse - Remove the last use information of all stack slots whose
334 /// values are available in the specific register.
335 void removeLastUse(unsigned PhysReg, MachineInstr *Use) {
336 std::multimap<unsigned, int>::iterator I =
337 PhysRegsAvailable.lower_bound(PhysReg);
338 while (I != PhysRegsAvailable.end() && I->first == PhysReg) {
339 int Slot = I->second;
340 I++;
341
342 std::map<int, SSInfo>::iterator II = SpillSlotsAvailable.find(Slot);
343 assert(II != SpillSlotsAvailable.end() && "Slot not available!");
344 unsigned Val = II->second.first;
345 assert((Val >> 1) == PhysReg && "Bidirectional map mismatch!");
346 if (II->second.second.back() == Use)
347 II->second.second.pop_back();
Evan Chengde4e9422007-02-25 09:51:27 +0000348 }
349 }
Chris Lattner540fec62006-02-25 01:51:33 +0000350
Chris Lattner66cf80f2006-02-03 23:13:58 +0000351 /// addAvailable - Mark that the specified stack slot is available in the
Chris Lattner593c9582006-02-03 23:28:46 +0000352 /// specified physreg. If CanClobber is true, the physreg can be modified at
353 /// any time without changing the semantics of the program.
Evan Cheng91e23902007-02-23 01:13:26 +0000354 void addAvailable(int Slot, MachineInstr *MI, unsigned Reg,
355 bool CanClobber = true) {
Chris Lattner86662492006-02-03 23:50:46 +0000356 // If this stack slot is thought to be available in some other physreg,
357 // remove its record.
358 ModifyStackSlot(Slot);
359
Chris Lattner66cf80f2006-02-03 23:13:58 +0000360 PhysRegsAvailable.insert(std::make_pair(Reg, Slot));
Evan Cheng6b448092007-03-02 08:52:00 +0000361 std::vector<MachineInstr*> DefUses;
362 DefUses.push_back(MI);
Evan Cheng91e23902007-02-23 01:13:26 +0000363 SpillSlotsAvailable[Slot] =
Evan Cheng6b448092007-03-02 08:52:00 +0000364 std::make_pair((Reg << 1) | (unsigned)CanClobber, DefUses);
Chris Lattner66cf80f2006-02-03 23:13:58 +0000365
Evan Cheng2638e1a2007-03-20 08:13:50 +0000366 if (Slot > VirtRegMap::MAX_STACK_SLOT)
367 DOUT << "Remembering RM#" << Slot-VirtRegMap::MAX_STACK_SLOT-1;
368 else
369 DOUT << "Remembering SS#" << Slot;
370 DOUT << " in physreg " << MRI->getName(Reg) << "\n";
Chris Lattner66cf80f2006-02-03 23:13:58 +0000371 }
Evan Cheng7a0d51c2006-12-14 07:54:05 +0000372
Chris Lattner593c9582006-02-03 23:28:46 +0000373 /// canClobberPhysReg - Return true if the spiller is allowed to change the
374 /// value of the specified stackslot register if it desires. The specified
375 /// stack slot must be available in a physreg for this query to make sense.
376 bool canClobberPhysReg(int Slot) const {
377 assert(SpillSlotsAvailable.count(Slot) && "Slot not available!");
Evan Cheng91e23902007-02-23 01:13:26 +0000378 return SpillSlotsAvailable.find(Slot)->second.first & 1;
Chris Lattner593c9582006-02-03 23:28:46 +0000379 }
Chris Lattner66cf80f2006-02-03 23:13:58 +0000380
Evan Cheng7a0d51c2006-12-14 07:54:05 +0000381 /// disallowClobberPhysReg - Unset the CanClobber bit of the specified
382 /// stackslot register. The register is still available but is no longer
383 /// allowed to be modifed.
384 void disallowClobberPhysReg(unsigned PhysReg);
385
Chris Lattner66cf80f2006-02-03 23:13:58 +0000386 /// ClobberPhysReg - This is called when the specified physreg changes
387 /// value. We use this to invalidate any info about stuff we thing lives in
388 /// it and any of its aliases.
389 void ClobberPhysReg(unsigned PhysReg);
390
391 /// ModifyStackSlot - This method is called when the value in a stack slot
392 /// changes. This removes information about which register the previous value
393 /// for this slot lives in (as the previous value is dead now).
394 void ModifyStackSlot(int Slot);
395};
Chris Lattnerf8c68f62006-06-28 22:17:39 +0000396}
Chris Lattner66cf80f2006-02-03 23:13:58 +0000397
Evan Cheng7a0d51c2006-12-14 07:54:05 +0000398/// disallowClobberPhysRegOnly - Unset the CanClobber bit of the specified
399/// stackslot register. The register is still available but is no longer
400/// allowed to be modifed.
401void AvailableSpills::disallowClobberPhysRegOnly(unsigned PhysReg) {
402 std::multimap<unsigned, int>::iterator I =
403 PhysRegsAvailable.lower_bound(PhysReg);
404 while (I != PhysRegsAvailable.end() && I->first == PhysReg) {
405 int Slot = I->second;
406 I++;
Evan Cheng91e23902007-02-23 01:13:26 +0000407 assert((SpillSlotsAvailable[Slot].first >> 1) == PhysReg &&
Evan Cheng7a0d51c2006-12-14 07:54:05 +0000408 "Bidirectional map mismatch!");
Evan Cheng91e23902007-02-23 01:13:26 +0000409 SpillSlotsAvailable[Slot].first &= ~1;
Evan Cheng7a0d51c2006-12-14 07:54:05 +0000410 DOUT << "PhysReg " << MRI->getName(PhysReg)
411 << " copied, it is available for use but can no longer be modified\n";
412 }
413}
414
415/// disallowClobberPhysReg - Unset the CanClobber bit of the specified
416/// stackslot register and its aliases. The register and its aliases may
417/// still available but is no longer allowed to be modifed.
418void AvailableSpills::disallowClobberPhysReg(unsigned PhysReg) {
419 for (const unsigned *AS = MRI->getAliasSet(PhysReg); *AS; ++AS)
420 disallowClobberPhysRegOnly(*AS);
421 disallowClobberPhysRegOnly(PhysReg);
422}
423
Chris Lattner66cf80f2006-02-03 23:13:58 +0000424/// ClobberPhysRegOnly - This is called when the specified physreg changes
425/// value. We use this to invalidate any info about stuff we thing lives in it.
426void AvailableSpills::ClobberPhysRegOnly(unsigned PhysReg) {
427 std::multimap<unsigned, int>::iterator I =
428 PhysRegsAvailable.lower_bound(PhysReg);
Chris Lattner07cf1412006-02-03 00:36:31 +0000429 while (I != PhysRegsAvailable.end() && I->first == PhysReg) {
Chris Lattner7fb64342004-10-01 19:04:51 +0000430 int Slot = I->second;
Chris Lattner07cf1412006-02-03 00:36:31 +0000431 PhysRegsAvailable.erase(I++);
Evan Cheng91e23902007-02-23 01:13:26 +0000432 assert((SpillSlotsAvailable[Slot].first >> 1) == PhysReg &&
Chris Lattner66cf80f2006-02-03 23:13:58 +0000433 "Bidirectional map mismatch!");
434 SpillSlotsAvailable.erase(Slot);
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000435 DOUT << "PhysReg " << MRI->getName(PhysReg)
Evan Cheng2638e1a2007-03-20 08:13:50 +0000436 << " clobbered, invalidating ";
437 if (Slot > VirtRegMap::MAX_STACK_SLOT)
438 DOUT << "RM#" << Slot-VirtRegMap::MAX_STACK_SLOT-1 << "\n";
439 else
440 DOUT << "SS#" << Slot << "\n";
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000441 }
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000442}
443
Chris Lattner66cf80f2006-02-03 23:13:58 +0000444/// ClobberPhysReg - This is called when the specified physreg changes
445/// value. We use this to invalidate any info about stuff we thing lives in
446/// it and any of its aliases.
447void AvailableSpills::ClobberPhysReg(unsigned PhysReg) {
Chris Lattner7fb64342004-10-01 19:04:51 +0000448 for (const unsigned *AS = MRI->getAliasSet(PhysReg); *AS; ++AS)
Chris Lattner66cf80f2006-02-03 23:13:58 +0000449 ClobberPhysRegOnly(*AS);
450 ClobberPhysRegOnly(PhysReg);
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000451}
452
Chris Lattner07cf1412006-02-03 00:36:31 +0000453/// ModifyStackSlot - This method is called when the value in a stack slot
454/// changes. This removes information about which register the previous value
455/// for this slot lives in (as the previous value is dead now).
Chris Lattner66cf80f2006-02-03 23:13:58 +0000456void AvailableSpills::ModifyStackSlot(int Slot) {
Evan Cheng91e23902007-02-23 01:13:26 +0000457 std::map<int, SSInfo>::iterator It = SpillSlotsAvailable.find(Slot);
Chris Lattner66cf80f2006-02-03 23:13:58 +0000458 if (It == SpillSlotsAvailable.end()) return;
Evan Cheng91e23902007-02-23 01:13:26 +0000459 unsigned Reg = It->second.first >> 1;
Chris Lattner66cf80f2006-02-03 23:13:58 +0000460 SpillSlotsAvailable.erase(It);
Chris Lattner07cf1412006-02-03 00:36:31 +0000461
462 // This register may hold the value of multiple stack slots, only remove this
463 // stack slot from the set of values the register contains.
464 std::multimap<unsigned, int>::iterator I = PhysRegsAvailable.lower_bound(Reg);
465 for (; ; ++I) {
466 assert(I != PhysRegsAvailable.end() && I->first == Reg &&
467 "Map inverse broken!");
468 if (I->second == Slot) break;
469 }
470 PhysRegsAvailable.erase(I);
471}
472
473
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000474
Chris Lattner7fb64342004-10-01 19:04:51 +0000475// ReusedOp - For each reused operand, we keep track of a bit of information, in
476// case we need to rollback upon processing a new operand. See comments below.
477namespace {
478 struct ReusedOp {
479 // The MachineInstr operand that reused an available value.
480 unsigned Operand;
Misha Brukmanedf128a2005-04-21 22:36:52 +0000481
Chris Lattner7fb64342004-10-01 19:04:51 +0000482 // StackSlot - The spill slot of the value being reused.
483 unsigned StackSlot;
Misha Brukmanedf128a2005-04-21 22:36:52 +0000484
Chris Lattner7fb64342004-10-01 19:04:51 +0000485 // PhysRegReused - The physical register the value was available in.
486 unsigned PhysRegReused;
Misha Brukmanedf128a2005-04-21 22:36:52 +0000487
Chris Lattner7fb64342004-10-01 19:04:51 +0000488 // AssignedPhysReg - The physreg that was assigned for use by the reload.
489 unsigned AssignedPhysReg;
Chris Lattner8a61a752005-10-06 17:19:06 +0000490
491 // VirtReg - The virtual register itself.
492 unsigned VirtReg;
Misha Brukmanedf128a2005-04-21 22:36:52 +0000493
Chris Lattner8a61a752005-10-06 17:19:06 +0000494 ReusedOp(unsigned o, unsigned ss, unsigned prr, unsigned apr,
495 unsigned vreg)
496 : Operand(o), StackSlot(ss), PhysRegReused(prr), AssignedPhysReg(apr),
497 VirtReg(vreg) {}
Chris Lattner7fb64342004-10-01 19:04:51 +0000498 };
Chris Lattner540fec62006-02-25 01:51:33 +0000499
500 /// ReuseInfo - This maintains a collection of ReuseOp's for each operand that
501 /// is reused instead of reloaded.
Chris Lattnerf8c68f62006-06-28 22:17:39 +0000502 class VISIBILITY_HIDDEN ReuseInfo {
Chris Lattner540fec62006-02-25 01:51:33 +0000503 MachineInstr &MI;
504 std::vector<ReusedOp> Reuses;
Evan Cheng957840b2007-02-21 02:22:03 +0000505 BitVector PhysRegsClobbered;
Chris Lattner540fec62006-02-25 01:51:33 +0000506 public:
Evan Chenge077ef62006-11-04 00:21:55 +0000507 ReuseInfo(MachineInstr &mi, const MRegisterInfo *mri) : MI(mi) {
Evan Cheng957840b2007-02-21 02:22:03 +0000508 PhysRegsClobbered.resize(mri->getNumRegs());
Evan Chenge077ef62006-11-04 00:21:55 +0000509 }
Chris Lattner540fec62006-02-25 01:51:33 +0000510
511 bool hasReuses() const {
512 return !Reuses.empty();
513 }
514
515 /// addReuse - If we choose to reuse a virtual register that is already
516 /// available instead of reloading it, remember that we did so.
517 void addReuse(unsigned OpNo, unsigned StackSlot,
518 unsigned PhysRegReused, unsigned AssignedPhysReg,
519 unsigned VirtReg) {
520 // If the reload is to the assigned register anyway, no undo will be
521 // required.
522 if (PhysRegReused == AssignedPhysReg) return;
523
524 // Otherwise, remember this.
525 Reuses.push_back(ReusedOp(OpNo, StackSlot, PhysRegReused,
526 AssignedPhysReg, VirtReg));
527 }
Evan Chenge077ef62006-11-04 00:21:55 +0000528
529 void markClobbered(unsigned PhysReg) {
Evan Cheng957840b2007-02-21 02:22:03 +0000530 PhysRegsClobbered.set(PhysReg);
Evan Chenge077ef62006-11-04 00:21:55 +0000531 }
532
533 bool isClobbered(unsigned PhysReg) const {
Evan Cheng957840b2007-02-21 02:22:03 +0000534 return PhysRegsClobbered.test(PhysReg);
Evan Chenge077ef62006-11-04 00:21:55 +0000535 }
Chris Lattner540fec62006-02-25 01:51:33 +0000536
537 /// GetRegForReload - We are about to emit a reload into PhysReg. If there
538 /// is some other operand that is using the specified register, either pick
539 /// a new register to use, or evict the previous reload and use this reg.
540 unsigned GetRegForReload(unsigned PhysReg, MachineInstr *MI,
541 AvailableSpills &Spills,
Evan Cheng3c82cab2007-01-19 22:40:14 +0000542 std::map<int, MachineInstr*> &MaybeDeadStores,
Chris Lattner08a4d5a2007-01-23 00:59:48 +0000543 SmallSet<unsigned, 8> &Rejected) {
Chris Lattner540fec62006-02-25 01:51:33 +0000544 if (Reuses.empty()) return PhysReg; // This is most often empty.
545
546 for (unsigned ro = 0, e = Reuses.size(); ro != e; ++ro) {
547 ReusedOp &Op = Reuses[ro];
548 // If we find some other reuse that was supposed to use this register
549 // exactly for its reload, we can change this reload to use ITS reload
Evan Cheng3c82cab2007-01-19 22:40:14 +0000550 // register. That is, unless its reload register has already been
551 // considered and subsequently rejected because it has also been reused
552 // by another operand.
553 if (Op.PhysRegReused == PhysReg &&
554 Rejected.count(Op.AssignedPhysReg) == 0) {
Chris Lattner540fec62006-02-25 01:51:33 +0000555 // Yup, use the reload register that we didn't use before.
Evan Cheng3c82cab2007-01-19 22:40:14 +0000556 unsigned NewReg = Op.AssignedPhysReg;
557 Rejected.insert(PhysReg);
558 return GetRegForReload(NewReg, MI, Spills, MaybeDeadStores, Rejected);
Chris Lattner540fec62006-02-25 01:51:33 +0000559 } else {
560 // Otherwise, we might also have a problem if a previously reused
561 // value aliases the new register. If so, codegen the previous reload
562 // and use this one.
563 unsigned PRRU = Op.PhysRegReused;
564 const MRegisterInfo *MRI = Spills.getRegInfo();
565 if (MRI->areAliases(PRRU, PhysReg)) {
566 // Okay, we found out that an alias of a reused register
567 // was used. This isn't good because it means we have
568 // to undo a previous reuse.
569 MachineBasicBlock *MBB = MI->getParent();
570 const TargetRegisterClass *AliasRC =
Chris Lattner28bad082006-02-25 02:17:31 +0000571 MBB->getParent()->getSSARegMap()->getRegClass(Op.VirtReg);
572
573 // Copy Op out of the vector and remove it, we're going to insert an
574 // explicit load for it.
575 ReusedOp NewOp = Op;
576 Reuses.erase(Reuses.begin()+ro);
577
578 // Ok, we're going to try to reload the assigned physreg into the
579 // slot that we were supposed to in the first place. However, that
580 // register could hold a reuse. Check to see if it conflicts or
581 // would prefer us to use a different register.
582 unsigned NewPhysReg = GetRegForReload(NewOp.AssignedPhysReg,
Evan Cheng3c82cab2007-01-19 22:40:14 +0000583 MI, Spills, MaybeDeadStores, Rejected);
Chris Lattner28bad082006-02-25 02:17:31 +0000584
585 MRI->loadRegFromStackSlot(*MBB, MI, NewPhysReg,
586 NewOp.StackSlot, AliasRC);
587 Spills.ClobberPhysReg(NewPhysReg);
588 Spills.ClobberPhysReg(NewOp.PhysRegReused);
Chris Lattner540fec62006-02-25 01:51:33 +0000589
590 // Any stores to this stack slot are not dead anymore.
Chris Lattner28bad082006-02-25 02:17:31 +0000591 MaybeDeadStores.erase(NewOp.StackSlot);
Chris Lattner540fec62006-02-25 01:51:33 +0000592
Chris Lattnere53f4a02006-05-04 17:52:23 +0000593 MI->getOperand(NewOp.Operand).setReg(NewPhysReg);
Chris Lattner540fec62006-02-25 01:51:33 +0000594
Evan Cheng91e23902007-02-23 01:13:26 +0000595 Spills.addAvailable(NewOp.StackSlot, MI, NewPhysReg);
Chris Lattner540fec62006-02-25 01:51:33 +0000596 ++NumLoads;
597 DEBUG(MachineBasicBlock::iterator MII = MI;
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000598 DOUT << '\t' << *prior(MII));
Chris Lattner540fec62006-02-25 01:51:33 +0000599
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000600 DOUT << "Reuse undone!\n";
Chris Lattner540fec62006-02-25 01:51:33 +0000601 --NumReused;
Chris Lattner28bad082006-02-25 02:17:31 +0000602
603 // Finally, PhysReg is now available, go ahead and use it.
Chris Lattner540fec62006-02-25 01:51:33 +0000604 return PhysReg;
605 }
606 }
607 }
608 return PhysReg;
609 }
Evan Cheng3c82cab2007-01-19 22:40:14 +0000610
611 /// GetRegForReload - Helper for the above GetRegForReload(). Add a
612 /// 'Rejected' set to remember which registers have been considered and
613 /// rejected for the reload. This avoids infinite looping in case like
614 /// this:
615 /// t1 := op t2, t3
616 /// t2 <- assigned r0 for use by the reload but ended up reuse r1
617 /// t3 <- assigned r1 for use by the reload but ended up reuse r0
618 /// t1 <- desires r1
619 /// sees r1 is taken by t2, tries t2's reload register r0
620 /// sees r0 is taken by t3, tries t3's reload register r1
621 /// sees r1 is taken by t2, tries t2's reload register r0 ...
622 unsigned GetRegForReload(unsigned PhysReg, MachineInstr *MI,
623 AvailableSpills &Spills,
624 std::map<int, MachineInstr*> &MaybeDeadStores) {
Chris Lattner08a4d5a2007-01-23 00:59:48 +0000625 SmallSet<unsigned, 8> Rejected;
Evan Cheng3c82cab2007-01-19 22:40:14 +0000626 return GetRegForReload(PhysReg, MI, Spills, MaybeDeadStores, Rejected);
627 }
Chris Lattner540fec62006-02-25 01:51:33 +0000628 };
Chris Lattner7fb64342004-10-01 19:04:51 +0000629}
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000630
Chris Lattner7fb64342004-10-01 19:04:51 +0000631
632/// rewriteMBB - Keep track of which spills are available even after the
633/// register allocator is done with them. If possible, avoid reloading vregs.
Evan Cheng2638e1a2007-03-20 08:13:50 +0000634void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM,
635 std::vector<MachineInstr*> &ReMatedMIs) {
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000636 DOUT << MBB.getBasicBlock()->getName() << ":\n";
Chris Lattner7fb64342004-10-01 19:04:51 +0000637
Chris Lattner66cf80f2006-02-03 23:13:58 +0000638 // Spills - Keep track of which spilled values are available in physregs so
639 // that we can choose to reuse the physregs instead of emitting reloads.
640 AvailableSpills Spills(MRI, TII);
641
Chris Lattner52b25db2004-10-01 19:47:12 +0000642 // MaybeDeadStores - When we need to write a value back into a stack slot,
643 // keep track of the inserted store. If the stack slot value is never read
644 // (because the value was used from some available register, for example), and
645 // subsequently stored to, the original store is dead. This map keeps track
646 // of inserted stores that are not used. If we see a subsequent store to the
647 // same stack slot, the original store is deleted.
648 std::map<int, MachineInstr*> MaybeDeadStores;
649
Evan Cheng6c087e52007-04-25 22:13:27 +0000650 MachineFunction &MF = *MBB.getParent();
Chris Lattner7fb64342004-10-01 19:04:51 +0000651 for (MachineBasicBlock::iterator MII = MBB.begin(), E = MBB.end();
652 MII != E; ) {
653 MachineInstr &MI = *MII;
654 MachineBasicBlock::iterator NextMII = MII; ++NextMII;
655
Chris Lattner540fec62006-02-25 01:51:33 +0000656 /// ReusedOperands - Keep track of operand reuse in case we need to undo
657 /// reuse.
Evan Chenge077ef62006-11-04 00:21:55 +0000658 ReuseInfo ReusedOperands(MI, MRI);
659
660 // Loop over all of the implicit defs, clearing them from our available
661 // sets.
Evan Cheng86facc22006-12-15 06:41:01 +0000662 const TargetInstrDescriptor *TID = MI.getInstrDescriptor();
Evan Cheng2638e1a2007-03-20 08:13:50 +0000663
664 // If this instruction is being rematerialized, just remove it!
Evan Cheng91935142007-04-04 07:40:01 +0000665 int FrameIdx;
666 if ((TID->Flags & M_REMATERIALIZIBLE) ||
Dan Gohmanc101e952007-06-14 20:50:44 +0000667 TII->isLoadFromStackSlot(&MI, FrameIdx) ||
668 TII->isOtherReMaterializableLoad(&MI)) {
Evan Cheng2638e1a2007-03-20 08:13:50 +0000669 bool Remove = true;
670 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
671 MachineOperand &MO = MI.getOperand(i);
672 if (!MO.isRegister() || MO.getReg() == 0)
673 continue; // Ignore non-register operands.
674 if (MO.isDef() && !VRM.isReMaterialized(MO.getReg())) {
675 Remove = false;
676 break;
677 }
678 }
679 if (Remove) {
680 VRM.RemoveFromFoldedVirtMap(&MI);
681 ReMatedMIs.push_back(MI.removeFromParent());
682 MII = NextMII;
683 continue;
684 }
685 }
686
Evan Cheng86facc22006-12-15 06:41:01 +0000687 const unsigned *ImpDef = TID->ImplicitDefs;
Evan Chenge077ef62006-11-04 00:21:55 +0000688 if (ImpDef) {
689 for ( ; *ImpDef; ++ImpDef) {
Evan Cheng6c087e52007-04-25 22:13:27 +0000690 MF.setPhysRegUsed(*ImpDef);
Evan Chenge077ef62006-11-04 00:21:55 +0000691 ReusedOperands.markClobbered(*ImpDef);
692 Spills.ClobberPhysReg(*ImpDef);
693 }
694 }
695
Chris Lattner7fb64342004-10-01 19:04:51 +0000696 // Process all of the spilled uses and all non spilled reg references.
697 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
698 MachineOperand &MO = MI.getOperand(i);
Chris Lattner50ea01e2005-09-09 20:29:51 +0000699 if (!MO.isRegister() || MO.getReg() == 0)
700 continue; // Ignore non-register operands.
701
702 if (MRegisterInfo::isPhysicalRegister(MO.getReg())) {
703 // Ignore physregs for spilling, but remember that it is used by this
704 // function.
Evan Cheng6c087e52007-04-25 22:13:27 +0000705 MF.setPhysRegUsed(MO.getReg());
Evan Chenge077ef62006-11-04 00:21:55 +0000706 ReusedOperands.markClobbered(MO.getReg());
Chris Lattner50ea01e2005-09-09 20:29:51 +0000707 continue;
708 }
709
710 assert(MRegisterInfo::isVirtualRegister(MO.getReg()) &&
711 "Not a virtual or a physical register?");
712
713 unsigned VirtReg = MO.getReg();
714 if (!VRM.hasStackSlot(VirtReg)) {
715 // This virtual register was assigned a physreg!
716 unsigned Phys = VRM.getPhys(VirtReg);
Evan Cheng6c087e52007-04-25 22:13:27 +0000717 MF.setPhysRegUsed(Phys);
Evan Chenge077ef62006-11-04 00:21:55 +0000718 if (MO.isDef())
719 ReusedOperands.markClobbered(Phys);
Chris Lattnere53f4a02006-05-04 17:52:23 +0000720 MI.getOperand(i).setReg(Phys);
Chris Lattner50ea01e2005-09-09 20:29:51 +0000721 continue;
722 }
723
724 // This virtual register is now known to be a spilled value.
725 if (!MO.isUse())
726 continue; // Handle defs in the loop below (handle use&def here though)
Chris Lattner7fb64342004-10-01 19:04:51 +0000727
Evan Cheng2638e1a2007-03-20 08:13:50 +0000728 bool doReMat = VRM.isReMaterialized(VirtReg);
Chris Lattner50ea01e2005-09-09 20:29:51 +0000729 int StackSlot = VRM.getStackSlot(VirtReg);
730 unsigned PhysReg;
Chris Lattner7fb64342004-10-01 19:04:51 +0000731
Chris Lattner50ea01e2005-09-09 20:29:51 +0000732 // Check to see if this stack slot is available.
Evan Cheng91e23902007-02-23 01:13:26 +0000733 MachineInstr *SSMI = NULL;
734 if ((PhysReg = Spills.getSpillSlotPhysReg(StackSlot, SSMI))) {
Chris Lattner29268692006-09-05 02:12:02 +0000735 // This spilled operand might be part of a two-address operand. If this
736 // is the case, then changing it will necessarily require changing the
737 // def part of the instruction as well. However, in some cases, we
738 // aren't allowed to modify the reused register. If none of these cases
739 // apply, reuse it.
740 bool CanReuse = true;
Evan Cheng86facc22006-12-15 06:41:01 +0000741 int ti = TID->getOperandConstraint(i, TOI::TIED_TO);
Evan Cheng360c2dd2006-11-01 23:06:55 +0000742 if (ti != -1 &&
743 MI.getOperand(ti).isReg() &&
744 MI.getOperand(ti).getReg() == VirtReg) {
Chris Lattner29268692006-09-05 02:12:02 +0000745 // Okay, we have a two address operand. We can reuse this physreg as
Evan Cheng3c82cab2007-01-19 22:40:14 +0000746 // long as we are allowed to clobber the value and there isn't an
747 // earlier def that has already clobbered the physreg.
Evan Chenge077ef62006-11-04 00:21:55 +0000748 CanReuse = Spills.canClobberPhysReg(StackSlot) &&
749 !ReusedOperands.isClobbered(PhysReg);
Chris Lattner29268692006-09-05 02:12:02 +0000750 }
751
752 if (CanReuse) {
Chris Lattneraddc55a2006-04-28 01:46:50 +0000753 // If this stack slot value is already available, reuse it!
Evan Cheng2638e1a2007-03-20 08:13:50 +0000754 if (StackSlot > VirtRegMap::MAX_STACK_SLOT)
755 DOUT << "Reusing RM#" << StackSlot-VirtRegMap::MAX_STACK_SLOT-1;
756 else
757 DOUT << "Reusing SS#" << StackSlot;
758 DOUT << " from physreg "
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000759 << MRI->getName(PhysReg) << " for vreg"
760 << VirtReg <<" instead of reloading into physreg "
761 << MRI->getName(VRM.getPhys(VirtReg)) << "\n";
Chris Lattnere53f4a02006-05-04 17:52:23 +0000762 MI.getOperand(i).setReg(PhysReg);
Chris Lattneraddc55a2006-04-28 01:46:50 +0000763
Evan Cheng91e23902007-02-23 01:13:26 +0000764 // Extend the live range of the MI that last kill the register if
765 // necessary.
Evan Chenga7288df2007-03-03 06:32:37 +0000766 bool WasKill = false;
Evan Cheng6b448092007-03-02 08:52:00 +0000767 if (SSMI) {
Evan Chengfaa51072007-04-26 19:00:32 +0000768 int UIdx = SSMI->findRegisterUseOperandIdx(PhysReg, true);
Evan Chengad7ccf32007-03-26 22:40:42 +0000769 if (UIdx != -1) {
770 MachineOperand &MOK = SSMI->getOperand(UIdx);
771 WasKill = MOK.isKill();
772 MOK.unsetIsKill();
Evan Chenga7288df2007-03-03 06:32:37 +0000773 }
Evan Cheng6b448092007-03-02 08:52:00 +0000774 }
775 if (ti == -1) {
776 // Unless it's the use of a two-address code, transfer the kill
777 // of the reused register to this use.
Evan Chenga7288df2007-03-03 06:32:37 +0000778 if (WasKill)
779 MI.getOperand(i).setIsKill();
Evan Cheng6b448092007-03-02 08:52:00 +0000780 Spills.addLastUse(PhysReg, &MI);
Evan Cheng50d25d72007-02-23 21:47:50 +0000781 }
Evan Cheng91e23902007-02-23 01:13:26 +0000782
Chris Lattneraddc55a2006-04-28 01:46:50 +0000783 // The only technical detail we have is that we don't know that
784 // PhysReg won't be clobbered by a reloaded stack slot that occurs
785 // later in the instruction. In particular, consider 'op V1, V2'.
786 // If V1 is available in physreg R0, we would choose to reuse it
787 // here, instead of reloading it into the register the allocator
788 // indicated (say R1). However, V2 might have to be reloaded
789 // later, and it might indicate that it needs to live in R0. When
790 // this occurs, we need to have information available that
791 // indicates it is safe to use R1 for the reload instead of R0.
792 //
793 // To further complicate matters, we might conflict with an alias,
794 // or R0 and R1 might not be compatible with each other. In this
795 // case, we actually insert a reload for V1 in R1, ensuring that
796 // we can get at R0 or its alias.
797 ReusedOperands.addReuse(i, StackSlot, PhysReg,
798 VRM.getPhys(VirtReg), VirtReg);
Evan Chenge077ef62006-11-04 00:21:55 +0000799 if (ti != -1)
800 // Only mark it clobbered if this is a use&def operand.
801 ReusedOperands.markClobbered(PhysReg);
Chris Lattneraddc55a2006-04-28 01:46:50 +0000802 ++NumReused;
803 continue;
804 }
805
806 // Otherwise we have a situation where we have a two-address instruction
807 // whose mod/ref operand needs to be reloaded. This reload is already
808 // available in some register "PhysReg", but if we used PhysReg as the
809 // operand to our 2-addr instruction, the instruction would modify
810 // PhysReg. This isn't cool if something later uses PhysReg and expects
811 // to get its initial value.
Chris Lattner50ea01e2005-09-09 20:29:51 +0000812 //
Chris Lattneraddc55a2006-04-28 01:46:50 +0000813 // To avoid this problem, and to avoid doing a load right after a store,
814 // we emit a copy from PhysReg into the designated register for this
815 // operand.
816 unsigned DesignatedReg = VRM.getPhys(VirtReg);
817 assert(DesignatedReg && "Must map virtreg to physreg!");
818
819 // Note that, if we reused a register for a previous operand, the
820 // register we want to reload into might not actually be
821 // available. If this occurs, use the register indicated by the
822 // reuser.
823 if (ReusedOperands.hasReuses())
824 DesignatedReg = ReusedOperands.GetRegForReload(DesignatedReg, &MI,
825 Spills, MaybeDeadStores);
826
Chris Lattnerba1fc3d2006-04-28 04:43:18 +0000827 // If the mapped designated register is actually the physreg we have
828 // incoming, we don't need to inserted a dead copy.
829 if (DesignatedReg == PhysReg) {
830 // If this stack slot value is already available, reuse it!
Evan Cheng2638e1a2007-03-20 08:13:50 +0000831 if (StackSlot > VirtRegMap::MAX_STACK_SLOT)
832 DOUT << "Reusing RM#" << StackSlot-VirtRegMap::MAX_STACK_SLOT-1;
833 else
834 DOUT << "Reusing SS#" << StackSlot;
835 DOUT << " from physreg " << MRI->getName(PhysReg) << " for vreg"
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000836 << VirtReg
837 << " instead of reloading into same physreg.\n";
Chris Lattnere53f4a02006-05-04 17:52:23 +0000838 MI.getOperand(i).setReg(PhysReg);
Evan Chenge077ef62006-11-04 00:21:55 +0000839 ReusedOperands.markClobbered(PhysReg);
Chris Lattnerba1fc3d2006-04-28 04:43:18 +0000840 ++NumReused;
841 continue;
842 }
843
Evan Cheng6c087e52007-04-25 22:13:27 +0000844 const TargetRegisterClass* RC = MF.getSSARegMap()->getRegClass(VirtReg);
845 MF.setPhysRegUsed(DesignatedReg);
Evan Chenge077ef62006-11-04 00:21:55 +0000846 ReusedOperands.markClobbered(DesignatedReg);
Chris Lattneraddc55a2006-04-28 01:46:50 +0000847 MRI->copyRegToReg(MBB, &MI, DesignatedReg, PhysReg, RC);
Evan Chengde4e9422007-02-25 09:51:27 +0000848
849 // Extend the live range of the MI that last kill the register if
850 // necessary.
Evan Chenga7288df2007-03-03 06:32:37 +0000851 bool WasKill = false;
Evan Chengde4e9422007-02-25 09:51:27 +0000852 if (SSMI) {
Evan Chengfaa51072007-04-26 19:00:32 +0000853 int UIdx = SSMI->findRegisterUseOperandIdx(PhysReg, true);
Evan Chengad7ccf32007-03-26 22:40:42 +0000854 if (UIdx != -1) {
855 MachineOperand &MOK = SSMI->getOperand(UIdx);
856 WasKill = MOK.isKill();
857 MOK.unsetIsKill();
Evan Chenga7288df2007-03-03 06:32:37 +0000858 }
Evan Chengde4e9422007-02-25 09:51:27 +0000859 }
Evan Cheng6b448092007-03-02 08:52:00 +0000860 MachineInstr *CopyMI = prior(MII);
Evan Chenga7288df2007-03-03 06:32:37 +0000861 if (WasKill) {
862 // Transfer kill to the next use.
Evan Chengfaa51072007-04-26 19:00:32 +0000863 int UIdx = CopyMI->findRegisterUseOperandIdx(PhysReg);
Evan Chengad7ccf32007-03-26 22:40:42 +0000864 assert(UIdx != -1);
865 MachineOperand &MOU = CopyMI->getOperand(UIdx);
866 MOU.setIsKill();
Evan Chenga7288df2007-03-03 06:32:37 +0000867 }
868 Spills.addLastUse(PhysReg, CopyMI);
Evan Chengde4e9422007-02-25 09:51:27 +0000869
Chris Lattneraddc55a2006-04-28 01:46:50 +0000870 // This invalidates DesignatedReg.
871 Spills.ClobberPhysReg(DesignatedReg);
872
Evan Cheng91e23902007-02-23 01:13:26 +0000873 Spills.addAvailable(StackSlot, &MI, DesignatedReg);
Chris Lattnere53f4a02006-05-04 17:52:23 +0000874 MI.getOperand(i).setReg(DesignatedReg);
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000875 DOUT << '\t' << *prior(MII);
Chris Lattner50ea01e2005-09-09 20:29:51 +0000876 ++NumReused;
877 continue;
878 }
879
880 // Otherwise, reload it and remember that we have it.
881 PhysReg = VRM.getPhys(VirtReg);
Chris Lattner172c3622006-01-04 06:47:48 +0000882 assert(PhysReg && "Must map virtreg to physreg!");
Evan Cheng6c087e52007-04-25 22:13:27 +0000883 const TargetRegisterClass* RC = MF.getSSARegMap()->getRegClass(VirtReg);
Chris Lattner7fb64342004-10-01 19:04:51 +0000884
Chris Lattner50ea01e2005-09-09 20:29:51 +0000885 // Note that, if we reused a register for a previous operand, the
886 // register we want to reload into might not actually be
887 // available. If this occurs, use the register indicated by the
888 // reuser.
Chris Lattner540fec62006-02-25 01:51:33 +0000889 if (ReusedOperands.hasReuses())
890 PhysReg = ReusedOperands.GetRegForReload(PhysReg, &MI,
891 Spills, MaybeDeadStores);
892
Evan Cheng6c087e52007-04-25 22:13:27 +0000893 MF.setPhysRegUsed(PhysReg);
Evan Chenge077ef62006-11-04 00:21:55 +0000894 ReusedOperands.markClobbered(PhysReg);
Evan Cheng91935142007-04-04 07:40:01 +0000895 if (doReMat) {
Evan Cheng2638e1a2007-03-20 08:13:50 +0000896 MRI->reMaterialize(MBB, &MI, PhysReg, VRM.getReMaterializedMI(VirtReg));
Evan Cheng91935142007-04-04 07:40:01 +0000897 ++NumReMats;
898 } else {
Evan Cheng2638e1a2007-03-20 08:13:50 +0000899 MRI->loadRegFromStackSlot(MBB, &MI, PhysReg, StackSlot, RC);
Evan Cheng91935142007-04-04 07:40:01 +0000900 ++NumLoads;
901 }
Chris Lattner50ea01e2005-09-09 20:29:51 +0000902 // This invalidates PhysReg.
Chris Lattner66cf80f2006-02-03 23:13:58 +0000903 Spills.ClobberPhysReg(PhysReg);
Chris Lattner50ea01e2005-09-09 20:29:51 +0000904
905 // Any stores to this stack slot are not dead anymore.
Evan Cheng2638e1a2007-03-20 08:13:50 +0000906 if (!doReMat)
907 MaybeDeadStores.erase(StackSlot);
Evan Cheng91e23902007-02-23 01:13:26 +0000908 Spills.addAvailable(StackSlot, &MI, PhysReg);
Evan Chengde4e9422007-02-25 09:51:27 +0000909 // Assumes this is the last use. IsKill will be unset if reg is reused
910 // unless it's a two-address operand.
911 if (TID->getOperandConstraint(i, TOI::TIED_TO) == -1)
912 MI.getOperand(i).setIsKill();
Chris Lattnere53f4a02006-05-04 17:52:23 +0000913 MI.getOperand(i).setReg(PhysReg);
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000914 DOUT << '\t' << *prior(MII);
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000915 }
916
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000917 DOUT << '\t' << MI;
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000918
Chris Lattner7fb64342004-10-01 19:04:51 +0000919 // If we have folded references to memory operands, make sure we clear all
920 // physical registers that may contain the value of the spilled virtual
921 // register
Chris Lattner8f1d6402005-01-14 15:54:24 +0000922 VirtRegMap::MI2VirtMapTy::const_iterator I, End;
923 for (tie(I, End) = VRM.getFoldedVirts(&MI); I != End; ++I) {
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000924 DOUT << "Folded vreg: " << I->second.first << " MR: "
925 << I->second.second;
Chris Lattnerbec6a9e2004-10-01 23:15:36 +0000926 unsigned VirtReg = I->second.first;
927 VirtRegMap::ModRef MR = I->second.second;
Chris Lattnercea86882005-09-19 06:56:21 +0000928 if (!VRM.hasStackSlot(VirtReg)) {
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000929 DOUT << ": No stack slot!\n";
Chris Lattnercea86882005-09-19 06:56:21 +0000930 continue;
931 }
932 int SS = VRM.getStackSlot(VirtReg);
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000933 DOUT << " - StackSlot: " << SS << "\n";
Chris Lattnercea86882005-09-19 06:56:21 +0000934
935 // If this folded instruction is just a use, check to see if it's a
936 // straight load from the virt reg slot.
937 if ((MR & VirtRegMap::isRef) && !(MR & VirtRegMap::isMod)) {
938 int FrameIdx;
Chris Lattner40839602006-02-02 20:12:32 +0000939 if (unsigned DestReg = TII->isLoadFromStackSlot(&MI, FrameIdx)) {
Chris Lattner6ec36262006-10-12 17:45:38 +0000940 if (FrameIdx == SS) {
941 // If this spill slot is available, turn it into a copy (or nothing)
942 // instead of leaving it as a load!
Evan Chengde4e9422007-02-25 09:51:27 +0000943 MachineInstr *SSMI = NULL;
944 if (unsigned InReg = Spills.getSpillSlotPhysReg(SS, SSMI)) {
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000945 DOUT << "Promoted Load To Copy: " << MI;
Chris Lattner6ec36262006-10-12 17:45:38 +0000946 if (DestReg != InReg) {
947 MRI->copyRegToReg(MBB, &MI, DestReg, InReg,
948 MF.getSSARegMap()->getRegClass(VirtReg));
949 // Revisit the copy so we make sure to notice the effects of the
950 // operation on the destreg (either needing to RA it if it's
951 // virtual or needing to clobber any values if it's physical).
952 NextMII = &MI;
953 --NextMII; // backtrack to the copy.
Evan Chengde4e9422007-02-25 09:51:27 +0000954 } else
955 DOUT << "Removing now-noop copy: " << MI;
956
Evan Chengc0ba1bc2007-03-01 02:27:30 +0000957 // Either way, the live range of the last kill of InReg has been
958 // extended. Remove its kill.
Evan Chenga7288df2007-03-03 06:32:37 +0000959 bool WasKill = false;
Evan Cheng6b448092007-03-02 08:52:00 +0000960 if (SSMI) {
Evan Chengfaa51072007-04-26 19:00:32 +0000961 int UIdx = SSMI->findRegisterUseOperandIdx(InReg, true);
Evan Chengad7ccf32007-03-26 22:40:42 +0000962 if (UIdx != -1) {
963 MachineOperand &MOK = SSMI->getOperand(UIdx);
964 WasKill = MOK.isKill();
965 MOK.unsetIsKill();
Evan Chenga7288df2007-03-03 06:32:37 +0000966 }
Evan Cheng6b448092007-03-02 08:52:00 +0000967 }
968 if (NextMII != MBB.end()) {
Evan Chengad7ccf32007-03-26 22:40:42 +0000969 // If NextMII uses InReg and the use is not a two address
970 // operand, mark it killed.
Evan Chengfaa51072007-04-26 19:00:32 +0000971 int UIdx = NextMII->findRegisterUseOperandIdx(InReg);
Evan Chengad7ccf32007-03-26 22:40:42 +0000972 if (UIdx != -1) {
973 MachineOperand &MOU = NextMII->getOperand(UIdx);
974 if (WasKill) {
975 const TargetInstrDescriptor *NTID =
976 NextMII->getInstrDescriptor();
Evan Cheng018d6e12007-03-27 00:48:28 +0000977 if (UIdx >= NTID->numOperands ||
978 NTID->getOperandConstraint(UIdx, TOI::TIED_TO) == -1)
Evan Chengad7ccf32007-03-26 22:40:42 +0000979 MOU.setIsKill();
980 }
Evan Cheng6b448092007-03-02 08:52:00 +0000981 Spills.addLastUse(InReg, &(*NextMII));
Evan Chengde4e9422007-02-25 09:51:27 +0000982 }
Chris Lattner6ec36262006-10-12 17:45:38 +0000983 }
Evan Chengde4e9422007-02-25 09:51:27 +0000984
Chris Lattner6ec36262006-10-12 17:45:38 +0000985 VRM.RemoveFromFoldedVirtMap(&MI);
986 MBB.erase(&MI);
987 goto ProcessNextInst;
Chris Lattnercea86882005-09-19 06:56:21 +0000988 }
Chris Lattnercea86882005-09-19 06:56:21 +0000989 }
990 }
991 }
992
993 // If this reference is not a use, any previous store is now dead.
994 // Otherwise, the store to this stack slot is not dead anymore.
995 std::map<int, MachineInstr*>::iterator MDSI = MaybeDeadStores.find(SS);
996 if (MDSI != MaybeDeadStores.end()) {
997 if (MR & VirtRegMap::isRef) // Previous store is not dead.
998 MaybeDeadStores.erase(MDSI);
999 else {
1000 // If we get here, the store is dead, nuke it now.
Chris Lattner35f27052006-05-01 21:16:03 +00001001 assert(VirtRegMap::isMod && "Can't be modref!");
Bill Wendlingb2b9c202006-11-17 02:09:07 +00001002 DOUT << "Removed dead store:\t" << *MDSI->second;
Chris Lattner35f27052006-05-01 21:16:03 +00001003 MBB.erase(MDSI->second);
Chris Lattner229924a2006-05-01 22:03:24 +00001004 VRM.RemoveFromFoldedVirtMap(MDSI->second);
Chris Lattner35f27052006-05-01 21:16:03 +00001005 MaybeDeadStores.erase(MDSI);
1006 ++NumDSE;
Chris Lattnercea86882005-09-19 06:56:21 +00001007 }
1008 }
1009
1010 // If the spill slot value is available, and this is a new definition of
1011 // the value, the value is not available anymore.
1012 if (MR & VirtRegMap::isMod) {
Chris Lattner07cf1412006-02-03 00:36:31 +00001013 // Notice that the value in this stack slot has been modified.
Chris Lattner66cf80f2006-02-03 23:13:58 +00001014 Spills.ModifyStackSlot(SS);
Chris Lattnercd816392006-02-02 23:29:36 +00001015
1016 // If this is *just* a mod of the value, check to see if this is just a
1017 // store to the spill slot (i.e. the spill got merged into the copy). If
1018 // so, realize that the vreg is available now, and add the store to the
1019 // MaybeDeadStore info.
1020 int StackSlot;
1021 if (!(MR & VirtRegMap::isRef)) {
1022 if (unsigned SrcReg = TII->isStoreToStackSlot(&MI, StackSlot)) {
1023 assert(MRegisterInfo::isPhysicalRegister(SrcReg) &&
1024 "Src hasn't been allocated yet?");
Chris Lattner07cf1412006-02-03 00:36:31 +00001025 // Okay, this is certainly a store of SrcReg to [StackSlot]. Mark
Chris Lattnercd816392006-02-02 23:29:36 +00001026 // this as a potentially dead store in case there is a subsequent
1027 // store into the stack slot without a read from it.
1028 MaybeDeadStores[StackSlot] = &MI;
1029
Chris Lattnercd816392006-02-02 23:29:36 +00001030 // If the stack slot value was previously available in some other
1031 // register, change it now. Otherwise, make the register available,
1032 // in PhysReg.
Evan Cheng91e23902007-02-23 01:13:26 +00001033 Spills.addAvailable(StackSlot, &MI, SrcReg, false/*don't clobber*/);
Chris Lattnercd816392006-02-02 23:29:36 +00001034 }
1035 }
Chris Lattner7fb64342004-10-01 19:04:51 +00001036 }
Chris Lattner8c4d88d2004-09-30 01:54:45 +00001037 }
1038
Chris Lattner7fb64342004-10-01 19:04:51 +00001039 // Process all of the spilled defs.
1040 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
1041 MachineOperand &MO = MI.getOperand(i);
1042 if (MO.isRegister() && MO.getReg() && MO.isDef()) {
1043 unsigned VirtReg = MO.getReg();
Chris Lattner8c4d88d2004-09-30 01:54:45 +00001044
Chris Lattner7fb64342004-10-01 19:04:51 +00001045 if (!MRegisterInfo::isVirtualRegister(VirtReg)) {
Chris Lattner29268692006-09-05 02:12:02 +00001046 // Check to see if this is a noop copy. If so, eliminate the
1047 // instruction before considering the dest reg to be changed.
1048 unsigned Src, Dst;
1049 if (TII->isMoveInstr(MI, Src, Dst) && Src == Dst) {
1050 ++NumDCE;
Bill Wendlingb2b9c202006-11-17 02:09:07 +00001051 DOUT << "Removing now-noop copy: " << MI;
Evan Cheng6b448092007-03-02 08:52:00 +00001052 Spills.removeLastUse(Src, &MI);
Chris Lattner29268692006-09-05 02:12:02 +00001053 MBB.erase(&MI);
1054 VRM.RemoveFromFoldedVirtMap(&MI);
Evan Cheng7a0d51c2006-12-14 07:54:05 +00001055 Spills.disallowClobberPhysReg(VirtReg);
Chris Lattner29268692006-09-05 02:12:02 +00001056 goto ProcessNextInst;
Chris Lattner7fb64342004-10-01 19:04:51 +00001057 }
Chris Lattner6ec36262006-10-12 17:45:38 +00001058
1059 // If it's not a no-op copy, it clobbers the value in the destreg.
Chris Lattner29268692006-09-05 02:12:02 +00001060 Spills.ClobberPhysReg(VirtReg);
Evan Chenge077ef62006-11-04 00:21:55 +00001061 ReusedOperands.markClobbered(VirtReg);
Chris Lattner6ec36262006-10-12 17:45:38 +00001062
1063 // Check to see if this instruction is a load from a stack slot into
1064 // a register. If so, this provides the stack slot value in the reg.
1065 int FrameIdx;
1066 if (unsigned DestReg = TII->isLoadFromStackSlot(&MI, FrameIdx)) {
1067 assert(DestReg == VirtReg && "Unknown load situation!");
1068
1069 // Otherwise, if it wasn't available, remember that it is now!
Evan Cheng91e23902007-02-23 01:13:26 +00001070 Spills.addAvailable(FrameIdx, &MI, DestReg);
Chris Lattner6ec36262006-10-12 17:45:38 +00001071 goto ProcessNextInst;
1072 }
1073
Chris Lattner29268692006-09-05 02:12:02 +00001074 continue;
Misha Brukmanedf128a2005-04-21 22:36:52 +00001075 }
Chris Lattner7fb64342004-10-01 19:04:51 +00001076
Chris Lattner84e752a2006-02-03 03:06:49 +00001077 // The only vregs left are stack slot definitions.
1078 int StackSlot = VRM.getStackSlot(VirtReg);
Evan Cheng6c087e52007-04-25 22:13:27 +00001079 const TargetRegisterClass *RC = MF.getSSARegMap()->getRegClass(VirtReg);
Chris Lattner7fb64342004-10-01 19:04:51 +00001080
Chris Lattner29268692006-09-05 02:12:02 +00001081 // If this def is part of a two-address operand, make sure to execute
1082 // the store from the correct physical register.
1083 unsigned PhysReg;
Evan Chengcc22a7a2006-12-08 18:45:48 +00001084 int TiedOp = MI.getInstrDescriptor()->findTiedToSrcOperand(i);
Evan Cheng360c2dd2006-11-01 23:06:55 +00001085 if (TiedOp != -1)
1086 PhysReg = MI.getOperand(TiedOp).getReg();
Evan Chenge077ef62006-11-04 00:21:55 +00001087 else {
Chris Lattner29268692006-09-05 02:12:02 +00001088 PhysReg = VRM.getPhys(VirtReg);
Evan Chenge077ef62006-11-04 00:21:55 +00001089 if (ReusedOperands.isClobbered(PhysReg)) {
1090 // Another def has taken the assigned physreg. It must have been a
1091 // use&def which got it due to reuse. Undo the reuse!
1092 PhysReg = ReusedOperands.GetRegForReload(PhysReg, &MI,
1093 Spills, MaybeDeadStores);
1094 }
1095 }
Chris Lattner7fb64342004-10-01 19:04:51 +00001096
Evan Cheng6c087e52007-04-25 22:13:27 +00001097 MF.setPhysRegUsed(PhysReg);
Evan Chenge077ef62006-11-04 00:21:55 +00001098 ReusedOperands.markClobbered(PhysReg);
Chris Lattner84e752a2006-02-03 03:06:49 +00001099 MRI->storeRegToStackSlot(MBB, next(MII), PhysReg, StackSlot, RC);
Bill Wendlingb2b9c202006-11-17 02:09:07 +00001100 DOUT << "Store:\t" << *next(MII);
Chris Lattnere53f4a02006-05-04 17:52:23 +00001101 MI.getOperand(i).setReg(PhysReg);
Chris Lattner7fb64342004-10-01 19:04:51 +00001102
Chris Lattner84e752a2006-02-03 03:06:49 +00001103 // If there is a dead store to this stack slot, nuke it now.
1104 MachineInstr *&LastStore = MaybeDeadStores[StackSlot];
1105 if (LastStore) {
Bill Wendlingb2b9c202006-11-17 02:09:07 +00001106 DOUT << "Removed dead store:\t" << *LastStore;
Chris Lattner84e752a2006-02-03 03:06:49 +00001107 ++NumDSE;
1108 MBB.erase(LastStore);
Chris Lattner229924a2006-05-01 22:03:24 +00001109 VRM.RemoveFromFoldedVirtMap(LastStore);
Chris Lattner7fb64342004-10-01 19:04:51 +00001110 }
Chris Lattner84e752a2006-02-03 03:06:49 +00001111 LastStore = next(MII);
1112
1113 // If the stack slot value was previously available in some other
1114 // register, change it now. Otherwise, make the register available,
1115 // in PhysReg.
Chris Lattner66cf80f2006-02-03 23:13:58 +00001116 Spills.ModifyStackSlot(StackSlot);
1117 Spills.ClobberPhysReg(PhysReg);
Evan Cheng91e23902007-02-23 01:13:26 +00001118 Spills.addAvailable(StackSlot, LastStore, PhysReg);
Chris Lattner84e752a2006-02-03 03:06:49 +00001119 ++NumStores;
Evan Chengf50d09a2007-02-08 06:04:54 +00001120
1121 // Check to see if this is a noop copy. If so, eliminate the
1122 // instruction before considering the dest reg to be changed.
1123 {
1124 unsigned Src, Dst;
1125 if (TII->isMoveInstr(MI, Src, Dst) && Src == Dst) {
1126 ++NumDCE;
1127 DOUT << "Removing now-noop copy: " << MI;
Evan Cheng7cb33c82007-03-30 20:21:35 +00001128 Spills.removeLastUse(Src, &MI);
Evan Chengf50d09a2007-02-08 06:04:54 +00001129 MBB.erase(&MI);
1130 VRM.RemoveFromFoldedVirtMap(&MI);
1131 goto ProcessNextInst;
1132 }
1133 }
Chris Lattner7fb64342004-10-01 19:04:51 +00001134 }
1135 }
Chris Lattnercea86882005-09-19 06:56:21 +00001136 ProcessNextInst:
Chris Lattner7fb64342004-10-01 19:04:51 +00001137 MII = NextMII;
1138 }
Chris Lattner8c4d88d2004-09-30 01:54:45 +00001139}
1140
Chris Lattnerf7da2c72006-08-24 22:43:55 +00001141
1142
Chris Lattner8c4d88d2004-09-30 01:54:45 +00001143llvm::Spiller* llvm::createSpiller() {
1144 switch (SpillerOpt) {
1145 default: assert(0 && "Unreachable!");
1146 case local:
1147 return new LocalSpiller();
1148 case simple:
1149 return new SimpleSpiller();
1150 }
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +00001151}