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gerrit-public.fairphone.software / fp2-dev / platform / external / llvm / ec7f4231cb7c26d5f52375617a9a73a1e79f3857 / . / test / CodeGen / PowerPC / crsave.ll
blob: f1cbc5afa8acf6763fa9873e41740c23915976b7 [file] [log] [blame]
Roman Divacky9d760ae2012-09-12 14:47:47 +0000[diff] [blame]1; RUN: llc -O0 -disable-fp-elim -mtriple=powerpc-unknown-linux-gnu < %s | FileCheck %s -check-prefix=PPC32
Hal Finkelb99c9952013-04-13 08:09:20 +0000[diff] [blame]2; RUN: llc -O0 -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck %s -check-prefix=PPC64
Roman Divacky9d760ae2012-09-12 14:47:47 +0000[diff] [blame]3
4declare void @foo()
5
6define i32 @test_cr2() nounwind {
7entry:
8 %ret = alloca i32, align 4
9 %0 = call i32 asm sideeffect "\0A\09mtcr $4\0A\09cmp 2,$2,$1\0A\09mfcr $0", "=r,r,r,r,r,~{cr2}"(i32 1, i32 2, i32 3, i32 0) nounwind
10 store i32 %0, i32* %ret, align 4
11 call void @foo()
12 %1 = load i32* %ret, align 4
13 ret i32 %1
14}
15
Bill Schmidtded53bf2013-05-14 16:08:32 +0000[diff] [blame]16; PPC32: stw 31, -4(1)
17; PPC32: stwu 1, -32(1)
Roman Divacky9d760ae2012-09-12 14:47:47 +0000[diff] [blame]18; PPC32: mfcr 12
Bill Schmidtded53bf2013-05-14 16:08:32 +0000[diff] [blame]19; PPC32-NEXT: stw 12, 24(31)
20; PPC32: lwz 12, 24(31)
Roman Divacky9d760ae2012-09-12 14:47:47 +0000[diff] [blame]21; PPC32-NEXT: mtcrf 32, 12
22
23; PPC64: mfcr 12
Hal Finkelfb6fe0a2013-04-15 02:07:05 +0000[diff] [blame]24; PPC64: stw 12, 8(1)
25; PPC64: stdu 1, -[[AMT:[0-9]+]](1)
26; PPC64: addi 1, 1, [[AMT]]
Roman Divacky9d760ae2012-09-12 14:47:47 +0000[diff] [blame]27; PPC64: lwz 12, 8(1)
Hal Finkelfb6fe0a2013-04-15 02:07:05 +0000[diff] [blame]28; PPC64: mtcrf 32, 12
Hal Finkelb99c9952013-04-13 08:09:20 +0000[diff] [blame]29
Roman Divacky9d760ae2012-09-12 14:47:47 +0000[diff] [blame]30define i32 @test_cr234() nounwind {
31entry:
32 %ret = alloca i32, align 4
33 %0 = call i32 asm sideeffect "\0A\09mtcr $4\0A\09cmp 2,$2,$1\0A\09cmp 3,$2,$2\0A\09cmp 4,$2,$3\0A\09mfcr $0", "=r,r,r,r,r,~{cr2},~{cr3},~{cr4}"(i32 1, i32 2, i32 3, i32 0) nounwind
34 store i32 %0, i32* %ret, align 4
35 call void @foo()
36 %1 = load i32* %ret, align 4
37 ret i32 %1
38}
39
Bill Schmidtded53bf2013-05-14 16:08:32 +0000[diff] [blame]40; PPC32: stw 31, -4(1)
41; PPC32: stwu 1, -32(1)
Roman Divacky9d760ae2012-09-12 14:47:47 +0000[diff] [blame]42; PPC32: mfcr 12
Bill Schmidtded53bf2013-05-14 16:08:32 +0000[diff] [blame]43; PPC32-NEXT: stw 12, 24(31)
44; PPC32: lwz 12, 24(31)
Roman Divacky9d760ae2012-09-12 14:47:47 +0000[diff] [blame]45; PPC32-NEXT: mtcrf 32, 12
46; PPC32-NEXT: mtcrf 16, 12
47; PPC32-NEXT: mtcrf 8, 12
48
49; PPC64: mfcr 12
Hal Finkelfb6fe0a2013-04-15 02:07:05 +0000[diff] [blame]50; PPC64: stw 12, 8(1)
51; PPC64: stdu 1, -[[AMT:[0-9]+]](1)
52; PPC64: addi 1, 1, [[AMT]]
Roman Divacky9d760ae2012-09-12 14:47:47 +0000[diff] [blame]53; PPC64: lwz 12, 8(1)
Hal Finkelfb6fe0a2013-04-15 02:07:05 +0000[diff] [blame]54; PPC64: mtcrf 32, 12
55; PPC64: mtcrf 16, 12
56; PPC64: mtcrf 8, 12
Hal Finkelb99c9952013-04-13 08:09:20 +0000[diff] [blame]57