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gerrit-public.fairphone.software / fp2-dev / platform / external / llvm / f048bfd97dd2ccef7dc5d86cd02a8ed65a63e2bd / . / lib / Target / SparcV9 / SparcV9Instr.def
blob: f3ed337d6e97fd7cb9032d99886ab99fee1f0c94 [file] [log] [blame]
Chris Lattner9a3d63b2001-09-19 15:56:23 +0000[diff] [blame]1//===-- SparcInstr.def - Sparc Instruction Information -----------*- C++ -*-==//
John Criswell856ba762003-10-21 15:17:13 +0000[diff] [blame]2//
3// The LLVM Compiler Infrastructure
4//
5// This file was developed by the LLVM research group and is distributed under
6// the University of Illinois Open Source License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
Chris Lattner9a3d63b2001-09-19 15:56:23 +0000[diff] [blame]9//
10// This file describes all of the instructions that the sparc backend uses. It
11// relys on an external 'I' macro being defined that takes the arguments
Chris Lattner232c3be2002-10-25 01:43:26 +0000[diff] [blame]12// specified below, and is used to make all of the information relevant to an
Chris Lattner9a3d63b2001-09-19 15:56:23 +0000[diff] [blame]13// instruction be in one place.
14//
15//===----------------------------------------------------------------------===//
16
17// NOTE: No include guards desired
18
19#ifndef I
20#errror "Must define I macro before including SparcInstr.def!"
21#endif
22
23// Constants for defining the maximum constant size field.
24// One #define per bit size
25//
26#define B5 ((1 << 5) - 1)
27#define B6 ((1 << 6) - 1)
28#define B12 ((1 << 12) - 1)
29#define B15 ((1 << 15) - 1)
30#define B18 ((1 << 18) - 1)
31#define B21 ((1 << 21) - 1)
32#define B22 ((1 << 22) - 1)
33#define B29 ((1 << 29) - 1)
34
35// Arguments passed into the I macro
36// enum name,
37// opCodeString,
38// numOperands,
39// resultPosition (0-based; -1 if no result),
40// maxImmedConst,
41// immedIsSignExtended,
42// numDelaySlots (in cycles)
43// latency (in cycles)
44// instr sched class (defined above)
Chris Lattner3501fea2003-01-14 22:00:31 +0000[diff] [blame]45// instr class flags (defined in TargetInstrInfo.h)
Chris Lattner9a3d63b2001-09-19 15:56:23 +0000[diff] [blame]46
47
Ruchira Sasanka3839e6e2001-11-03 19:59:59 +0000[diff] [blame]48
Vikram S. Adve6e64ef42001-09-30 23:46:57 +0000[diff] [blame]49I(NOP, "nop", 0, -1, 0, false, 0, 1, SPARC_NONE, M_NOP_FLAG)
Vikram S. Adve585612e2002-03-24 03:33:53 +0000[diff] [blame]50
Chris Lattner9a3d63b2001-09-19 15:56:23 +0000[diff] [blame]51// Synthetic SPARC assembly opcodes for setting a register to a constant.
52// Max immediate constant should be ignored for both these instructions.
Vikram S. Adve6e64ef42001-09-30 23:46:57 +0000[diff] [blame]53// Use a latency > 1 since this may generate as many as 3 instructions.
Chris Lattner07559122004-02-29 05:58:30 +0000[diff] [blame]54I(SETSW, "setsw", 2, 1, 0, true , 0, 2, SPARC_IEUN, M_PSEUDO_FLAG )
55I(SETUW, "setuw", 2, 1, 0, false, 0, 2, SPARC_IEUN, M_PSEUDO_FLAG )
56I(SETX, "setx", 3, 2, 0, true, 0, 2, SPARC_IEUN, M_PSEUDO_FLAG )
Chris Lattner9a3d63b2001-09-19 15:56:23 +0000[diff] [blame]57
58// Set high-order bits of register and clear low-order bits
Chris Lattner07559122004-02-29 05:58:30 +0000[diff] [blame]59I(SETHI, "sethi", 2, 1, B22, false, 0, 1, SPARC_IEUN, 0)
Vikram S. Adve6e64ef42001-09-30 23:46:57 +0000[diff] [blame]60
Chris Lattner9a3d63b2001-09-19 15:56:23 +0000[diff] [blame]61// Add or add with carry.
Chris Lattner07559122004-02-29 05:58:30 +0000[diff] [blame]62I(ADDr , "add", 3, 2, B12, true , 0, 1, SPARC_IEUN, 0)
63I(ADDi , "add", 3, 2, B12, true , 0, 1, SPARC_IEUN, 0)
64I(ADDccr, "addcc", 4, 2, B12, true , 0, 1, SPARC_IEU1, M_CC_FLAG )
65I(ADDcci, "addcc", 4, 2, B12, true , 0, 1, SPARC_IEU1, M_CC_FLAG )
66I(ADDCr , "addc", 3, 2, B12, true , 0, 1, SPARC_IEUN, 0)
67I(ADDCi , "addc", 3, 2, B12, true , 0, 1, SPARC_IEUN, 0)
68I(ADDCccr, "addccc", 4, 2, B12, true , 0, 1, SPARC_IEU1, M_CC_FLAG )
69I(ADDCcci, "addccc", 4, 2, B12, true , 0, 1, SPARC_IEU1, M_CC_FLAG )
Chris Lattner9a3d63b2001-09-19 15:56:23 +0000[diff] [blame]70
71// Subtract or subtract with carry.
Chris Lattner07559122004-02-29 05:58:30 +0000[diff] [blame]72I(SUBr , "sub", 3, 2, B12, true , 0, 1, SPARC_IEUN, 0)
73I(SUBi , "sub", 3, 2, B12, true , 0, 1, SPARC_IEUN, 0)
74I(SUBccr , "subcc", 4, 2, B12, true , 0, 1, SPARC_IEU1, M_CC_FLAG )
75I(SUBcci , "subcc", 4, 2, B12, true , 0, 1, SPARC_IEU1, M_CC_FLAG )
76I(SUBCr , "subc", 3, 2, B12, true , 0, 1, SPARC_IEUN, 0)
77I(SUBCi , "subc", 3, 2, B12, true , 0, 1, SPARC_IEUN, 0)
78I(SUBCccr, "subccc", 4, 2, B12, true , 0, 1, SPARC_IEU1, M_CC_FLAG )
79I(SUBCcci, "subccc", 4, 2, B12, true , 0, 1, SPARC_IEU1, M_CC_FLAG )
Chris Lattner9a3d63b2001-09-19 15:56:23 +0000[diff] [blame]80
81// Integer multiply, signed divide, unsigned divide.
82// Note that the deprecated 32-bit multiply and multiply-step are not used.
Chris Lattner07559122004-02-29 05:58:30 +0000[diff] [blame]83I(MULXr , "mulx", 3, 2, B12, true , 0, 3, SPARC_IEUN, 0)
84I(MULXi , "mulx", 3, 2, B12, true , 0, 3, SPARC_IEUN, 0)
85I(SDIVXr, "sdivx", 3, 2, B12, true , 0, 6, SPARC_IEUN, 0)
86I(SDIVXi, "sdivx", 3, 2, B12, true , 0, 6, SPARC_IEUN, 0)
87I(UDIVXr, "udivx", 3, 2, B12, true , 0, 6, SPARC_IEUN, 0)
88I(UDIVXi, "udivx", 3, 2, B12, true , 0, 6, SPARC_IEUN, 0)
Vikram S. Adve585612e2002-03-24 03:33:53 +0000[diff] [blame]89
Chris Lattner9a3d63b2001-09-19 15:56:23 +0000[diff] [blame]90 // Floating point add, subtract, compare.
91 // Note that destination of FCMP* instructions is operand 0, not operand 2.
Chris Lattner07559122004-02-29 05:58:30 +0000[diff] [blame]92I(FADDS, "fadds", 3, 2, 0, false, 0, 3, SPARC_FPA, 0)
93I(FADDD, "faddd", 3, 2, 0, false, 0, 3, SPARC_FPA, 0)
94I(FADDQ, "faddq", 3, 2, 0, false, 0, 3, SPARC_FPA, 0)
95I(FSUBS, "fsubs", 3, 2, 0, false, 0, 3, SPARC_FPA, 0)
96I(FSUBD, "fsubd", 3, 2, 0, false, 0, 3, SPARC_FPA, 0)
97I(FSUBQ, "fsubq", 3, 2, 0, false, 0, 3, SPARC_FPA, 0)
98I(FCMPS, "fcmps", 3, 0, 0, false, 0, 3, SPARC_FPA, M_CC_FLAG )
99I(FCMPD, "fcmpd", 3, 0, 0, false, 0, 3, SPARC_FPA, M_CC_FLAG )
100I(FCMPQ, "fcmpq", 3, 0, 0, false, 0, 3, SPARC_FPA, M_CC_FLAG )
Chris Lattner9a3d63b2001-09-19 15:56:23 +0000[diff] [blame]101// NOTE: FCMPE{S,D,Q}: FP Compare With Exception are currently unused!
Vikram S. Advec7b2e5c2001-10-28 21:41:01 +0000[diff] [blame]102
Chris Lattner9a3d63b2001-09-19 15:56:23 +0000[diff] [blame]103// Floating point multiply or divide.
Chris Lattner07559122004-02-29 05:58:30 +0000[diff] [blame]104I(FMULS , "fmuls", 3, 2, 0, false, 0, 3, SPARC_FPM, 0)
105I(FMULD , "fmuld", 3, 2, 0, false, 0, 3, SPARC_FPM, 0)
106I(FMULQ , "fmulq", 3, 2, 0, false, 0, 0, SPARC_FPM, 0)
107I(FSMULD, "fsmuld", 3, 2, 0, false, 0, 3, SPARC_FPM, 0)
108I(FDMULQ, "fdmulq", 3, 2, 0, false, 0, 0, SPARC_FPM, 0)
109I(FDIVS , "fdivs", 3, 2, 0, false, 0, 12, SPARC_FPM, 0)
110I(FDIVD , "fdivd", 3, 2, 0, false, 0, 22, SPARC_FPM, 0)
111I(FDIVQ , "fdivq", 3, 2, 0, false, 0, 0, SPARC_FPM, 0)
112I(FSQRTS, "fsqrts", 3, 2, 0, false, 0, 12, SPARC_FPM, 0)
113I(FSQRTD, "fsqrtd", 3, 2, 0, false, 0, 22, SPARC_FPM, 0)
114I(FSQRTQ, "fsqrtq", 3, 2, 0, false, 0, 0, SPARC_FPM, 0)
Vikram S. Adve585612e2002-03-24 03:33:53 +0000[diff] [blame]115
Chris Lattner9a3d63b2001-09-19 15:56:23 +0000[diff] [blame]116// Logical operations
Chris Lattner07559122004-02-29 05:58:30 +0000[diff] [blame]117I(ANDr , "and", 3, 2, B12, true , 0, 1, SPARC_IEUN, 0)
118I(ANDi , "and", 3, 2, B12, true , 0, 1, SPARC_IEUN, 0)
119I(ANDccr , "andcc", 4, 2, B12, true , 0, 1, SPARC_IEU1, 0)
120I(ANDcci , "andcc", 4, 2, B12, true , 0, 1, SPARC_IEU1, 0)
121I(ANDNr , "andn", 3, 2, B12, true , 0, 1, SPARC_IEUN, 0)
122I(ANDNi , "andn", 3, 2, B12, true , 0, 1, SPARC_IEUN, 0)
123I(ANDNccr, "andncc", 4, 2, B12, true , 0, 1, SPARC_IEU1, 0)
124I(ANDNcci, "andncc", 4, 2, B12, true , 0, 1, SPARC_IEU1, 0)
Misha Brukman6ddd9d82003-05-27 22:32:38 +0000[diff] [blame]125
Chris Lattner07559122004-02-29 05:58:30 +0000[diff] [blame]126I(ORr , "or", 3, 2, B12, true , 0, 1, SPARC_IEUN, 0)
127I(ORi , "or", 3, 2, B12, true , 0, 1, SPARC_IEUN, 0)
128I(ORccr , "orcc", 4, 2, B12, true , 0, 1, SPARC_IEU1, 0)
129I(ORcci , "orcc", 4, 2, B12, true , 0, 1, SPARC_IEU1, 0)
130I(ORNr , "orn", 3, 2, B12, true , 0, 1, SPARC_IEUN, 0)
131I(ORNi , "orn", 3, 2, B12, true , 0, 1, SPARC_IEUN, 0)
132I(ORNccr, "orncc", 4, 2, B12, true , 0, 1, SPARC_IEU1, 0)
133I(ORNcci, "orncc", 4, 2, B12, true , 0, 1, SPARC_IEU1, 0)
Misha Brukman6ddd9d82003-05-27 22:32:38 +0000[diff] [blame]134
Chris Lattner07559122004-02-29 05:58:30 +0000[diff] [blame]135I(XORr , "xor", 3, 2, B12, true , 0, 1, SPARC_IEUN, 0)
136I(XORi , "xor", 3, 2, B12, true , 0, 1, SPARC_IEUN, 0)
137I(XORccr , "xorcc", 4, 2, B12, true , 0, 1, SPARC_IEU1, 0)
138I(XORcci , "xorcc", 4, 2, B12, true , 0, 1, SPARC_IEU1, 0)
139I(XNORr , "xnor", 3, 2, B12, true , 0, 1, SPARC_IEUN, 0)
140I(XNORi , "xnor", 3, 2, B12, true , 0, 1, SPARC_IEUN, 0)
141I(XNORccr, "xnorcc", 4, 2, B12, true , 0, 1, SPARC_IEU1, 0)
142I(XNORcci, "xnorcc", 4, 2, B12, true , 0, 1, SPARC_IEU1, 0)
Vikram S. Adve585612e2002-03-24 03:33:53 +0000[diff] [blame]143
Chris Lattner9a3d63b2001-09-19 15:56:23 +0000[diff] [blame]144// Shift operations
Chris Lattner07559122004-02-29 05:58:30 +0000[diff] [blame]145I(SLLr5 , "sll", 3, 2, B5, true , 0, 1, SPARC_IEU0, 0)
146I(SLLi5 , "sll", 3, 2, B5, true , 0, 1, SPARC_IEU0, 0)
147I(SRLr5 , "srl", 3, 2, B5, true , 0, 1, SPARC_IEU0, 0)
148I(SRLi5 , "srl", 3, 2, B5, true , 0, 1, SPARC_IEU0, 0)
149I(SRAr5 , "sra", 3, 2, B5, true , 0, 1, SPARC_IEU0, 0)
150I(SRAi5 , "sra", 3, 2, B5, true , 0, 1, SPARC_IEU0, 0)
151I(SLLXr6, "sllx", 3, 2, B6, true , 0, 1, SPARC_IEU0, 0)
152I(SLLXi6, "sllx", 3, 2, B6, true , 0, 1, SPARC_IEU0, 0)
153I(SRLXr6, "srlx", 3, 2, B6, true , 0, 1, SPARC_IEU0, 0)
154I(SRLXi6, "srlx", 3, 2, B6, true , 0, 1, SPARC_IEU0, 0)
155I(SRAXr6, "srax", 3, 2, B6, true , 0, 1, SPARC_IEU0, 0)
156I(SRAXi6, "srax", 3, 2, B6, true , 0, 1, SPARC_IEU0, 0)
Misha Brukman6ddd9d82003-05-27 22:32:38 +0000[diff] [blame]157
Chris Lattner9a3d63b2001-09-19 15:56:23 +0000[diff] [blame]158// Floating point move, negate, and abs instructions
Chris Lattner07559122004-02-29 05:58:30 +0000[diff] [blame]159I(FMOVS, "fmovs", 2, 1, 0, false, 0, 1, SPARC_FPA, 0)
160I(FMOVD, "fmovd", 2, 1, 0, false, 0, 1, SPARC_FPA, 0)
161//I(FMOVQ, "fmovq", 2, 1, 0, false, 0, ?, SPARC_FPA, 0)
162I(FNEGS, "fnegs", 2, 1, 0, false, 0, 1, SPARC_FPA, 0)
163I(FNEGD, "fnegd", 2, 1, 0, false, 0, 1, SPARC_FPA, 0)
164//I(FNEGQ, "fnegq", 2, 1, 0, false, 0, ?, SPARC_FPA, 0)
165I(FABSS, "fabss", 2, 1, 0, false, 0, 1, SPARC_FPA, 0)
166I(FABSD, "fabsd", 2, 1, 0, false, 0, 1, SPARC_FPA, 0)
167//I(FABSQ, "fabsq", 2, 1, 0, false, 0, ?, SPARC_FPA, 0)
Vikram S. Adve585612e2002-03-24 03:33:53 +0000[diff] [blame]168
Chris Lattner9a3d63b2001-09-19 15:56:23 +0000[diff] [blame]169// Convert from floating point to floating point formats
Chris Lattner07559122004-02-29 05:58:30 +0000[diff] [blame]170I(FSTOD, "fstod", 2, 1, 0, false, 0, 3, SPARC_FPA, 0)
171I(FSTOQ, "fstoq", 2, 1, 0, false, 0, 0, SPARC_FPA, 0)
172I(FDTOS, "fdtos", 2, 1, 0, false, 0, 3, SPARC_FPA, 0)
173I(FDTOQ, "fdtoq", 2, 1, 0, false, 0, 0, SPARC_FPA, 0)
174I(FQTOS, "fqtos", 2, 1, 0, false, 0, 0, SPARC_FPA, 0)
175I(FQTOD, "fqtod", 2, 1, 0, false, 0, 0, SPARC_FPA, 0)
Vikram S. Adve585612e2002-03-24 03:33:53 +0000[diff] [blame]176
Chris Lattner9a3d63b2001-09-19 15:56:23 +0000[diff] [blame]177// Convert from floating point to integer formats.
178// Note that this accesses both integer and floating point registers.
Chris Lattner07559122004-02-29 05:58:30 +0000[diff] [blame]179I(FSTOX, "fstox", 2, 1, 0, false, 0, 3, SPARC_FPA, 0)
180I(FDTOX, "fdtox", 2, 1, 0, false, 0, 0, SPARC_FPA, 0)
181I(FQTOX, "fqtox", 2, 1, 0, false, 0, 2, SPARC_FPA, 0)
182I(FSTOI, "fstoi", 2, 1, 0, false, 0, 3, SPARC_FPA, 0)
183I(FDTOI, "fdtoi", 2, 1, 0, false, 0, 3, SPARC_FPA, 0)
184I(FQTOI, "fqtoi", 2, 1, 0, false, 0, 0, SPARC_FPA, 0)
Vikram S. Adve585612e2002-03-24 03:33:53 +0000[diff] [blame]185
Chris Lattner9a3d63b2001-09-19 15:56:23 +0000[diff] [blame]186// Convert from integer to floating point formats
187// Note that this accesses both integer and floating point registers.
Chris Lattner07559122004-02-29 05:58:30 +0000[diff] [blame]188I(FXTOS, "fxtos", 2, 1, 0, false, 0, 3, SPARC_FPA, 0)
189I(FXTOD, "fxtod", 2, 1, 0, false, 0, 3, SPARC_FPA, 0)
190I(FXTOQ, "fxtoq", 2, 1, 0, false, 0, 0, SPARC_FPA, 0)
191I(FITOS, "fitos", 2, 1, 0, false, 0, 3, SPARC_FPA, 0)
192I(FITOD, "fitod", 2, 1, 0, false, 0, 3, SPARC_FPA, 0)
193I(FITOQ, "fitoq", 2, 1, 0, false, 0, 0, SPARC_FPA, 0)
Vikram S. Adve585612e2002-03-24 03:33:53 +0000[diff] [blame]194
Chris Lattner9a3d63b2001-09-19 15:56:23 +0000[diff] [blame]195// Branch on integer comparison with zero.
Vikram S. Adve585612e2002-03-24 03:33:53 +0000[diff] [blame]196// Latency excludes the delay slot since it can be issued in same cycle.
Chris Lattner07559122004-02-29 05:58:30 +0000[diff] [blame]197I(BRZ , "brz", 2, -1, B15, true , 1, 1, SPARC_CTI, M_BRANCH_FLAG)
198I(BRLEZ, "brlez", 2, -1, B15, true , 1, 1, SPARC_CTI, M_BRANCH_FLAG)
199I(BRLZ , "brlz", 2, -1, B15, true , 1, 1, SPARC_CTI, M_BRANCH_FLAG)
200I(BRNZ , "brnz", 2, -1, B15, true , 1, 1, SPARC_CTI, M_BRANCH_FLAG)
201I(BRGZ , "brgz", 2, -1, B15, true , 1, 1, SPARC_CTI, M_BRANCH_FLAG)
202I(BRGEZ, "brgez", 2, -1, B15, true , 1, 1, SPARC_CTI, M_BRANCH_FLAG)
Chris Lattner9a3d63b2001-09-19 15:56:23 +0000[diff] [blame]203
204// Branch on integer condition code.
205// The first argument specifies the ICC register: %icc or %xcc
206// Latency includes the delay slot.
Vikram S. Adve97da3642002-07-08 23:25:17 +0000[diff] [blame]207I(BA , "ba", 1, -1, B21, true , 1, 2, SPARC_CTI, M_CC_FLAG | M_BRANCH_FLAG)
Chris Lattner9a3d63b2001-09-19 15:56:23 +0000[diff] [blame]208I(BN , "bn", 2, -1, B21, true , 1, 2, SPARC_CTI, M_CC_FLAG | M_BRANCH_FLAG)
209I(BNE , "bne", 2, -1, B21, true , 1, 2, SPARC_CTI, M_CC_FLAG | M_BRANCH_FLAG)
210I(BE , "be", 2, -1, B21, true , 1, 2, SPARC_CTI, M_CC_FLAG | M_BRANCH_FLAG)
211I(BG , "bg", 2, -1, B21, true , 1, 2, SPARC_CTI, M_CC_FLAG | M_BRANCH_FLAG)
212I(BLE , "ble", 2, -1, B21, true , 1, 2, SPARC_CTI, M_CC_FLAG | M_BRANCH_FLAG)
213I(BGE , "bge", 2, -1, B21, true , 1, 2, SPARC_CTI, M_CC_FLAG | M_BRANCH_FLAG)
214I(BL , "bl", 2, -1, B21, true , 1, 2, SPARC_CTI, M_CC_FLAG | M_BRANCH_FLAG)
215I(BGU , "bgu", 2, -1, B21, true , 1, 2, SPARC_CTI, M_CC_FLAG | M_BRANCH_FLAG)
216I(BLEU, "bleu", 2, -1, B21, true , 1, 2, SPARC_CTI, M_CC_FLAG | M_BRANCH_FLAG)
217I(BCC , "bcc", 2, -1, B21, true , 1, 2, SPARC_CTI, M_CC_FLAG | M_BRANCH_FLAG)
218I(BCS , "bcs", 2, -1, B21, true , 1, 2, SPARC_CTI, M_CC_FLAG | M_BRANCH_FLAG)
219I(BPOS, "bpos", 2, -1, B21, true , 1, 2, SPARC_CTI, M_CC_FLAG | M_BRANCH_FLAG)
220I(BNEG, "bneg", 2, -1, B21, true , 1, 2, SPARC_CTI, M_CC_FLAG | M_BRANCH_FLAG)
221I(BVC , "bvc", 2, -1, B21, true , 1, 2, SPARC_CTI, M_CC_FLAG | M_BRANCH_FLAG)
222I(BVS , "bvs", 2, -1, B21, true , 1, 2, SPARC_CTI, M_CC_FLAG | M_BRANCH_FLAG)
223
224// Branch on floating point condition code.
Chris Lattner9a3d63b2001-09-19 15:56:23 +0000[diff] [blame]225// The first argument is the FCCn register (0 <= n <= 3).
226// Latency includes the delay slot.
227I(FBA , "fba", 2, -1, B18, true , 1, 2, SPARC_CTI, M_CC_FLAG | M_BRANCH_FLAG)
228I(FBN , "fbn", 2, -1, B18, true , 1, 2, SPARC_CTI, M_CC_FLAG | M_BRANCH_FLAG)
229I(FBU , "fbu", 2, -1, B18, true , 1, 2, SPARC_CTI, M_CC_FLAG | M_BRANCH_FLAG)
230I(FBG , "fbg", 2, -1, B18, true , 1, 2, SPARC_CTI, M_CC_FLAG | M_BRANCH_FLAG)
231I(FBUG , "fbug", 2, -1, B18, true , 1, 2, SPARC_CTI, M_CC_FLAG | M_BRANCH_FLAG)
232I(FBL , "fbl", 2, -1, B18, true , 1, 2, SPARC_CTI, M_CC_FLAG | M_BRANCH_FLAG)
233I(FBUL , "fbul", 2, -1, B18, true , 1, 2, SPARC_CTI, M_CC_FLAG | M_BRANCH_FLAG)
234I(FBLG , "fblg", 2, -1, B18, true , 1, 2, SPARC_CTI, M_CC_FLAG | M_BRANCH_FLAG)
235I(FBNE , "fbne", 2, -1, B18, true , 1, 2, SPARC_CTI, M_CC_FLAG | M_BRANCH_FLAG)
236I(FBE , "fbe", 2, -1, B18, true , 1, 2, SPARC_CTI, M_CC_FLAG | M_BRANCH_FLAG)
237I(FBUE , "fbue", 2, -1, B18, true , 1, 2, SPARC_CTI, M_CC_FLAG | M_BRANCH_FLAG)
238I(FBGE , "fbge", 2, -1, B18, true , 1, 2, SPARC_CTI, M_CC_FLAG | M_BRANCH_FLAG)
239I(FBUGE, "fbuge", 2, -1, B18, true , 1, 2, SPARC_CTI, M_CC_FLAG | M_BRANCH_FLAG)
240I(FBLE , "fble", 2, -1, B18, true , 1, 2, SPARC_CTI, M_CC_FLAG | M_BRANCH_FLAG)
241I(FBULE, "fbule", 2, -1, B18, true , 1, 2, SPARC_CTI, M_CC_FLAG | M_BRANCH_FLAG)
242I(FBO , "fbo", 2, -1, B18, true , 1, 2, SPARC_CTI, M_CC_FLAG | M_BRANCH_FLAG)
243
244// Conditional move on integer comparison with zero.
Chris Lattner07559122004-02-29 05:58:30 +0000[diff] [blame]245I(MOVRZr , "movrz", 3, 2, B12, true , 0, 2, SPARC_SINGLE, 0)
246I(MOVRZi , "movrz", 3, 2, B12, true , 0, 2, SPARC_SINGLE, 0)
247I(MOVRLEZr, "movrlez", 3, 2, B12, true , 0, 2, SPARC_SINGLE, 0)
248I(MOVRLEZi, "movrlez", 3, 2, B12, true , 0, 2, SPARC_SINGLE, 0)
249I(MOVRLZr , "movrlz", 3, 2, B12, true , 0, 2, SPARC_SINGLE, 0)
250I(MOVRLZi , "movrlz", 3, 2, B12, true , 0, 2, SPARC_SINGLE, 0)
251I(MOVRNZr , "movrnz", 3, 2, B12, true , 0, 2, SPARC_SINGLE, 0)
252I(MOVRNZi , "movrnz", 3, 2, B12, true , 0, 2, SPARC_SINGLE, 0)
253I(MOVRGZr , "movrgz", 3, 2, B12, true , 0, 2, SPARC_SINGLE, 0)
254I(MOVRGZi , "movrgz", 3, 2, B12, true , 0, 2, SPARC_SINGLE, 0)
255I(MOVRGEZr, "movrgez", 3, 2, B12, true , 0, 2, SPARC_SINGLE, 0)
256I(MOVRGEZi, "movrgez", 3, 2, B12, true , 0, 2, SPARC_SINGLE, 0)
Chris Lattner9a3d63b2001-09-19 15:56:23 +0000[diff] [blame]257
258// Conditional move on integer condition code.
259// The first argument specifies the ICC register: %icc or %xcc
Chris Lattner07559122004-02-29 05:58:30 +0000[diff] [blame]260I(MOVAr , "mova", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
261I(MOVAi , "mova", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
262I(MOVNr , "movn", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
263I(MOVNi , "movn", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
264I(MOVNEr , "movne", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
265I(MOVNEi , "movne", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
266I(MOVEr , "move", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
267I(MOVEi , "move", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
268I(MOVGr , "movg", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
269I(MOVGi , "movg", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
270I(MOVLEr , "movle", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
271I(MOVLEi , "movle", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
272I(MOVGEr , "movge", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
273I(MOVGEi , "movge", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
274I(MOVLr , "movl", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
275I(MOVLi , "movl", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
276I(MOVGUr , "movgu", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
277I(MOVGUi , "movgu", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
278I(MOVLEUr, "movleu", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
279I(MOVLEUi, "movleu", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
280I(MOVCCr , "movcc", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
281I(MOVCCi , "movcc", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
282I(MOVCSr , "movcs", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
283I(MOVCSi , "movcs", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
284I(MOVPOSr, "movpos", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
285I(MOVPOSi, "movpos", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
286I(MOVNEGr, "movneg", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
287I(MOVNEGi, "movneg", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
288I(MOVVCr , "movvc", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
289I(MOVVCi , "movvc", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
290I(MOVVSr , "movvs", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
291I(MOVVSi , "movvs", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
Chris Lattner9a3d63b2001-09-19 15:56:23 +0000[diff] [blame]292
293// Conditional move (of integer register) on floating point condition code.
294// The first argument is the FCCn register (0 <= n <= 3).
295// Note that the enum name above is not the same as the assembly mnemonic
296// because some of the assembly mnemonics are the same as the move on
297// integer CC (e.g., MOVG), and we cannot have the same enum entry twice.
Chris Lattner07559122004-02-29 05:58:30 +0000[diff] [blame]298I(MOVFAr , "mova", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
299I(MOVFAi , "mova", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
300I(MOVFNr , "movn", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
301I(MOVFNi , "movn", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
302I(MOVFUr , "movu", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
303I(MOVFUi , "movu", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
304I(MOVFGr , "movg", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
305I(MOVFGi , "movg", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
306I(MOVFUGr , "movug", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
307I(MOVFUGi , "movug", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
308I(MOVFLr , "movl", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
309I(MOVFLi , "movl", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
310I(MOVFULr , "movul", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
311I(MOVFULi , "movul", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
312I(MOVFLGr , "movlg", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
313I(MOVFLGi , "movlg", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
314I(MOVFNEr , "movne", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
315I(MOVFNEi , "movne", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
316I(MOVFEr , "move", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
317I(MOVFEi , "move", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
318I(MOVFUEr , "movue", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
319I(MOVFUEi , "movue", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
320I(MOVFGEr , "movge", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
321I(MOVFGEi , "movge", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
322I(MOVFUGEr, "movuge", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
323I(MOVFUGEi, "movuge", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
324I(MOVFLEr , "movle", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
325I(MOVFLEi , "movle", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
326I(MOVFULEr, "movule", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
327I(MOVFULEi, "movule", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
328I(MOVFOr , "movo", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
329I(MOVFOi , "movo", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
Chris Lattner9a3d63b2001-09-19 15:56:23 +0000[diff] [blame]330
331// Conditional move of floating point register on each of the above:
332// i. on integer comparison with zero.
333// ii. on integer condition code
334// iii. on floating point condition code
335// Note that the same set is repeated for S,D,Q register classes.
Chris Lattner07559122004-02-29 05:58:30 +0000[diff] [blame]336I(FMOVRSZ ,"fmovrsz", 3, 2, 0, false, 0, 2, SPARC_SINGLE, 0)
337I(FMOVRSLEZ,"fmovrslez",3, 2, 0, false, 0, 2, SPARC_SINGLE, 0)
338I(FMOVRSLZ ,"fmovrslz", 3, 2, 0, false, 0, 2, SPARC_SINGLE, 0)
339I(FMOVRSNZ ,"fmovrsnz", 3, 2, 0, false, 0, 2, SPARC_SINGLE, 0)
340I(FMOVRSGZ ,"fmovrsgz", 3, 2, 0, false, 0, 2, SPARC_SINGLE, 0)
341I(FMOVRSGEZ,"fmovrsgez",3, 2, 0, false, 0, 2, SPARC_SINGLE, 0)
Chris Lattner9a3d63b2001-09-19 15:56:23 +0000[diff] [blame]342
Chris Lattner07559122004-02-29 05:58:30 +0000[diff] [blame]343I(FMOVSA , "fmovsa", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
344I(FMOVSN , "fmovsn", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
345I(FMOVSNE , "fmovsne", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
346I(FMOVSE , "fmovse", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
347I(FMOVSG , "fmovsg", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
348I(FMOVSLE , "fmovsle", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
349I(FMOVSGE , "fmovsge", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
350I(FMOVSL , "fmovsl", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
351I(FMOVSGU , "fmovsgu", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
352I(FMOVSLEU, "fmovsleu", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
353I(FMOVSCC , "fmovscc", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
354I(FMOVSCS , "fmovscs", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
355I(FMOVSPOS, "fmovspos", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
356I(FMOVSNEG, "fmovsneg", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
357I(FMOVSVC , "fmovsvc", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
358I(FMOVSVS , "fmovsvs", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
Chris Lattner9a3d63b2001-09-19 15:56:23 +0000[diff] [blame]359
Chris Lattner07559122004-02-29 05:58:30 +0000[diff] [blame]360I(FMOVSFA , "fmovsa", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
361I(FMOVSFN , "fmovsn", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
362I(FMOVSFU , "fmovsu", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
363I(FMOVSFG , "fmovsg", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
364I(FMOVSFUG , "fmovsug", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
365I(FMOVSFL , "fmovsl", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
366I(FMOVSFUL , "fmovsul", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
367I(FMOVSFLG , "fmovslg", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
368I(FMOVSFNE , "fmovsne", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
369I(FMOVSFE , "fmovse", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
370I(FMOVSFUE , "fmovsue", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
371I(FMOVSFGE , "fmovsge", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
372I(FMOVSFUGE, "fmovsuge",3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
373I(FMOVSFLE , "fmovsle", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
374I(FMOVSFULE, "fmovslue",3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
375I(FMOVSFO , "fmovso", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
Chris Lattner9a3d63b2001-09-19 15:56:23 +0000[diff] [blame]376
Chris Lattner07559122004-02-29 05:58:30 +0000[diff] [blame]377I(FMOVRDZ , "fmovrdz", 3, 2, 0, false, 0, 2, SPARC_SINGLE, 0)
378I(FMOVRDLEZ, "fmovrdlez",3, 2, 0, false, 0, 2, SPARC_SINGLE, 0)
379I(FMOVRDLZ , "fmovrdlz",3, 2, 0, false, 0, 2, SPARC_SINGLE, 0)
380I(FMOVRDNZ , "fmovrdnz",3, 2, 0, false, 0, 2, SPARC_SINGLE, 0)
381I(FMOVRDGZ , "fmovrdgz",3, 2, 0, false, 0, 2, SPARC_SINGLE, 0)
382I(FMOVRDGEZ, "fmovrdgez",3, 2, 0, false, 0, 2, SPARC_SINGLE, 0)
Chris Lattner9a3d63b2001-09-19 15:56:23 +0000[diff] [blame]383
Chris Lattner07559122004-02-29 05:58:30 +0000[diff] [blame]384I(FMOVDA , "fmovda", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
385I(FMOVDN , "fmovdn", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
386I(FMOVDNE , "fmovdne", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
387I(FMOVDE , "fmovde", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
388I(FMOVDG , "fmovdg", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
389I(FMOVDLE , "fmovdle", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
390I(FMOVDGE , "fmovdge", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
391I(FMOVDL , "fmovdl", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
392I(FMOVDGU , "fmovdgu", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
393I(FMOVDLEU, "fmovdleu", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
394I(FMOVDCC , "fmovdcc", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
395I(FMOVDCS , "fmovdcs", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
396I(FMOVDPOS, "fmovdpos", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
397I(FMOVDNEG, "fmovdneg", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
398I(FMOVDVC , "fmovdvc", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
399I(FMOVDVS , "fmovdvs", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
Chris Lattner9a3d63b2001-09-19 15:56:23 +0000[diff] [blame]400
Chris Lattner07559122004-02-29 05:58:30 +0000[diff] [blame]401I(FMOVDFA , "fmovda", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
402I(FMOVDFN , "fmovdn", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
403I(FMOVDFU , "fmovdu", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
404I(FMOVDFG , "fmovdg", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
405I(FMOVDFUG , "fmovdug", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
406I(FMOVDFL , "fmovdl", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
407I(FMOVDFUL , "fmovdul", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
408I(FMOVDFLG , "fmovdlg", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
409I(FMOVDFNE , "fmovdne", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
410I(FMOVDFE , "fmovde", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
411I(FMOVDFUE , "fmovdue", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
412I(FMOVDFGE , "fmovdge", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
413I(FMOVDFUGE, "fmovduge",3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
414I(FMOVDFLE , "fmovdle", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
415I(FMOVDFULE, "fmovdule",3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
416I(FMOVDFO , "fmovdo", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
Chris Lattner9a3d63b2001-09-19 15:56:23 +0000[diff] [blame]417
Chris Lattner07559122004-02-29 05:58:30 +0000[diff] [blame]418I(FMOVRQZ , "fmovrqz", 3, 2, 0, false, 0, 2, SPARC_SINGLE, 0)
419I(FMOVRQLEZ, "fmovrqlez",3, 2, 0, false, 0, 2, SPARC_SINGLE, 0)
420I(FMOVRQLZ , "fmovrqlz",3, 2, 0, false, 0, 2, SPARC_SINGLE, 0)
421I(FMOVRQNZ , "fmovrqnz",3, 2, 0, false, 0, 2, SPARC_SINGLE, 0)
422I(FMOVRQGZ , "fmovrqgz",3, 2, 0, false, 0, 2, SPARC_SINGLE, 0)
423I(FMOVRQGEZ, "fmovrqgez",3, 2, 0, false, 0, 2, SPARC_SINGLE, 0)
Chris Lattner9a3d63b2001-09-19 15:56:23 +0000[diff] [blame]424
Chris Lattner07559122004-02-29 05:58:30 +0000[diff] [blame]425I(FMOVQA , "fmovqa", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
426I(FMOVQN , "fmovqn", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
427I(FMOVQNE , "fmovqne", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
428I(FMOVQE , "fmovqe", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
429I(FMOVQG , "fmovqg", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
430I(FMOVQLE , "fmovqle", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
431I(FMOVQGE , "fmovqge", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
432I(FMOVQL , "fmovql", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
433I(FMOVQGU , "fmovqgu", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
434I(FMOVQLEU, "fmovqleu", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
435I(FMOVQCC , "fmovqcc", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
436I(FMOVQCS , "fmovqcs", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
437I(FMOVQPOS, "fmovqpos", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
438I(FMOVQNEG, "fmovqneg", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
439I(FMOVQVC , "fmovqvc", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
440I(FMOVQVS , "fmovqvs", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
Chris Lattner9a3d63b2001-09-19 15:56:23 +0000[diff] [blame]441
Chris Lattner07559122004-02-29 05:58:30 +0000[diff] [blame]442I(FMOVQFA , "fmovqa", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
443I(FMOVQFN , "fmovqn", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
444I(FMOVQFU , "fmovqu", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
445I(FMOVQFG , "fmovqg", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
446I(FMOVQFUG , "fmovqug", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
447I(FMOVQFL , "fmovql", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
448I(FMOVQFUL , "fmovqul", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
449I(FMOVQFLG , "fmovqlg", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
450I(FMOVQFNE , "fmovqne", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
451I(FMOVQFE , "fmovqe", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
452I(FMOVQFUE , "fmovque", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
453I(FMOVQFGE , "fmovqge", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
454I(FMOVQFUGE, "fmovquge",3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
455I(FMOVQFLE , "fmovqle", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
456I(FMOVQFULE, "fmovqule",3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
457I(FMOVQFO , "fmovqo", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG)
Vikram S. Adve585612e2002-03-24 03:33:53 +0000[diff] [blame]458
Chris Lattner9a3d63b2001-09-19 15:56:23 +0000[diff] [blame]459// Load integer instructions
Vikram S. Adve585612e2002-03-24 03:33:53 +0000[diff] [blame]460// Latency includes 1 cycle for address generation (Sparc IIi),
461// plus 3 cycles assumed for average miss penalty (bias towards L1 hits).
Chris Lattner9a3d63b2001-09-19 15:56:23 +0000[diff] [blame]462// Signed loads of less than 64 bits need an extra cycle for sign-extension.
463//
464// Not reflected here: After a 3-cycle loads, all subsequent consecutive
465// loads also require 3 cycles to avoid contention for the load return
466// stage. Latency returns to 2 cycles after the first cycle with no load.
Chris Lattner07559122004-02-29 05:58:30 +0000[diff] [blame]467I(LDSBr, "ldsb", 3, 2, B12, true , 0, 6, SPARC_LD, M_LOAD_FLAG)
468I(LDSBi, "ldsb", 3, 2, B12, true , 0, 6, SPARC_LD, M_LOAD_FLAG)
469I(LDSHr, "ldsh", 3, 2, B12, true , 0, 6, SPARC_LD, M_LOAD_FLAG)
470I(LDSHi, "ldsh", 3, 2, B12, true , 0, 6, SPARC_LD, M_LOAD_FLAG)
471I(LDSWr, "ldsw", 3, 2, B12, true , 0, 6, SPARC_LD, M_LOAD_FLAG)
472I(LDSWi, "ldsw", 3, 2, B12, true , 0, 6, SPARC_LD, M_LOAD_FLAG)
473I(LDUBr, "ldub", 3, 2, B12, true , 0, 5, SPARC_LD, M_LOAD_FLAG)
474I(LDUBi, "ldub", 3, 2, B12, true , 0, 5, SPARC_LD, M_LOAD_FLAG)
475I(LDUHr, "lduh", 3, 2, B12, true , 0, 5, SPARC_LD, M_LOAD_FLAG)
476I(LDUHi, "lduh", 3, 2, B12, true , 0, 5, SPARC_LD, M_LOAD_FLAG)
477I(LDUWr, "lduw", 3, 2, B12, true , 0, 5, SPARC_LD, M_LOAD_FLAG)
478I(LDUWi, "lduw", 3, 2, B12, true , 0, 5, SPARC_LD, M_LOAD_FLAG)
479I(LDXr , "ldx" , 3, 2, B12, true , 0, 5, SPARC_LD, M_LOAD_FLAG)
480I(LDXi , "ldx" , 3, 2, B12, true , 0, 5, SPARC_LD, M_LOAD_FLAG)
Vikram S. Adve585612e2002-03-24 03:33:53 +0000[diff] [blame]481
Chris Lattner9a3d63b2001-09-19 15:56:23 +0000[diff] [blame]482// Load floating-point instructions
483// Latency includes 1 cycle for address generation (Sparc IIi)
Chris Lattner07559122004-02-29 05:58:30 +0000[diff] [blame]484I(LDFr , "ld", 3, 2, B12, true , 0, 5, SPARC_LD, M_LOAD_FLAG)
485I(LDFi , "ld", 3, 2, B12, true , 0, 5, SPARC_LD, M_LOAD_FLAG)
486I(LDDFr, "ldd", 3, 2, B12, true , 0, 5, SPARC_LD, M_LOAD_FLAG)
487I(LDDFi, "ldd", 3, 2, B12, true , 0, 5, SPARC_LD, M_LOAD_FLAG)
488I(LDQFr, "ldq", 3, 2, B12, true , 0, 5, SPARC_LD, M_LOAD_FLAG)
489I(LDQFi, "ldq", 3, 2, B12, true , 0, 5, SPARC_LD, M_LOAD_FLAG)
490I(LDFSRr, "ld", 3, 2, B12, true , 0, 5, SPARC_LD, M_LOAD_FLAG)
491I(LDFSRi, "ld", 3, 2, B12, true , 0, 5, SPARC_LD, M_LOAD_FLAG)
492I(LDXFSRr, "ldx", 3, 2, B12, true , 0, 5, SPARC_LD, M_LOAD_FLAG)
493I(LDXFSRi, "ldx", 3, 2, B12, true , 0, 5, SPARC_LD, M_LOAD_FLAG)
Vikram S. Adve585612e2002-03-24 03:33:53 +0000[diff] [blame]494
495// Store integer instructions.
496// Requires 1 cycle for address generation (Sparc IIi).
497// Default latency is 0 because value is not explicitly used.
Chris Lattner07559122004-02-29 05:58:30 +0000[diff] [blame]498I(STBr, "stb", 3, -1, B12, true , 0, 0, SPARC_ST, M_STORE_FLAG)
499I(STBi, "stb", 3, -1, B12, true , 0, 0, SPARC_ST, M_STORE_FLAG)
500I(STHr, "sth", 3, -1, B12, true , 0, 0, SPARC_ST, M_STORE_FLAG)
501I(STHi, "sth", 3, -1, B12, true , 0, 0, SPARC_ST, M_STORE_FLAG)
502I(STWr, "stw", 3, -1, B12, true , 0, 0, SPARC_ST, M_STORE_FLAG)
503I(STWi, "stw", 3, -1, B12, true , 0, 0, SPARC_ST, M_STORE_FLAG)
504I(STXr, "stx", 3, -1, B12, true , 0, 0, SPARC_ST, M_STORE_FLAG)
505I(STXi, "stx", 3, -1, B12, true , 0, 0, SPARC_ST, M_STORE_FLAG)
Vikram S. Adve585612e2002-03-24 03:33:53 +0000[diff] [blame]506
Chris Lattner9a3d63b2001-09-19 15:56:23 +0000[diff] [blame]507// Store floating-point instructions (Sparc IIi)
Chris Lattner07559122004-02-29 05:58:30 +0000[diff] [blame]508I(STFr, "st", 3, -1, B12, true , 0, 0, SPARC_ST, M_STORE_FLAG)
509I(STFi, "st", 3, -1, B12, true , 0, 0, SPARC_ST, M_STORE_FLAG)
510I(STDFr, "std", 3, -1, B12, true , 0, 0, SPARC_ST, M_STORE_FLAG)
511I(STDFi, "std", 3, -1, B12, true , 0, 0, SPARC_ST, M_STORE_FLAG)
512I(STFSRr, "st", 3, -1, B12, true , 0, 0, SPARC_ST, M_STORE_FLAG)
513I(STFSRi, "st", 3, -1, B12, true , 0, 0, SPARC_ST, M_STORE_FLAG)
514I(STXFSRr, "stx", 3, -1, B12, true , 0, 0, SPARC_ST, M_STORE_FLAG)
515I(STXFSRi, "stx", 3, -1, B12, true , 0, 0, SPARC_ST, M_STORE_FLAG)
Vikram S. Adve585612e2002-03-24 03:33:53 +0000[diff] [blame]516
Vikram S. Adveac670062002-09-28 17:00:15 +0000[diff] [blame]517// Call, Return and "Jump and link". Operand (2) for JMPL is marked as
518// a "result" because JMPL stores the return address for the call in it.
Chris Lattner9a3d63b2001-09-19 15:56:23 +0000[diff] [blame]519// Latency includes the delay slot.
Misha Brukman6ddd9d82003-05-27 22:32:38 +0000[diff] [blame]520I(CALL, "call", 1, -1, B29, true , 1, 2, SPARC_CTI, M_CALL_FLAG)
521I(JMPLCALLr, "jmpl", 3, 2, B12, true , 1, 2, SPARC_CTI, M_CALL_FLAG)
522I(JMPLCALLi, "jmpl", 3, 2, B12, true , 1, 2, SPARC_CTI, M_CALL_FLAG)
523I(JMPLRETr, "jmpl", 3, 2, B12, true , 1, 2, SPARC_CTI, M_RET_FLAG)
524I(JMPLRETi, "jmpl", 3, 2, B12, true , 1, 2, SPARC_CTI, M_RET_FLAG)
525I(RETURNr, "return", 2, -1, 0, false, 1, 2, SPARC_CTI, M_RET_FLAG)
526I(RETURNi, "return", 2, -1, 0, false, 1, 2, SPARC_CTI, M_RET_FLAG)
Vikram S. Adveb7f06f42001-11-04 19:34:49 +0000[diff] [blame]527
Vikram S. Adve1d86cc02001-10-22 13:32:55 +0000[diff] [blame]528// SAVE and restore instructions
Chris Lattner07559122004-02-29 05:58:30 +0000[diff] [blame]529I(SAVEr, "save", 3, 2, B12, true , 0, 1, SPARC_SINGLE, 0)
530I(SAVEi, "save", 3, 2, B12, true , 0, 1, SPARC_SINGLE, 0)
531I(RESTOREr, "restore", 3, 2, B12, true , 0, 1, SPARC_SINGLE, 0)
532I(RESTOREi, "restore", 3, 2, B12, true , 0, 1, SPARC_SINGLE, 0)
Vikram S. Adve1d86cc02001-10-22 13:32:55 +0000[diff] [blame]533
Ruchira Sasanka3839e6e2001-11-03 19:59:59 +0000[diff] [blame]534// Read and Write CCR register from/to an int reg
Chris Lattner07559122004-02-29 05:58:30 +0000[diff] [blame]535I(RDCCR, "rd", 2, 1, 0, false, 0, 1, SPARC_SINGLE, M_CC_FLAG)
536I(WRCCRr, "wr", 3, 2, 0, false, 0, 1, SPARC_SINGLE, M_CC_FLAG)
537I(WRCCRi, "wr", 3, 2, 0, false, 0, 1, SPARC_SINGLE, M_CC_FLAG)
Ruchira Sasanka3839e6e2001-11-03 19:59:59 +0000[diff] [blame]538
Chris Lattner9a3d63b2001-09-19 15:56:23 +0000[diff] [blame]539// Synthetic phi operation for near-SSA form of machine code
540// Number of operands is variable, indicated by -1. Result is the first op.
Tanya Lattnerf048bfd2004-03-01 15:05:17 +0000[diff] [blame^]541I(PHI, "<phi>", -1, 0, 0, false, 0, 0, SPARC_NONE, M_DUMMY_PHI_FLAG)
Chris Lattner9a3d63b2001-09-19 15:56:23 +0000[diff] [blame]542
543
544#undef B5
545#undef B6
546#undef B12
547#undef B15
548#undef B18
549#undef B21
550#undef B22
551#undef B29
552
553#undef I