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Evan Chenga8e29892007-01-19 07:51:42 +00001//===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===//
Rafael Espindola7bc59bc2006-05-14 22:18:28 +00002//
3// The LLVM Compiler Infrastructure
4//
5// This file was developed by the "Instituto Nokia de Tecnologia" and
6// is distributed under the University of Illinois Open Source
7// License. See LICENSE.TXT for details.
8//
9//===----------------------------------------------------------------------===//
10//
11// This file describes the ARM instructions in TableGen format.
12//
13//===----------------------------------------------------------------------===//
14
Evan Chenga8e29892007-01-19 07:51:42 +000015//===----------------------------------------------------------------------===//
16// ARM specific DAG Nodes.
17//
Rafael Espindola7cca7c52006-09-11 17:25:40 +000018
Evan Chenga8e29892007-01-19 07:51:42 +000019// Type profiles.
20def SDT_ARMCallSeq : SDTypeProfile<0, 1, [ SDTCisVT<0, i32> ]>;
Rafael Espindola6e8c6492006-11-08 17:07:32 +000021
Evan Chenga8e29892007-01-19 07:51:42 +000022def SDT_ARMSaveCallPC : SDTypeProfile<0, 1, []>;
Rafael Espindola32bd5f42006-10-17 18:04:53 +000023
Evan Chenga8e29892007-01-19 07:51:42 +000024def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisInt<0>]>;
Rafael Espindola7cca7c52006-09-11 17:25:40 +000025
Evan Chenga8e29892007-01-19 07:51:42 +000026def SDT_ARMCMov : SDTypeProfile<1, 3,
27 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
28 SDTCisVT<3, i32>]>;
Rafael Espindola6e8c6492006-11-08 17:07:32 +000029
Evan Chenga8e29892007-01-19 07:51:42 +000030def SDT_ARMBrcond : SDTypeProfile<0, 2,
31 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
32
33def SDT_ARMBrJT : SDTypeProfile<0, 3,
34 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
35 SDTCisVT<2, i32>]>;
36
37def SDT_ARMCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
38
39def SDT_ARMPICAdd : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>,
40 SDTCisPtrTy<1>, SDTCisVT<2, i32>]>;
41
Lauro Ramos Venancio64f4fa52007-04-27 13:54:47 +000042def SDT_ARMThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
43
Evan Chenga8e29892007-01-19 07:51:42 +000044// Node definitions.
45def ARMWrapper : SDNode<"ARMISD::Wrapper", SDTIntUnaryOp>;
Evan Chenga8e29892007-01-19 07:51:42 +000046def ARMWrapperJT : SDNode<"ARMISD::WrapperJT", SDTIntBinOp>;
47
48def ARMcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeq,
49 [SDNPHasChain, SDNPOutFlag]>;
50def ARMcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeq,
Evan Chengb38cba92007-02-03 09:11:58 +000051 [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>;
Evan Chenga8e29892007-01-19 07:51:42 +000052
53def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall,
54 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
55def ARMcall_nolink : SDNode<"ARMISD::CALL_NOLINK", SDT_ARMcall,
56 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
57
58def ARMretflag : SDNode<"ARMISD::RET_FLAG", SDTRet,
59 [SDNPHasChain, SDNPOptInFlag]>;
60
61def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov,
62 [SDNPInFlag]>;
63def ARMcneg : SDNode<"ARMISD::CNEG", SDT_ARMCMov,
64 [SDNPInFlag]>;
65
66def ARMbrcond : SDNode<"ARMISD::BRCOND", SDT_ARMBrcond,
67 [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>;
68
69def ARMbrjt : SDNode<"ARMISD::BR_JT", SDT_ARMBrJT,
70 [SDNPHasChain]>;
71
72def ARMcmp : SDNode<"ARMISD::CMP", SDT_ARMCmp,
73 [SDNPOutFlag]>;
74
Lauro Ramos Venancio99966632007-04-02 01:30:03 +000075def ARMcmpNZ : SDNode<"ARMISD::CMPNZ", SDT_ARMCmp,
76 [SDNPOutFlag]>;
77
Evan Chenga8e29892007-01-19 07:51:42 +000078def ARMpic_add : SDNode<"ARMISD::PIC_ADD", SDT_ARMPICAdd>;
79
80def ARMsrl_flag : SDNode<"ARMISD::SRL_FLAG", SDTIntUnaryOp, [SDNPOutFlag]>;
81def ARMsra_flag : SDNode<"ARMISD::SRA_FLAG", SDTIntUnaryOp, [SDNPOutFlag]>;
82def ARMrrx : SDNode<"ARMISD::RRX" , SDTIntUnaryOp, [SDNPInFlag ]>;
Rafael Espindola32bd5f42006-10-17 18:04:53 +000083
Lauro Ramos Venancio64f4fa52007-04-27 13:54:47 +000084def ARMthread_pointer: SDNode<"ARMISD::THREAD_POINTER", SDT_ARMThreadPointer>;
85
Rafael Espindola7bc59bc2006-05-14 22:18:28 +000086//===----------------------------------------------------------------------===//
Evan Chenga8e29892007-01-19 07:51:42 +000087// ARM Instruction Predicate Definitions.
88//
89def HasV5T : Predicate<"Subtarget->hasV5TOps()">;
90def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">;
91def HasV6 : Predicate<"Subtarget->hasV6Ops()">;
92def IsThumb : Predicate<"Subtarget->isThumb()">;
93def IsARM : Predicate<"!Subtarget->isThumb()">;
94
Rafael Espindola7bc59bc2006-05-14 22:18:28 +000095//===----------------------------------------------------------------------===//
Evan Chenga8e29892007-01-19 07:51:42 +000096// ARM Flag Definitions.
97
98class RegConstraint<string C> {
99 string Constraints = C;
100}
101
102//===----------------------------------------------------------------------===//
103// ARM specific transformation functions and pattern fragments.
104//
105
106// so_imm_XFORM - Return a so_imm value packed into the format described for
107// so_imm def below.
108def so_imm_XFORM : SDNodeXForm<imm, [{
109 return CurDAG->getTargetConstant(ARM_AM::getSOImmVal(N->getValue()),
110 MVT::i32);
111}]>;
112
113// so_imm_neg_XFORM - Return a so_imm value packed into the format described for
114// so_imm_neg def below.
115def so_imm_neg_XFORM : SDNodeXForm<imm, [{
116 return CurDAG->getTargetConstant(ARM_AM::getSOImmVal(-(int)N->getValue()),
117 MVT::i32);
118}]>;
119
120// so_imm_not_XFORM - Return a so_imm value packed into the format described for
121// so_imm_not def below.
122def so_imm_not_XFORM : SDNodeXForm<imm, [{
123 return CurDAG->getTargetConstant(ARM_AM::getSOImmVal(~(int)N->getValue()),
124 MVT::i32);
125}]>;
126
127// rot_imm predicate - True if the 32-bit immediate is equal to 8, 16, or 24.
128def rot_imm : PatLeaf<(i32 imm), [{
129 int32_t v = (int32_t)N->getValue();
130 return v == 8 || v == 16 || v == 24;
131}]>;
132
133/// imm1_15 predicate - True if the 32-bit immediate is in the range [1,15].
134def imm1_15 : PatLeaf<(i32 imm), [{
135 return (int32_t)N->getValue() >= 1 && (int32_t)N->getValue() < 16;
136}]>;
137
138/// imm16_31 predicate - True if the 32-bit immediate is in the range [16,31].
139def imm16_31 : PatLeaf<(i32 imm), [{
140 return (int32_t)N->getValue() >= 16 && (int32_t)N->getValue() < 32;
141}]>;
142
143def so_imm_neg :
144 PatLeaf<(imm), [{ return ARM_AM::getSOImmVal(-(int)N->getValue()) != -1; }],
145 so_imm_neg_XFORM>;
146
Evan Chenga2515702007-03-19 07:09:02 +0000147def so_imm_not :
Evan Chenga8e29892007-01-19 07:51:42 +0000148 PatLeaf<(imm), [{ return ARM_AM::getSOImmVal(~(int)N->getValue()) != -1; }],
149 so_imm_not_XFORM>;
150
151// sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits.
152def sext_16_node : PatLeaf<(i32 GPR:$a), [{
153 return TLI.ComputeNumSignBits(SDOperand(N,0)) >= 17;
154}]>;
155
156
Evan Chenga8e29892007-01-19 07:51:42 +0000157
158//===----------------------------------------------------------------------===//
159// Operand Definitions.
160//
161
162// Branch target.
163def brtarget : Operand<OtherVT>;
164
Evan Chenga8e29892007-01-19 07:51:42 +0000165// A list of registers separated by comma. Used by load/store multiple.
166def reglist : Operand<i32> {
167 let PrintMethod = "printRegisterList";
168}
169
170// An operand for the CONSTPOOL_ENTRY pseudo-instruction.
171def cpinst_operand : Operand<i32> {
172 let PrintMethod = "printCPInstOperand";
173}
174
175def jtblock_operand : Operand<i32> {
176 let PrintMethod = "printJTBlockOperand";
177}
178
179// Local PC labels.
180def pclabel : Operand<i32> {
181 let PrintMethod = "printPCLabel";
182}
183
184// shifter_operand operands: so_reg and so_imm.
185def so_reg : Operand<i32>, // reg reg imm
186 ComplexPattern<i32, 3, "SelectShifterOperandReg",
187 [shl,srl,sra,rotr]> {
188 let PrintMethod = "printSORegOperand";
189 let MIOperandInfo = (ops GPR, GPR, i32imm);
190}
191
192// so_imm - Match a 32-bit shifter_operand immediate operand, which is an
193// 8-bit immediate rotated by an arbitrary number of bits. so_imm values are
194// represented in the imm field in the same 12-bit form that they are encoded
195// into so_imm instructions: the 8-bit immediate is the least significant bits
196// [bits 0-7], the 4-bit shift amount is the next 4 bits [bits 8-11].
197def so_imm : Operand<i32>,
198 PatLeaf<(imm),
199 [{ return ARM_AM::getSOImmVal(N->getValue()) != -1; }],
200 so_imm_XFORM> {
201 let PrintMethod = "printSOImmOperand";
202}
203
Evan Chengc70d1842007-03-20 08:11:30 +0000204// Break so_imm's up into two pieces. This handles immediates with up to 16
205// bits set in them. This uses so_imm2part to match and so_imm2part_[12] to
206// get the first/second pieces.
207def so_imm2part : Operand<i32>,
208 PatLeaf<(imm),
209 [{ return ARM_AM::isSOImmTwoPartVal((unsigned)N->getValue()); }]> {
210 let PrintMethod = "printSOImm2PartOperand";
211}
212
213def so_imm2part_1 : SDNodeXForm<imm, [{
214 unsigned V = ARM_AM::getSOImmTwoPartFirst((unsigned)N->getValue());
215 return CurDAG->getTargetConstant(ARM_AM::getSOImmVal(V), MVT::i32);
216}]>;
217
218def so_imm2part_2 : SDNodeXForm<imm, [{
219 unsigned V = ARM_AM::getSOImmTwoPartSecond((unsigned)N->getValue());
220 return CurDAG->getTargetConstant(ARM_AM::getSOImmVal(V), MVT::i32);
221}]>;
222
Evan Chenga8e29892007-01-19 07:51:42 +0000223
224// Define ARM specific addressing modes.
225
226// addrmode2 := reg +/- reg shop imm
227// addrmode2 := reg +/- imm12
228//
229def addrmode2 : Operand<i32>,
230 ComplexPattern<i32, 3, "SelectAddrMode2", []> {
231 let PrintMethod = "printAddrMode2Operand";
232 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
233}
234
235def am2offset : Operand<i32>,
236 ComplexPattern<i32, 2, "SelectAddrMode2Offset", []> {
237 let PrintMethod = "printAddrMode2OffsetOperand";
238 let MIOperandInfo = (ops GPR, i32imm);
239}
240
241// addrmode3 := reg +/- reg
242// addrmode3 := reg +/- imm8
243//
244def addrmode3 : Operand<i32>,
245 ComplexPattern<i32, 3, "SelectAddrMode3", []> {
246 let PrintMethod = "printAddrMode3Operand";
247 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
248}
249
250def am3offset : Operand<i32>,
251 ComplexPattern<i32, 2, "SelectAddrMode3Offset", []> {
252 let PrintMethod = "printAddrMode3OffsetOperand";
253 let MIOperandInfo = (ops GPR, i32imm);
254}
255
256// addrmode4 := reg, <mode|W>
257//
258def addrmode4 : Operand<i32>,
259 ComplexPattern<i32, 2, "", []> {
260 let PrintMethod = "printAddrMode4Operand";
261 let MIOperandInfo = (ops GPR, i32imm);
262}
263
264// addrmode5 := reg +/- imm8*4
265//
266def addrmode5 : Operand<i32>,
267 ComplexPattern<i32, 2, "SelectAddrMode5", []> {
268 let PrintMethod = "printAddrMode5Operand";
269 let MIOperandInfo = (ops GPR, i32imm);
270}
271
272// addrmodepc := pc + reg
273//
274def addrmodepc : Operand<i32>,
275 ComplexPattern<i32, 2, "SelectAddrModePC", []> {
276 let PrintMethod = "printAddrModePCOperand";
277 let MIOperandInfo = (ops GPR, i32imm);
278}
279
Evan Cheng42d712b2007-05-08 21:08:43 +0000280// ARM branch / cmov condition code operand.
Evan Cheng5ada1992007-05-16 20:50:01 +0000281def ccop : Operand<i32> {
Evan Cheng42d712b2007-05-08 21:08:43 +0000282 let PrintMethod = "printPredicateOperand";
283}
284
285// ARM Predicate operand. Default to 14 = always (AL).
286def pred : PredicateOperand<i32, (ops i32imm), (ops (i32 14))> {
287 let PrintMethod = "printPredicateOperand";
288}
289
Evan Chenga8e29892007-01-19 07:51:42 +0000290//===----------------------------------------------------------------------===//
291// ARM Instruction flags. These need to match ARMInstrInfo.h.
292//
293
294// Addressing mode.
295class AddrMode<bits<4> val> {
296 bits<4> Value = val;
297}
298def AddrModeNone : AddrMode<0>;
299def AddrMode1 : AddrMode<1>;
300def AddrMode2 : AddrMode<2>;
301def AddrMode3 : AddrMode<3>;
302def AddrMode4 : AddrMode<4>;
303def AddrMode5 : AddrMode<5>;
304def AddrModeT1 : AddrMode<6>;
305def AddrModeT2 : AddrMode<7>;
306def AddrModeT4 : AddrMode<8>;
307def AddrModeTs : AddrMode<9>;
308
309// Instruction size.
310class SizeFlagVal<bits<3> val> {
311 bits<3> Value = val;
312}
313def SizeInvalid : SizeFlagVal<0>; // Unset.
314def SizeSpecial : SizeFlagVal<1>; // Pseudo or special.
315def Size8Bytes : SizeFlagVal<2>;
316def Size4Bytes : SizeFlagVal<3>;
317def Size2Bytes : SizeFlagVal<4>;
318
319// Load / store index mode.
320class IndexMode<bits<2> val> {
321 bits<2> Value = val;
322}
323def IndexModeNone : IndexMode<0>;
324def IndexModePre : IndexMode<1>;
325def IndexModePost : IndexMode<2>;
326
327//===----------------------------------------------------------------------===//
328// ARM Instruction templates.
329//
330
331// ARMPat - Same as Pat<>, but requires that the compiler be in ARM mode.
332class ARMPat<dag pattern, dag result> : Pat<pattern, result> {
333 list<Predicate> Predicates = [IsARM];
334}
Evan Cheng34b12d22007-01-19 20:27:35 +0000335class ARMV5TEPat<dag pattern, dag result> : Pat<pattern, result> {
336 list<Predicate> Predicates = [IsARM, HasV5TE];
337}
Evan Chenga8e29892007-01-19 07:51:42 +0000338class ARMV6Pat<dag pattern, dag result> : Pat<pattern, result> {
339 list<Predicate> Predicates = [IsARM, HasV6];
340}
341
Evan Chenga8e29892007-01-19 07:51:42 +0000342class InstARM<bits<4> opcod, AddrMode am, SizeFlagVal sz, IndexMode im,
Evan Cheng44bec522007-05-15 01:29:07 +0000343 string cstr>
Evan Chenga8e29892007-01-19 07:51:42 +0000344 : Instruction {
Rafael Espindola7bc59bc2006-05-14 22:18:28 +0000345 let Namespace = "ARM";
346
Evan Chenga8e29892007-01-19 07:51:42 +0000347 bits<4> Opcode = opcod;
348 AddrMode AM = am;
349 bits<4> AddrModeBits = AM.Value;
350
351 SizeFlagVal SZ = sz;
352 bits<3> SizeFlag = SZ.Value;
353
354 IndexMode IM = im;
355 bits<2> IndexModeBits = IM.Value;
356
Evan Chenga8e29892007-01-19 07:51:42 +0000357 let Constraints = cstr;
358}
359
360class PseudoInst<dag ops, string asm, list<dag> pattern>
Evan Cheng44bec522007-05-15 01:29:07 +0000361 : InstARM<0, AddrModeNone, SizeSpecial, IndexModeNone, ""> {
362 let OperandList = ops;
363 let AsmString = asm;
Rafael Espindola7bc59bc2006-05-14 22:18:28 +0000364 let Pattern = pattern;
365}
366
Evan Cheng5ada1992007-05-16 20:50:01 +0000367// Almost all ARM instructions are predicable.
Evan Cheng44bec522007-05-15 01:29:07 +0000368class I<dag oprnds, AddrMode am, SizeFlagVal sz, IndexMode im,
369 string opc, string asm, string cstr, list<dag> pattern>
Evan Chenga8e29892007-01-19 07:51:42 +0000370 // FIXME: Set all opcodes to 0 for now.
Evan Cheng44bec522007-05-15 01:29:07 +0000371 : InstARM<0, am, sz, im, cstr> {
372 let OperandList = !con(oprnds, (ops pred:$p));
373 let AsmString = !strconcat(opc, !strconcat("$p", asm));
Evan Chenga8e29892007-01-19 07:51:42 +0000374 let Pattern = pattern;
375 list<Predicate> Predicates = [IsARM];
376}
Rafael Espindola15a6c3e2006-10-16 17:57:20 +0000377
Evan Cheng44bec522007-05-15 01:29:07 +0000378class AI<dag ops, string opc, string asm, list<dag> pattern>
379 : I<ops, AddrModeNone, Size4Bytes, IndexModeNone, opc, asm, "", pattern>;
380class AI1<dag ops, string opc, string asm, list<dag> pattern>
381 : I<ops, AddrMode1, Size4Bytes, IndexModeNone, opc, asm, "", pattern>;
382class AI2<dag ops, string opc, string asm, list<dag> pattern>
383 : I<ops, AddrMode2, Size4Bytes, IndexModeNone, opc, asm, "", pattern>;
384class AI3<dag ops, string opc, string asm, list<dag> pattern>
385 : I<ops, AddrMode3, Size4Bytes, IndexModeNone, opc, asm, "", pattern>;
386class AI4<dag ops, string opc, string asm, list<dag> pattern>
387 : I<ops, AddrMode4, Size4Bytes, IndexModeNone, opc, asm, "", pattern>;
388class AI1x2<dag ops, string opc, string asm, list<dag> pattern>
389 : I<ops, AddrMode1, Size8Bytes, IndexModeNone, opc, asm, "", pattern>;
Rafael Espindolaa6f149d2006-10-16 18:32:36 +0000390
Evan Chenga8e29892007-01-19 07:51:42 +0000391// Pre-indexed ops
Evan Cheng44bec522007-05-15 01:29:07 +0000392class AI2pr<dag ops, string opc, string asm, string cstr, list<dag> pattern>
393 : I<ops, AddrMode2, Size4Bytes, IndexModePre, opc, asm, cstr, pattern>;
394class AI3pr<dag ops, string opc, string asm, string cstr, list<dag> pattern>
395 : I<ops, AddrMode3, Size4Bytes, IndexModePre, opc, asm, cstr, pattern>;
Rafael Espindola27e469e2006-10-16 18:39:22 +0000396
Evan Chenga8e29892007-01-19 07:51:42 +0000397// Post-indexed ops
Evan Cheng44bec522007-05-15 01:29:07 +0000398class AI2po<dag ops, string opc, string asm, string cstr, list<dag> pattern>
399 : I<ops, AddrMode2, Size4Bytes, IndexModePost, opc, asm, cstr, pattern>;
400class AI3po<dag ops, string opc, string asm, string cstr, list<dag> pattern>
401 : I<ops, AddrMode3, Size4Bytes, IndexModePost, opc, asm, cstr, pattern>;
Rafael Espindola04d88ff2006-10-17 20:45:22 +0000402
Evan Chenga8e29892007-01-19 07:51:42 +0000403// BR_JT instructions
Evan Cheng44bec522007-05-15 01:29:07 +0000404class JTI<dag ops, string opc, string asm, list<dag> pattern>
405 : I<ops, AddrModeNone, SizeSpecial, IndexModeNone, opc, asm, "", pattern>;
406class JTI1<dag ops, string opc, string asm, list<dag> pattern>
407 : I<ops, AddrMode1, SizeSpecial, IndexModeNone, opc, asm, "", pattern>;
408class JTI2<dag ops, string opc, string asm, list<dag> pattern>
409 : I<ops, AddrMode2, SizeSpecial, IndexModeNone, opc, asm, "", pattern>;
Rafael Espindola04d88ff2006-10-17 20:45:22 +0000410
Evan Chenga8e29892007-01-19 07:51:42 +0000411
412class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>;
413class UnOpFrag <dag res> : PatFrag<(ops node:$Src), res>;
414
415
416/// AI1_bin_irs - Defines a set of (op r, {so_imm|r|so_reg}) patterns for a
417/// binop that produces a value.
418multiclass AI1_bin_irs<string opc, PatFrag opnode> {
419 def ri : AI1<(ops GPR:$dst, GPR:$a, so_imm:$b),
Evan Cheng44bec522007-05-15 01:29:07 +0000420 opc, " $dst, $a, $b",
Evan Chenga8e29892007-01-19 07:51:42 +0000421 [(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]>;
422 def rr : AI1<(ops GPR:$dst, GPR:$a, GPR:$b),
Evan Cheng44bec522007-05-15 01:29:07 +0000423 opc, " $dst, $a, $b",
Evan Chenga8e29892007-01-19 07:51:42 +0000424 [(set GPR:$dst, (opnode GPR:$a, GPR:$b))]>;
425 def rs : AI1<(ops GPR:$dst, GPR:$a, so_reg:$b),
Evan Cheng44bec522007-05-15 01:29:07 +0000426 opc, " $dst, $a, $b",
Evan Chenga8e29892007-01-19 07:51:42 +0000427 [(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]>;
428}
429
430/// AI1_bin0_irs - Defines a set of (op r, {so_imm|r|so_reg}) patterns.
431/// Similar to AI1_bin_irs except the instruction does not produce a result.
432multiclass AI1_bin0_irs<string opc, PatFrag opnode> {
433 def ri : AI1<(ops GPR:$a, so_imm:$b),
Evan Cheng44bec522007-05-15 01:29:07 +0000434 opc, " $a, $b",
Evan Chenga8e29892007-01-19 07:51:42 +0000435 [(opnode GPR:$a, so_imm:$b)]>;
436 def rr : AI1<(ops GPR:$a, GPR:$b),
Evan Cheng44bec522007-05-15 01:29:07 +0000437 opc, " $a, $b",
Evan Chenga8e29892007-01-19 07:51:42 +0000438 [(opnode GPR:$a, GPR:$b)]>;
439 def rs : AI1<(ops GPR:$a, so_reg:$b),
Evan Cheng44bec522007-05-15 01:29:07 +0000440 opc, " $a, $b",
Evan Chenga8e29892007-01-19 07:51:42 +0000441 [(opnode GPR:$a, so_reg:$b)]>;
442}
443
444/// AI1_bin_is - Defines a set of (op r, {so_imm|so_reg}) patterns for a binop.
445multiclass AI1_bin_is<string opc, PatFrag opnode> {
446 def ri : AI1<(ops GPR:$dst, GPR:$a, so_imm:$b),
Evan Cheng44bec522007-05-15 01:29:07 +0000447 opc, " $dst, $a, $b",
Evan Chenga8e29892007-01-19 07:51:42 +0000448 [(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]>;
449 def rs : AI1<(ops GPR:$dst, GPR:$a, so_reg:$b),
Evan Cheng44bec522007-05-15 01:29:07 +0000450 opc, " $dst, $a, $b",
Evan Chenga8e29892007-01-19 07:51:42 +0000451 [(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]>;
452}
453
454/// AI1_unary_irs - Defines a set of (op {so_imm|r|so_reg}) patterns for unary
455/// ops.
456multiclass AI1_unary_irs<string opc, PatFrag opnode> {
457 def i : AI1<(ops GPR:$dst, so_imm:$a),
Evan Cheng44bec522007-05-15 01:29:07 +0000458 opc, " $dst, $a",
Evan Chenga8e29892007-01-19 07:51:42 +0000459 [(set GPR:$dst, (opnode so_imm:$a))]>;
460 def r : AI1<(ops GPR:$dst, GPR:$a),
Evan Cheng44bec522007-05-15 01:29:07 +0000461 opc, " $dst, $a",
Evan Chenga8e29892007-01-19 07:51:42 +0000462 [(set GPR:$dst, (opnode GPR:$a))]>;
463 def s : AI1<(ops GPR:$dst, so_reg:$a),
Evan Cheng44bec522007-05-15 01:29:07 +0000464 opc, " $dst, $a",
Evan Chenga8e29892007-01-19 07:51:42 +0000465 [(set GPR:$dst, (opnode so_reg:$a))]>;
466}
467
468/// AI_unary_rrot - A unary operation with two forms: one whose operand is a
469/// register and one whose operand is a register rotated by 8/16/24.
470multiclass AI_unary_rrot<string opc, PatFrag opnode> {
471 def r : AI<(ops GPR:$dst, GPR:$Src),
Evan Cheng44bec522007-05-15 01:29:07 +0000472 opc, " $dst, $Src",
Evan Chenga8e29892007-01-19 07:51:42 +0000473 [(set GPR:$dst, (opnode GPR:$Src))]>, Requires<[IsARM, HasV6]>;
474 def r_rot : AI<(ops GPR:$dst, GPR:$Src, i32imm:$rot),
Evan Cheng44bec522007-05-15 01:29:07 +0000475 opc, " $dst, $Src, ror $rot",
Evan Chenga8e29892007-01-19 07:51:42 +0000476 [(set GPR:$dst, (opnode (rotr GPR:$Src, rot_imm:$rot)))]>,
477 Requires<[IsARM, HasV6]>;
478}
479
480/// AI_bin_rrot - A binary operation with two forms: one whose operand is a
481/// register and one whose operand is a register rotated by 8/16/24.
482multiclass AI_bin_rrot<string opc, PatFrag opnode> {
483 def rr : AI<(ops GPR:$dst, GPR:$LHS, GPR:$RHS),
Evan Cheng44bec522007-05-15 01:29:07 +0000484 opc, " $dst, $LHS, $RHS",
Evan Chenga8e29892007-01-19 07:51:42 +0000485 [(set GPR:$dst, (opnode GPR:$LHS, GPR:$RHS))]>,
486 Requires<[IsARM, HasV6]>;
487 def rr_rot : AI<(ops GPR:$dst, GPR:$LHS, GPR:$RHS, i32imm:$rot),
Evan Cheng44bec522007-05-15 01:29:07 +0000488 opc, " $dst, $LHS, $RHS, ror $rot",
Evan Chenga8e29892007-01-19 07:51:42 +0000489 [(set GPR:$dst, (opnode GPR:$LHS,
490 (rotr GPR:$RHS, rot_imm:$rot)))]>,
491 Requires<[IsARM, HasV6]>;
492}
493
Evan Cheng44bec522007-05-15 01:29:07 +0000494// Special cases.
495class XI<dag oprnds, AddrMode am, SizeFlagVal sz, IndexMode im,
496 string asm, string cstr, list<dag> pattern>
497 // FIXME: Set all opcodes to 0 for now.
498 : InstARM<0, am, sz, im, cstr> {
499 let OperandList = oprnds;
500 let AsmString = asm;
501 let Pattern = pattern;
502 list<Predicate> Predicates = [IsARM];
503}
504
505class AXI<dag ops, string asm, list<dag> pattern>
506 : XI<ops, AddrModeNone, Size4Bytes, IndexModeNone, asm, "", pattern>;
507class AXI1<dag ops, string asm, list<dag> pattern>
508 : XI<ops, AddrMode1, Size4Bytes, IndexModeNone, asm, "", pattern>;
509class AXI2<dag ops, string asm, list<dag> pattern>
510 : XI<ops, AddrMode2, Size4Bytes, IndexModeNone, asm, "", pattern>;
Dale Johannesenf23b8cf2007-05-21 22:42:04 +0000511class AXI3<dag ops, string asm, list<dag> pattern>
512 : XI<ops, AddrMode3, Size4Bytes, IndexModeNone, asm, "", pattern>;
Evan Cheng44bec522007-05-15 01:29:07 +0000513class AXI4<dag ops, string asm, list<dag> pattern>
514 : XI<ops, AddrMode4, Size4Bytes, IndexModeNone, asm, "", pattern>;
515
516class AXIx2<dag ops, string asm, list<dag> pattern>
517 : XI<ops, AddrModeNone, Size8Bytes, IndexModeNone, asm, "", pattern>;
518
Rafael Espindola90057aa2006-10-16 18:18:14 +0000519
Rafael Espindola15a6c3e2006-10-16 17:57:20 +0000520//===----------------------------------------------------------------------===//
521// Instructions
522//===----------------------------------------------------------------------===//
523
Evan Chenga8e29892007-01-19 07:51:42 +0000524//===----------------------------------------------------------------------===//
525// Miscellaneous Instructions.
526//
527def IMPLICIT_DEF_GPR :
Evan Cheng44bec522007-05-15 01:29:07 +0000528PseudoInst<(ops GPR:$rD, pred:$p),
Evan Chenga8e29892007-01-19 07:51:42 +0000529 "@ IMPLICIT_DEF_GPR $rD",
530 [(set GPR:$rD, (undef))]>;
Rafael Espindola687bc492006-08-24 13:45:55 +0000531
Rafael Espindola6f602de2006-08-24 16:13:15 +0000532
Evan Chenga8e29892007-01-19 07:51:42 +0000533/// CONSTPOOL_ENTRY - This instruction represents a floating constant pool in
534/// the function. The first operand is the ID# for this instruction, the second
535/// is the index into the MachineConstantPool that this is, the third is the
536/// size in bytes of this constant pool entry.
537def CONSTPOOL_ENTRY :
538PseudoInst<(ops cpinst_operand:$instid, cpinst_operand:$cpidx, i32imm:$size),
539 "${instid:label} ${cpidx:cpentry}", []>;
Rafael Espindola7bc59bc2006-05-14 22:18:28 +0000540
Evan Chenga8e29892007-01-19 07:51:42 +0000541def ADJCALLSTACKUP :
Evan Cheng44bec522007-05-15 01:29:07 +0000542PseudoInst<(ops i32imm:$amt, pred:$p),
Evan Chenga8e29892007-01-19 07:51:42 +0000543 "@ ADJCALLSTACKUP $amt",
544 [(ARMcallseq_end imm:$amt)]>, Imp<[SP],[SP]>;
Rafael Espindolacdda88c2006-08-24 17:19:08 +0000545
Evan Chenga8e29892007-01-19 07:51:42 +0000546def ADJCALLSTACKDOWN :
Evan Cheng44bec522007-05-15 01:29:07 +0000547PseudoInst<(ops i32imm:$amt, pred:$p),
Evan Chenga8e29892007-01-19 07:51:42 +0000548 "@ ADJCALLSTACKDOWN $amt",
549 [(ARMcallseq_start imm:$amt)]>, Imp<[SP],[SP]>;
Rafael Espindola3c000bf2006-08-21 22:00:32 +0000550
Evan Chenga8e29892007-01-19 07:51:42 +0000551def DWARF_LOC :
552PseudoInst<(ops i32imm:$line, i32imm:$col, i32imm:$file),
553 ".loc $file, $line, $col",
554 [(dwarf_loc (i32 imm:$line), (i32 imm:$col), (i32 imm:$file))]>;
Rafael Espindola4b20fbc2006-10-10 12:56:00 +0000555
Evan Cheng44bec522007-05-15 01:29:07 +0000556def PICADD : AXI1<(ops GPR:$dst, GPR:$a, pclabel:$cp, pred:$p),
557 "$cp:\n\tadd$p $dst, pc, $a",
558 [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>;
Dale Johannesen86d40692007-05-21 22:14:33 +0000559
560let isLoad = 1, AddedComplexity = 10 in {
561def PICLD : AXI2<(ops GPR:$dst, addrmodepc:$addr, pred:$p),
Evan Cheng44bec522007-05-15 01:29:07 +0000562 "${addr:label}:\n\tldr$p $dst, $addr",
Evan Chenga8e29892007-01-19 07:51:42 +0000563 [(set GPR:$dst, (load addrmodepc:$addr))]>;
Rafael Espindola84b19be2006-07-16 01:02:57 +0000564
Dale Johannesenf23b8cf2007-05-21 22:42:04 +0000565def PICLDZH : AXI3<(ops GPR:$dst, addrmodepc:$addr, pred:$p),
Dale Johannesen86d40692007-05-21 22:14:33 +0000566 "${addr:label}:\n\tldr${p}h $dst, $addr",
567 [(set GPR:$dst, (zextloadi16 addrmodepc:$addr))]>;
568
569def PICLDZB : AXI2<(ops GPR:$dst, addrmodepc:$addr, pred:$p),
570 "${addr:label}:\n\tldr${p}b $dst, $addr",
571 [(set GPR:$dst, (zextloadi8 addrmodepc:$addr))]>;
572
Dale Johannesenf23b8cf2007-05-21 22:42:04 +0000573def PICLDH : AXI3<(ops GPR:$dst, addrmodepc:$addr, pred:$p),
Dale Johannesen86d40692007-05-21 22:14:33 +0000574 "${addr:label}:\n\tldr${p}h $dst, $addr",
575 [(set GPR:$dst, (extloadi16 addrmodepc:$addr))]>;
576
577def PICLDB : AXI2<(ops GPR:$dst, addrmodepc:$addr, pred:$p),
578 "${addr:label}:\n\tldr${p}b $dst, $addr",
579 [(set GPR:$dst, (extloadi8 addrmodepc:$addr))]>;
580
Dale Johannesenf23b8cf2007-05-21 22:42:04 +0000581def PICLDSH : AXI3<(ops GPR:$dst, addrmodepc:$addr, pred:$p),
Dale Johannesen86d40692007-05-21 22:14:33 +0000582 "${addr:label}:\n\tldr${p}sh $dst, $addr",
583 [(set GPR:$dst, (sextloadi16 addrmodepc:$addr))]>;
584
Dale Johannesenf23b8cf2007-05-21 22:42:04 +0000585def PICLDSB : AXI3<(ops GPR:$dst, addrmodepc:$addr, pred:$p),
Dale Johannesen86d40692007-05-21 22:14:33 +0000586 "${addr:label}:\n\tldr${p}sb $dst, $addr",
587 [(set GPR:$dst, (sextloadi8 addrmodepc:$addr))]>;
588}
589let isStore = 1, AddedComplexity = 10 in {
590def PICSTR : AXI2<(ops GPR:$src, addrmodepc:$addr, pred:$p),
591 "${addr:label}:\n\tstr$p $src, $addr",
592 [(store GPR:$src, addrmodepc:$addr)]>;
593
Dale Johannesenf23b8cf2007-05-21 22:42:04 +0000594def PICSTRH : AXI3<(ops GPR:$src, addrmodepc:$addr, pred:$p),
Dale Johannesen86d40692007-05-21 22:14:33 +0000595 "${addr:label}:\n\tstr${p}h $src, $addr",
596 [(truncstorei16 GPR:$src, addrmodepc:$addr)]>;
597
598def PICSTRB : AXI2<(ops GPR:$src, addrmodepc:$addr, pred:$p),
599 "${addr:label}:\n\tstr${p}b $src, $addr",
600 [(truncstorei8 GPR:$src, addrmodepc:$addr)]>;
601}
602
Evan Chenga8e29892007-01-19 07:51:42 +0000603//===----------------------------------------------------------------------===//
604// Control Flow Instructions.
605//
Rafael Espindola9e071f02006-10-02 19:30:56 +0000606
Evan Chenga8e29892007-01-19 07:51:42 +0000607let isReturn = 1, isTerminator = 1 in
Evan Cheng44bec522007-05-15 01:29:07 +0000608 def BX_RET : AI<(ops), "bx", " lr", [(ARMretflag)]>;
Rafael Espindola27185192006-09-29 21:20:16 +0000609
Evan Chenga8e29892007-01-19 07:51:42 +0000610// FIXME: remove when we have a way to marking a MI with these properties.
611let isLoad = 1, isReturn = 1, isTerminator = 1 in
Evan Cheng44bec522007-05-15 01:29:07 +0000612 def LDM_RET : AXI4<(ops addrmode4:$addr, pred:$p, reglist:$dst1, variable_ops),
613 "ldm${p}${addr:submode} $addr, $dst1",
Evan Chenga8e29892007-01-19 07:51:42 +0000614 []>;
Rafael Espindolaa2845842006-10-05 16:48:49 +0000615
Evan Chenga8e29892007-01-19 07:51:42 +0000616let isCall = 1, noResults = 1,
617 Defs = [R0, R1, R2, R3, R12, LR,
618 D0, D1, D2, D3, D4, D5, D6, D7] in {
Evan Chengdcc50a42007-05-18 01:53:54 +0000619 def BL : AXI<(ops i32imm:$func, variable_ops),
620 "bl ${func:call}",
Evan Cheng44bec522007-05-15 01:29:07 +0000621 [(ARMcall tglobaladdr:$func)]>;
Evan Chenga8e29892007-01-19 07:51:42 +0000622 // ARMv5T and above
Evan Chengdcc50a42007-05-18 01:53:54 +0000623 def BLX : AXI<(ops GPR:$dst, variable_ops),
624 "blx $dst",
Evan Cheng44bec522007-05-15 01:29:07 +0000625 [(ARMcall GPR:$dst)]>, Requires<[IsARM, HasV5T]>;
Lauro Ramos Venancio64c88d72007-03-20 17:57:23 +0000626 let Uses = [LR] in {
627 // ARMv4T
Evan Chengdcc50a42007-05-18 01:53:54 +0000628 def BX : AXIx2<(ops GPR:$dst, variable_ops),
629 "mov lr, pc\n\tbx $dst",
Lauro Ramos Venanciob8a93a42007-03-27 16:19:21 +0000630 [(ARMcall_nolink GPR:$dst)]>;
Lauro Ramos Venancio64c88d72007-03-20 17:57:23 +0000631 }
Rafael Espindola35574632006-07-18 17:00:30 +0000632}
Rafael Espindoladc124a22006-05-18 21:45:49 +0000633
Evan Chengaeafca02007-05-16 07:45:54 +0000634let isBranch = 1, isTerminator = 1, noResults = 1 in {
Evan Cheng5ada1992007-05-16 20:50:01 +0000635 // B is "predicable" since it can be xformed into a Bcc.
Evan Chengaeafca02007-05-16 07:45:54 +0000636 let isBarrier = 1 in {
Evan Cheng5ada1992007-05-16 20:50:01 +0000637 let isPredicable = 1 in
638 def B : AXI<(ops brtarget:$dst), "b $dst",
639 [(br bb:$dst)]>;
Evan Cheng44bec522007-05-15 01:29:07 +0000640
Evan Chenga8e29892007-01-19 07:51:42 +0000641 def BR_JTr : JTI<(ops GPR:$dst, jtblock_operand:$jt, i32imm:$id),
Evan Cheng44bec522007-05-15 01:29:07 +0000642 "mov", " pc, $dst \n$jt",
Evan Chenga8e29892007-01-19 07:51:42 +0000643 [(ARMbrjt GPR:$dst, tjumptable:$jt, imm:$id)]>;
644 def BR_JTm : JTI2<(ops addrmode2:$dst, jtblock_operand:$jt, i32imm:$id),
Evan Cheng44bec522007-05-15 01:29:07 +0000645 "ldr", " pc, $dst \n$jt",
Evan Chenga8e29892007-01-19 07:51:42 +0000646 [(ARMbrjt (i32 (load addrmode2:$dst)), tjumptable:$jt,
647 imm:$id)]>;
648 def BR_JTadd : JTI1<(ops GPR:$dst, GPR:$idx, jtblock_operand:$jt, i32imm:$id),
Evan Cheng44bec522007-05-15 01:29:07 +0000649 "add", " pc, $dst, $idx \n$jt",
Evan Chenga8e29892007-01-19 07:51:42 +0000650 [(ARMbrjt (add GPR:$dst, GPR:$idx), tjumptable:$jt,
651 imm:$id)]>;
Evan Chengaeafca02007-05-16 07:45:54 +0000652 }
653
654 def Bcc : AXI<(ops brtarget:$dst, ccop:$cc), "b$cc $dst",
655 [(ARMbrcond bb:$dst, imm:$cc)]>;
Rafael Espindola1ed3af12006-08-01 18:53:10 +0000656}
Rafael Espindola84b19be2006-07-16 01:02:57 +0000657
Evan Chenga8e29892007-01-19 07:51:42 +0000658//===----------------------------------------------------------------------===//
659// Load / store Instructions.
660//
Rafael Espindola82c678b2006-10-16 17:17:22 +0000661
Evan Chenga8e29892007-01-19 07:51:42 +0000662// Load
663let isLoad = 1 in {
664def LDR : AI2<(ops GPR:$dst, addrmode2:$addr),
Evan Cheng44bec522007-05-15 01:29:07 +0000665 "ldr", " $dst, $addr",
Evan Chenga8e29892007-01-19 07:51:42 +0000666 [(set GPR:$dst, (load addrmode2:$addr))]>;
Rafael Espindola82c678b2006-10-16 17:17:22 +0000667
Evan Chengfa775d02007-03-19 07:20:03 +0000668// Special LDR for loads from non-pc-relative constpools.
669let isReMaterializable = 1 in
670def LDRcp : AI2<(ops GPR:$dst, addrmode2:$addr),
Evan Cheng44bec522007-05-15 01:29:07 +0000671 "ldr", " $dst, $addr", []>;
Evan Chengfa775d02007-03-19 07:20:03 +0000672
Evan Chenga8e29892007-01-19 07:51:42 +0000673// Loads with zero extension
674def LDRH : AI3<(ops GPR:$dst, addrmode3:$addr),
Evan Cheng44bec522007-05-15 01:29:07 +0000675 "ldrh", " $dst, $addr",
Evan Chenga8e29892007-01-19 07:51:42 +0000676 [(set GPR:$dst, (zextloadi16 addrmode3:$addr))]>;
Rafael Espindola82c678b2006-10-16 17:17:22 +0000677
Evan Chenga8e29892007-01-19 07:51:42 +0000678def LDRB : AI2<(ops GPR:$dst, addrmode2:$addr),
Evan Cheng44bec522007-05-15 01:29:07 +0000679 "ldrb", " $dst, $addr",
Evan Chenga8e29892007-01-19 07:51:42 +0000680 [(set GPR:$dst, (zextloadi8 addrmode2:$addr))]>;
Rafael Espindola82c678b2006-10-16 17:17:22 +0000681
Evan Chenga8e29892007-01-19 07:51:42 +0000682// Loads with sign extension
683def LDRSH : AI3<(ops GPR:$dst, addrmode3:$addr),
Evan Cheng44bec522007-05-15 01:29:07 +0000684 "ldrsh", " $dst, $addr",
Evan Chenga8e29892007-01-19 07:51:42 +0000685 [(set GPR:$dst, (sextloadi16 addrmode3:$addr))]>;
Rafael Espindola7bc59bc2006-05-14 22:18:28 +0000686
Evan Chenga8e29892007-01-19 07:51:42 +0000687def LDRSB : AI3<(ops GPR:$dst, addrmode3:$addr),
Evan Cheng44bec522007-05-15 01:29:07 +0000688 "ldrsb", " $dst, $addr",
Evan Chenga8e29892007-01-19 07:51:42 +0000689 [(set GPR:$dst, (sextloadi8 addrmode3:$addr))]>;
Rafael Espindolac391d162006-10-23 20:34:27 +0000690
Evan Chenga8e29892007-01-19 07:51:42 +0000691// Load doubleword
692def LDRD : AI3<(ops GPR:$dst, addrmode3:$addr),
Evan Cheng44bec522007-05-15 01:29:07 +0000693 "ldrd", " $dst, $addr",
Evan Chenga8e29892007-01-19 07:51:42 +0000694 []>, Requires<[IsARM, HasV5T]>;
Rafael Espindolac391d162006-10-23 20:34:27 +0000695
Evan Chenga8e29892007-01-19 07:51:42 +0000696// Indexed loads
697def LDR_PRE : AI2pr<(ops GPR:$dst, GPR:$base_wb, addrmode2:$addr),
Evan Cheng44bec522007-05-15 01:29:07 +0000698 "ldr", " $dst, $addr!", "$addr.base = $base_wb", []>;
Rafael Espindoladc124a22006-05-18 21:45:49 +0000699
Evan Chenga8e29892007-01-19 07:51:42 +0000700def LDR_POST : AI2po<(ops GPR:$dst, GPR:$base_wb, GPR:$base, am2offset:$offset),
Evan Cheng44bec522007-05-15 01:29:07 +0000701 "ldr", " $dst, [$base], $offset", "$base = $base_wb", []>;
Rafael Espindola450856d2006-12-12 00:37:38 +0000702
Evan Chenga8e29892007-01-19 07:51:42 +0000703def LDRH_PRE : AI3pr<(ops GPR:$dst, GPR:$base_wb, addrmode3:$addr),
Evan Cheng44bec522007-05-15 01:29:07 +0000704 "ldrh", " $dst, $addr!", "$addr.base = $base_wb", []>;
Rafael Espindola4e307642006-09-08 16:59:47 +0000705
Evan Chenga8e29892007-01-19 07:51:42 +0000706def LDRH_POST : AI3po<(ops GPR:$dst, GPR:$base_wb, GPR:$base,am3offset:$offset),
Evan Cheng44bec522007-05-15 01:29:07 +0000707 "ldrh", " $dst, [$base], $offset", "$base = $base_wb", []>;
Lauro Ramos Venancio301009a2006-12-28 13:11:14 +0000708
Evan Chenga8e29892007-01-19 07:51:42 +0000709def LDRB_PRE : AI2pr<(ops GPR:$dst, GPR:$base_wb, addrmode2:$addr),
Evan Cheng44bec522007-05-15 01:29:07 +0000710 "ldrb", " $dst, $addr!", "$addr.base = $base_wb", []>;
Lauro Ramos Venancio301009a2006-12-28 13:11:14 +0000711
Evan Chenga8e29892007-01-19 07:51:42 +0000712def LDRB_POST : AI2po<(ops GPR:$dst, GPR:$base_wb, GPR:$base,am2offset:$offset),
Evan Cheng44bec522007-05-15 01:29:07 +0000713 "ldrb", " $dst, [$base], $offset", "$base = $base_wb", []>;
Evan Chenga8e29892007-01-19 07:51:42 +0000714
715def LDRSH_PRE : AI3pr<(ops GPR:$dst, GPR:$base_wb, addrmode3:$addr),
Evan Cheng44bec522007-05-15 01:29:07 +0000716 "ldrsh", " $dst, $addr!", "$addr.base = $base_wb", []>;
Evan Chenga8e29892007-01-19 07:51:42 +0000717
718def LDRSH_POST: AI3po<(ops GPR:$dst, GPR:$base_wb, GPR:$base,am3offset:$offset),
Evan Cheng44bec522007-05-15 01:29:07 +0000719 "ldrsh", " $dst, [$base], $offset", "$base = $base_wb", []>;
Evan Chenga8e29892007-01-19 07:51:42 +0000720
721def LDRSB_PRE : AI3pr<(ops GPR:$dst, GPR:$base_wb, addrmode3:$addr),
Evan Cheng44bec522007-05-15 01:29:07 +0000722 "ldrsb", " $dst, $addr!", "$addr.base = $base_wb", []>;
Evan Chenga8e29892007-01-19 07:51:42 +0000723
724def LDRSB_POST: AI3po<(ops GPR:$dst, GPR:$base_wb, GPR:$base,am3offset:$offset),
Evan Cheng44bec522007-05-15 01:29:07 +0000725 "ldrsb", " $dst, [$base], $offset", "$base = $base_wb", []>;
Evan Chenga8e29892007-01-19 07:51:42 +0000726} // isLoad
727
728// Store
729let isStore = 1 in {
730def STR : AI2<(ops GPR:$src, addrmode2:$addr),
Evan Cheng44bec522007-05-15 01:29:07 +0000731 "str", " $src, $addr",
Evan Chenga8e29892007-01-19 07:51:42 +0000732 [(store GPR:$src, addrmode2:$addr)]>;
733
734// Stores with truncate
735def STRH : AI3<(ops GPR:$src, addrmode3:$addr),
Evan Cheng44bec522007-05-15 01:29:07 +0000736 "strh", " $src, $addr",
Evan Chenga8e29892007-01-19 07:51:42 +0000737 [(truncstorei16 GPR:$src, addrmode3:$addr)]>;
738
739def STRB : AI2<(ops GPR:$src, addrmode2:$addr),
Evan Cheng44bec522007-05-15 01:29:07 +0000740 "strb", " $src, $addr",
Evan Chenga8e29892007-01-19 07:51:42 +0000741 [(truncstorei8 GPR:$src, addrmode2:$addr)]>;
742
743// Store doubleword
744def STRD : AI3<(ops GPR:$src, addrmode3:$addr),
Evan Cheng44bec522007-05-15 01:29:07 +0000745 "strd", " $src, $addr",
Evan Chenga8e29892007-01-19 07:51:42 +0000746 []>, Requires<[IsARM, HasV5T]>;
747
748// Indexed stores
749def STR_PRE : AI2pr<(ops GPR:$base_wb, GPR:$src, GPR:$base, am2offset:$offset),
Evan Cheng44bec522007-05-15 01:29:07 +0000750 "str", " $src, [$base, $offset]!", "$base = $base_wb",
Evan Chenga8e29892007-01-19 07:51:42 +0000751 [(set GPR:$base_wb,
752 (pre_store GPR:$src, GPR:$base, am2offset:$offset))]>;
753
754def STR_POST : AI2po<(ops GPR:$base_wb, GPR:$src, GPR:$base,am2offset:$offset),
Evan Cheng44bec522007-05-15 01:29:07 +0000755 "str", " $src, [$base], $offset", "$base = $base_wb",
Evan Chenga8e29892007-01-19 07:51:42 +0000756 [(set GPR:$base_wb,
757 (post_store GPR:$src, GPR:$base, am2offset:$offset))]>;
758
759def STRH_PRE : AI3pr<(ops GPR:$base_wb, GPR:$src, GPR:$base,am3offset:$offset),
Evan Cheng44bec522007-05-15 01:29:07 +0000760 "strh", " $src, [$base, $offset]!", "$base = $base_wb",
Evan Chenga8e29892007-01-19 07:51:42 +0000761 [(set GPR:$base_wb,
762 (pre_truncsti16 GPR:$src, GPR:$base,am3offset:$offset))]>;
763
764def STRH_POST: AI3po<(ops GPR:$base_wb, GPR:$src, GPR:$base,am3offset:$offset),
Evan Cheng44bec522007-05-15 01:29:07 +0000765 "strh", " $src, [$base], $offset", "$base = $base_wb",
Evan Chenga8e29892007-01-19 07:51:42 +0000766 [(set GPR:$base_wb, (post_truncsti16 GPR:$src,
767 GPR:$base, am3offset:$offset))]>;
768
769def STRB_PRE : AI2pr<(ops GPR:$base_wb, GPR:$src, GPR:$base,am2offset:$offset),
Evan Cheng44bec522007-05-15 01:29:07 +0000770 "strb", " $src, [$base, $offset]!", "$base = $base_wb",
Evan Chenga8e29892007-01-19 07:51:42 +0000771 [(set GPR:$base_wb, (pre_truncsti8 GPR:$src,
772 GPR:$base, am2offset:$offset))]>;
773
774def STRB_POST: AI2po<(ops GPR:$base_wb, GPR:$src, GPR:$base,am2offset:$offset),
Evan Cheng44bec522007-05-15 01:29:07 +0000775 "strb", " $src, [$base], $offset", "$base = $base_wb",
Evan Chenga8e29892007-01-19 07:51:42 +0000776 [(set GPR:$base_wb, (post_truncsti8 GPR:$src,
777 GPR:$base, am2offset:$offset))]>;
778} // isStore
779
780//===----------------------------------------------------------------------===//
781// Load / store multiple Instructions.
782//
783
784let isLoad = 1 in
Evan Cheng44bec522007-05-15 01:29:07 +0000785def LDM : AXI4<(ops addrmode4:$addr, pred:$p, reglist:$dst1, variable_ops),
786 "ldm${p}${addr:submode} $addr, $dst1",
787 []>;
Evan Chenga8e29892007-01-19 07:51:42 +0000788
789let isStore = 1 in
Evan Cheng44bec522007-05-15 01:29:07 +0000790def STM : AXI4<(ops addrmode4:$addr, pred:$p, reglist:$src1, variable_ops),
791 "stm${p}${addr:submode} $addr, $src1",
792 []>;
Evan Chenga8e29892007-01-19 07:51:42 +0000793
794//===----------------------------------------------------------------------===//
795// Move Instructions.
796//
797
Evan Cheng9f6636f2007-03-19 07:48:02 +0000798def MOVr : AI1<(ops GPR:$dst, GPR:$src),
Evan Cheng44bec522007-05-15 01:29:07 +0000799 "mov", " $dst, $src", []>;
Evan Cheng9f6636f2007-03-19 07:48:02 +0000800def MOVs : AI1<(ops GPR:$dst, so_reg:$src),
Evan Cheng44bec522007-05-15 01:29:07 +0000801 "mov", " $dst, $src", [(set GPR:$dst, so_reg:$src)]>;
Evan Chenga2515702007-03-19 07:09:02 +0000802
803let isReMaterializable = 1 in
Evan Cheng9f6636f2007-03-19 07:48:02 +0000804def MOVi : AI1<(ops GPR:$dst, so_imm:$src),
Evan Cheng44bec522007-05-15 01:29:07 +0000805 "mov", " $dst, $src", [(set GPR:$dst, so_imm:$src)]>;
Evan Chenga8e29892007-01-19 07:51:42 +0000806
807// These aren't really mov instructions, but we have to define them this way
808// due to flag operands.
809
810def MOVsrl_flag : AI1<(ops GPR:$dst, GPR:$src),
Evan Cheng44bec522007-05-15 01:29:07 +0000811 "movs", " $dst, $src, lsr #1",
Evan Chenga8e29892007-01-19 07:51:42 +0000812 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>;
813def MOVsra_flag : AI1<(ops GPR:$dst, GPR:$src),
Evan Cheng44bec522007-05-15 01:29:07 +0000814 "movs", " $dst, $src, asr #1",
Evan Chenga8e29892007-01-19 07:51:42 +0000815 [(set GPR:$dst, (ARMsra_flag GPR:$src))]>;
Evan Cheng9f6636f2007-03-19 07:48:02 +0000816def MOVrx : AI1<(ops GPR:$dst, GPR:$src),
Evan Cheng44bec522007-05-15 01:29:07 +0000817 "mov", " $dst, $src, rrx",
Evan Chenga8e29892007-01-19 07:51:42 +0000818 [(set GPR:$dst, (ARMrrx GPR:$src))]>;
819
Evan Chenga8e29892007-01-19 07:51:42 +0000820//===----------------------------------------------------------------------===//
821// Extend Instructions.
822//
823
824// Sign extenders
825
826defm SXTB : AI_unary_rrot<"sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>;
827defm SXTH : AI_unary_rrot<"sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>;
828
829defm SXTAB : AI_bin_rrot<"sxtab",
830 BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
831defm SXTAH : AI_bin_rrot<"sxtah",
832 BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
833
834// TODO: SXT(A){B|H}16
835
836// Zero extenders
837
838let AddedComplexity = 16 in {
839defm UXTB : AI_unary_rrot<"uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>;
840defm UXTH : AI_unary_rrot<"uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
841defm UXTB16 : AI_unary_rrot<"uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
842
843def : ARMV6Pat<(and (shl GPR:$Src, 8), 0xFF00FF),
844 (UXTB16r_rot GPR:$Src, 24)>;
845def : ARMV6Pat<(and (srl GPR:$Src, 8), 0xFF00FF),
846 (UXTB16r_rot GPR:$Src, 8)>;
847
848defm UXTAB : AI_bin_rrot<"uxtab",
849 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
850defm UXTAH : AI_bin_rrot<"uxtah",
851 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
Rafael Espindola3c000bf2006-08-21 22:00:32 +0000852}
853
Evan Chenga8e29892007-01-19 07:51:42 +0000854// This isn't safe in general, the add is two 16-bit units, not a 32-bit add.
855//defm UXTAB16 : xxx<"uxtab16", 0xff00ff>;
Rafael Espindola817e7fd2006-09-11 19:24:19 +0000856
Evan Chenga8e29892007-01-19 07:51:42 +0000857// TODO: UXT(A){B|H}16
858
859//===----------------------------------------------------------------------===//
860// Arithmetic Instructions.
861//
862
863defm ADD : AI1_bin_irs<"add" , BinOpFrag<(add node:$LHS, node:$RHS)>>;
864defm ADDS : AI1_bin_irs<"adds", BinOpFrag<(addc node:$LHS, node:$RHS)>>;
865defm ADC : AI1_bin_irs<"adc" , BinOpFrag<(adde node:$LHS, node:$RHS)>>;
866defm SUB : AI1_bin_irs<"sub" , BinOpFrag<(sub node:$LHS, node:$RHS)>>;
867defm SUBS : AI1_bin_irs<"subs", BinOpFrag<(subc node:$LHS, node:$RHS)>>;
868defm SBC : AI1_bin_irs<"sbc" , BinOpFrag<(sube node:$LHS, node:$RHS)>>;
869
870// These don't define reg/reg forms, because they are handled above.
871defm RSB : AI1_bin_is <"rsb" , BinOpFrag<(sub node:$RHS, node:$LHS)>>;
872defm RSBS : AI1_bin_is <"rsbs", BinOpFrag<(subc node:$RHS, node:$LHS)>>;
873defm RSC : AI1_bin_is <"rsc" , BinOpFrag<(sube node:$RHS, node:$LHS)>>;
874
875// (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
876def : ARMPat<(add GPR:$src, so_imm_neg:$imm),
877 (SUBri GPR:$src, so_imm_neg:$imm)>;
878
879//def : ARMPat<(addc GPR:$src, so_imm_neg:$imm),
880// (SUBSri GPR:$src, so_imm_neg:$imm)>;
881//def : ARMPat<(adde GPR:$src, so_imm_neg:$imm),
882// (SBCri GPR:$src, so_imm_neg:$imm)>;
883
884// Note: These are implemented in C++ code, because they have to generate
885// ADD/SUBrs instructions, which use a complex pattern that a xform function
886// cannot produce.
887// (mul X, 2^n+1) -> (add (X << n), X)
888// (mul X, 2^n-1) -> (rsb X, (X << n))
889
890
891//===----------------------------------------------------------------------===//
892// Bitwise Instructions.
893//
894
895defm AND : AI1_bin_irs<"and", BinOpFrag<(and node:$LHS, node:$RHS)>>;
896defm ORR : AI1_bin_irs<"orr", BinOpFrag<(or node:$LHS, node:$RHS)>>;
897defm EOR : AI1_bin_irs<"eor", BinOpFrag<(xor node:$LHS, node:$RHS)>>;
898defm BIC : AI1_bin_irs<"bic", BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
899
Evan Chenga2515702007-03-19 07:09:02 +0000900def MVNr : AI<(ops GPR:$dst, GPR:$src),
Evan Cheng44bec522007-05-15 01:29:07 +0000901 "mvn", " $dst, $src", [(set GPR:$dst, (not GPR:$src))]>;
Evan Chenga2515702007-03-19 07:09:02 +0000902def MVNs : AI<(ops GPR:$dst, so_reg:$src),
Evan Cheng44bec522007-05-15 01:29:07 +0000903 "mvn", " $dst, $src", [(set GPR:$dst, (not so_reg:$src))]>;
Evan Chenga2515702007-03-19 07:09:02 +0000904let isReMaterializable = 1 in
905def MVNi : AI<(ops GPR:$dst, so_imm:$imm),
Evan Cheng44bec522007-05-15 01:29:07 +0000906 "mvn", " $dst, $imm", [(set GPR:$dst, so_imm_not:$imm)]>;
Evan Chenga8e29892007-01-19 07:51:42 +0000907
908def : ARMPat<(and GPR:$src, so_imm_not:$imm),
909 (BICri GPR:$src, so_imm_not:$imm)>;
910
911//===----------------------------------------------------------------------===//
912// Multiply Instructions.
913//
914
915// AI_orr - Defines a (op r, r) pattern.
916class AI_orr<string opc, SDNode opnode>
917 : AI<(ops GPR:$dst, GPR:$a, GPR:$b),
Evan Cheng44bec522007-05-15 01:29:07 +0000918 opc, " $dst, $a, $b",
Evan Chenga8e29892007-01-19 07:51:42 +0000919 [(set GPR:$dst, (opnode GPR:$a, GPR:$b))]>;
920
921// AI_oorr - Defines a (op (op r, r), r) pattern.
922class AI_oorr<string opc, SDNode opnode1, SDNode opnode2>
923 : AI<(ops GPR:$dst, GPR:$a, GPR:$b, GPR:$c),
Evan Cheng44bec522007-05-15 01:29:07 +0000924 opc, " $dst, $a, $b, $c",
Evan Chenga8e29892007-01-19 07:51:42 +0000925 [(set GPR:$dst, (opnode1 (opnode2 GPR:$a, GPR:$b), GPR:$c))]>;
926
927def MUL : AI_orr<"mul", mul>;
928def MLA : AI_oorr<"mla", add, mul>;
929
930// Extra precision multiplies with low / high results
931def SMULL : AI<(ops GPR:$ldst, GPR:$hdst, GPR:$a, GPR:$b),
Evan Cheng44bec522007-05-15 01:29:07 +0000932 "smull", " $ldst, $hdst, $a, $b",
Evan Chenga8e29892007-01-19 07:51:42 +0000933 []>;
934
935def UMULL : AI<(ops GPR:$ldst, GPR:$hdst, GPR:$a, GPR:$b),
Evan Cheng44bec522007-05-15 01:29:07 +0000936 "umull", " $ldst, $hdst, $a, $b",
Evan Chenga8e29892007-01-19 07:51:42 +0000937 []>;
938
939// Multiply + accumulate
940def SMLAL : AI<(ops GPR:$ldst, GPR:$hdst, GPR:$a, GPR:$b),
Evan Cheng44bec522007-05-15 01:29:07 +0000941 "smlal", " $ldst, $hdst, $a, $b",
Evan Chenga8e29892007-01-19 07:51:42 +0000942 []>;
943
944def UMLAL : AI<(ops GPR:$ldst, GPR:$hdst, GPR:$a, GPR:$b),
Evan Cheng44bec522007-05-15 01:29:07 +0000945 "umlal", " $ldst, $hdst, $a, $b",
Evan Chenga8e29892007-01-19 07:51:42 +0000946 []>;
947
948def UMAAL : AI<(ops GPR:$ldst, GPR:$hdst, GPR:$a, GPR:$b),
Evan Cheng44bec522007-05-15 01:29:07 +0000949 "umaal", " $ldst, $hdst, $a, $b",
Evan Chenga8e29892007-01-19 07:51:42 +0000950 []>, Requires<[IsARM, HasV6]>;
951
952// Most significant word multiply
953def SMMUL : AI_orr<"smmul", mulhs>, Requires<[IsARM, HasV6]>;
954def SMMLA : AI_oorr<"smmla", add, mulhs>, Requires<[IsARM, HasV6]>;
955
956
957def SMMLS : AI<(ops GPR:$dst, GPR:$a, GPR:$b, GPR:$c),
Evan Cheng44bec522007-05-15 01:29:07 +0000958 "smmls", " $dst, $a, $b, $c",
Evan Chenga8e29892007-01-19 07:51:42 +0000959 [(set GPR:$dst, (sub GPR:$c, (mulhs GPR:$a, GPR:$b)))]>,
960 Requires<[IsARM, HasV6]>;
961
962multiclass AI_smul<string opc, PatFrag opnode> {
Evan Cheng34b12d22007-01-19 20:27:35 +0000963 def BB : AI<(ops GPR:$dst, GPR:$a, GPR:$b),
Evan Cheng44bec522007-05-15 01:29:07 +0000964 !strconcat(opc, "bb"), " $dst, $a, $b",
Evan Cheng34b12d22007-01-19 20:27:35 +0000965 [(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16),
966 (sext_inreg GPR:$b, i16)))]>,
967 Requires<[IsARM, HasV5TE]>;
968 def BT : AI<(ops GPR:$dst, GPR:$a, GPR:$b),
Evan Cheng44bec522007-05-15 01:29:07 +0000969 !strconcat(opc, "bt"), " $dst, $a, $b",
Evan Cheng34b12d22007-01-19 20:27:35 +0000970 [(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16),
971 (sra GPR:$b, 16)))]>,
972 Requires<[IsARM, HasV5TE]>;
973 def TB : AI<(ops GPR:$dst, GPR:$a, GPR:$b),
Evan Cheng44bec522007-05-15 01:29:07 +0000974 !strconcat(opc, "tb"), " $dst, $a, $b",
Evan Cheng34b12d22007-01-19 20:27:35 +0000975 [(set GPR:$dst, (opnode (sra GPR:$a, 16),
976 (sext_inreg GPR:$b, i16)))]>,
977 Requires<[IsARM, HasV5TE]>;
Evan Chenga8e29892007-01-19 07:51:42 +0000978 def TT : AI<(ops GPR:$dst, GPR:$a, GPR:$b),
Evan Cheng44bec522007-05-15 01:29:07 +0000979 !strconcat(opc, "tt"), " $dst, $a, $b",
Evan Chenga8e29892007-01-19 07:51:42 +0000980 [(set GPR:$dst, (opnode (sra GPR:$a, 16),
981 (sra GPR:$b, 16)))]>,
982 Requires<[IsARM, HasV5TE]>;
Evan Cheng34b12d22007-01-19 20:27:35 +0000983 def WB : AI<(ops GPR:$dst, GPR:$a, GPR:$b),
Evan Cheng44bec522007-05-15 01:29:07 +0000984 !strconcat(opc, "wb"), " $dst, $a, $b",
Evan Cheng34b12d22007-01-19 20:27:35 +0000985 [(set GPR:$dst, (sra (opnode GPR:$a,
986 (sext_inreg GPR:$b, i16)), 16))]>,
987 Requires<[IsARM, HasV5TE]>;
Evan Chenga8e29892007-01-19 07:51:42 +0000988 def WT : AI<(ops GPR:$dst, GPR:$a, GPR:$b),
Evan Cheng44bec522007-05-15 01:29:07 +0000989 !strconcat(opc, "wt"), " $dst, $a, $b",
Evan Chenga8e29892007-01-19 07:51:42 +0000990 [(set GPR:$dst, (sra (opnode GPR:$a,
991 (sra GPR:$b, 16)), 16))]>,
992 Requires<[IsARM, HasV5TE]>;
Rafael Espindolabec2e382006-10-16 16:33:29 +0000993}
994
Evan Chenga8e29892007-01-19 07:51:42 +0000995multiclass AI_smla<string opc, PatFrag opnode> {
Evan Cheng34b12d22007-01-19 20:27:35 +0000996 def BB : AI<(ops GPR:$dst, GPR:$a, GPR:$b, GPR:$acc),
Evan Cheng44bec522007-05-15 01:29:07 +0000997 !strconcat(opc, "bb"), " $dst, $a, $b, $acc",
Evan Cheng34b12d22007-01-19 20:27:35 +0000998 [(set GPR:$dst, (add GPR:$acc,
999 (opnode (sext_inreg GPR:$a, i16),
1000 (sext_inreg GPR:$b, i16))))]>,
1001 Requires<[IsARM, HasV5TE]>;
1002 def BT : AI<(ops GPR:$dst, GPR:$a, GPR:$b, GPR:$acc),
Evan Cheng44bec522007-05-15 01:29:07 +00001003 !strconcat(opc, "bt"), " $dst, $a, $b, $acc",
Evan Cheng34b12d22007-01-19 20:27:35 +00001004 [(set GPR:$dst, (add GPR:$acc, (opnode (sext_inreg GPR:$a, i16),
Evan Chenga8e29892007-01-19 07:51:42 +00001005 (sra GPR:$b, 16))))]>,
Evan Cheng34b12d22007-01-19 20:27:35 +00001006 Requires<[IsARM, HasV5TE]>;
1007 def TB : AI<(ops GPR:$dst, GPR:$a, GPR:$b, GPR:$acc),
Evan Cheng44bec522007-05-15 01:29:07 +00001008 !strconcat(opc, "tb"), " $dst, $a, $b, $acc",
Evan Cheng34b12d22007-01-19 20:27:35 +00001009 [(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, 16),
1010 (sext_inreg GPR:$b, i16))))]>,
1011 Requires<[IsARM, HasV5TE]>;
Evan Chenga8e29892007-01-19 07:51:42 +00001012 def TT : AI<(ops GPR:$dst, GPR:$a, GPR:$b, GPR:$acc),
Evan Cheng44bec522007-05-15 01:29:07 +00001013 !strconcat(opc, "tt"), " $dst, $a, $b, $acc",
Evan Chenga8e29892007-01-19 07:51:42 +00001014 [(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, 16),
1015 (sra GPR:$b, 16))))]>,
1016 Requires<[IsARM, HasV5TE]>;
1017
Evan Cheng34b12d22007-01-19 20:27:35 +00001018 def WB : AI<(ops GPR:$dst, GPR:$a, GPR:$b, GPR:$acc),
Evan Cheng44bec522007-05-15 01:29:07 +00001019 !strconcat(opc, "wb"), " $dst, $a, $b, $acc",
Evan Cheng34b12d22007-01-19 20:27:35 +00001020 [(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a,
1021 (sext_inreg GPR:$b, i16)), 16)))]>,
1022 Requires<[IsARM, HasV5TE]>;
Evan Chenga8e29892007-01-19 07:51:42 +00001023 def WT : AI<(ops GPR:$dst, GPR:$a, GPR:$b, GPR:$acc),
Evan Cheng44bec522007-05-15 01:29:07 +00001024 !strconcat(opc, "wt"), " $dst, $a, $b, $acc",
Evan Chenga8e29892007-01-19 07:51:42 +00001025 [(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a,
1026 (sra GPR:$b, 16)), 16)))]>,
1027 Requires<[IsARM, HasV5TE]>;
Rafael Espindola70673a12006-10-18 16:20:57 +00001028}
Rafael Espindola5c2aa0a2006-09-08 12:47:03 +00001029
Evan Chenga8e29892007-01-19 07:51:42 +00001030defm SMUL : AI_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
1031defm SMLA : AI_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
Rafael Espindola27185192006-09-29 21:20:16 +00001032
Evan Chenga8e29892007-01-19 07:51:42 +00001033// TODO: Halfword multiple accumulate long: SMLAL<x><y>
1034// TODO: Dual halfword multiple: SMUAD, SMUSD, SMLAD, SMLSD, SMLALD, SMLSLD
Rafael Espindola42b62f32006-10-13 13:14:59 +00001035
Evan Chenga8e29892007-01-19 07:51:42 +00001036//===----------------------------------------------------------------------===//
1037// Misc. Arithmetic Instructions.
1038//
Rafael Espindola0d9fe762006-10-10 16:33:47 +00001039
Evan Chenga8e29892007-01-19 07:51:42 +00001040def CLZ : AI<(ops GPR:$dst, GPR:$src),
Evan Cheng44bec522007-05-15 01:29:07 +00001041 "clz", " $dst, $src",
Evan Chenga8e29892007-01-19 07:51:42 +00001042 [(set GPR:$dst, (ctlz GPR:$src))]>, Requires<[IsARM, HasV5T]>;
Rafael Espindola199dd672006-10-17 13:13:23 +00001043
Evan Chenga8e29892007-01-19 07:51:42 +00001044def REV : AI<(ops GPR:$dst, GPR:$src),
Evan Cheng44bec522007-05-15 01:29:07 +00001045 "rev", " $dst, $src",
Evan Chenga8e29892007-01-19 07:51:42 +00001046 [(set GPR:$dst, (bswap GPR:$src))]>, Requires<[IsARM, HasV6]>;
Rafael Espindola199dd672006-10-17 13:13:23 +00001047
Evan Chenga8e29892007-01-19 07:51:42 +00001048def REV16 : AI<(ops GPR:$dst, GPR:$src),
Evan Cheng44bec522007-05-15 01:29:07 +00001049 "rev16", " $dst, $src",
Evan Chenga8e29892007-01-19 07:51:42 +00001050 [(set GPR:$dst,
1051 (or (and (srl GPR:$src, 8), 0xFF),
1052 (or (and (shl GPR:$src, 8), 0xFF00),
1053 (or (and (srl GPR:$src, 8), 0xFF0000),
1054 (and (shl GPR:$src, 8), 0xFF000000)))))]>,
1055 Requires<[IsARM, HasV6]>;
Rafael Espindola27185192006-09-29 21:20:16 +00001056
Evan Chenga8e29892007-01-19 07:51:42 +00001057def REVSH : AI<(ops GPR:$dst, GPR:$src),
Evan Cheng44bec522007-05-15 01:29:07 +00001058 "revsh", " $dst, $src",
Evan Chenga8e29892007-01-19 07:51:42 +00001059 [(set GPR:$dst,
1060 (sext_inreg
Chris Lattner120fba92007-04-17 22:39:58 +00001061 (or (srl (and GPR:$src, 0xFF00), 8),
Evan Chenga8e29892007-01-19 07:51:42 +00001062 (shl GPR:$src, 8)), i16))]>,
1063 Requires<[IsARM, HasV6]>;
Rafael Espindola27185192006-09-29 21:20:16 +00001064
Evan Chenga8e29892007-01-19 07:51:42 +00001065def PKHBT : AI<(ops GPR:$dst, GPR:$src1, GPR:$src2, i32imm:$shamt),
Evan Cheng44bec522007-05-15 01:29:07 +00001066 "pkhbt", " $dst, $src1, $src2, LSL $shamt",
Evan Chenga8e29892007-01-19 07:51:42 +00001067 [(set GPR:$dst, (or (and GPR:$src1, 0xFFFF),
1068 (and (shl GPR:$src2, (i32 imm:$shamt)),
1069 0xFFFF0000)))]>,
1070 Requires<[IsARM, HasV6]>;
Rafael Espindola27185192006-09-29 21:20:16 +00001071
Evan Chenga8e29892007-01-19 07:51:42 +00001072// Alternate cases for PKHBT where identities eliminate some nodes.
1073def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF), (and GPR:$src2, 0xFFFF0000)),
1074 (PKHBT GPR:$src1, GPR:$src2, 0)>;
1075def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF), (shl GPR:$src2, imm16_31:$shamt)),
1076 (PKHBT GPR:$src1, GPR:$src2, imm16_31:$shamt)>;
Rafael Espindola9e071f02006-10-02 19:30:56 +00001077
Rafael Espindolaa2845842006-10-05 16:48:49 +00001078
Evan Chenga8e29892007-01-19 07:51:42 +00001079def PKHTB : AI<(ops GPR:$dst, GPR:$src1, GPR:$src2, i32imm:$shamt),
Evan Cheng44bec522007-05-15 01:29:07 +00001080 "pkhtb", " $dst, $src1, $src2, ASR $shamt",
Evan Chenga8e29892007-01-19 07:51:42 +00001081 [(set GPR:$dst, (or (and GPR:$src1, 0xFFFF0000),
1082 (and (sra GPR:$src2, imm16_31:$shamt),
1083 0xFFFF)))]>, Requires<[IsARM, HasV6]>;
Rafael Espindola9e071f02006-10-02 19:30:56 +00001084
Evan Chenga8e29892007-01-19 07:51:42 +00001085// Alternate cases for PKHTB where identities eliminate some nodes. Note that
1086// a shift amount of 0 is *not legal* here, it is PKHBT instead.
1087def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000), (srl GPR:$src2, 16)),
1088 (PKHTB GPR:$src1, GPR:$src2, 16)>;
1089def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000),
1090 (and (srl GPR:$src2, imm1_15:$shamt), 0xFFFF)),
1091 (PKHTB GPR:$src1, GPR:$src2, imm1_15:$shamt)>;
Rafael Espindolab47e1d02006-10-10 18:55:14 +00001092
Rafael Espindolad9ae7782006-10-07 13:46:42 +00001093
Evan Chenga8e29892007-01-19 07:51:42 +00001094//===----------------------------------------------------------------------===//
1095// Comparison Instructions...
1096//
Rafael Espindolab47e1d02006-10-10 18:55:14 +00001097
Evan Chenga8e29892007-01-19 07:51:42 +00001098defm CMP : AI1_bin0_irs<"cmp", BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
1099defm CMN : AI1_bin0_irs<"cmn", BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>;
Rafael Espindolae5bbd6d2006-10-07 14:24:52 +00001100
Evan Chenga8e29892007-01-19 07:51:42 +00001101def : ARMPat<(ARMcmp GPR:$src, so_imm_neg:$imm),
1102 (CMNri GPR:$src, so_imm_neg:$imm)>;
Rafael Espindola493a7fc2006-10-10 20:38:57 +00001103
Evan Chenga8e29892007-01-19 07:51:42 +00001104// Note that TST/TEQ don't set all the same flags that CMP does!
Lauro Ramos Venancio99966632007-04-02 01:30:03 +00001105defm TST : AI1_bin0_irs<"tst", BinOpFrag<(ARMcmpNZ (and node:$LHS, node:$RHS), 0)>>;
1106defm TEQ : AI1_bin0_irs<"teq", BinOpFrag<(ARMcmpNZ (xor node:$LHS, node:$RHS), 0)>>;
1107
1108defm CMPnz : AI1_bin0_irs<"cmp", BinOpFrag<(ARMcmpNZ node:$LHS, node:$RHS)>>;
1109defm CMNnz : AI1_bin0_irs<"cmn", BinOpFrag<(ARMcmpNZ node:$LHS,(ineg node:$RHS))>>;
1110
1111def : ARMPat<(ARMcmpNZ GPR:$src, so_imm_neg:$imm),
1112 (CMNri GPR:$src, so_imm_neg:$imm)>;
1113
Rafael Espindolae5bbd6d2006-10-07 14:24:52 +00001114
Evan Chenga8e29892007-01-19 07:51:42 +00001115// Conditional moves
Evan Cheng44bec522007-05-15 01:29:07 +00001116def MOVCCr : AXI<(ops GPR:$dst, GPR:$false, GPR:$true, ccop:$cc),
1117 "mov$cc $dst, $true",
1118 [(set GPR:$dst, (ARMcmov GPR:$false, GPR:$true, imm:$cc))]>,
1119 RegConstraint<"$false = $dst">;
Rafael Espindola493a7fc2006-10-10 20:38:57 +00001120
Evan Cheng44bec522007-05-15 01:29:07 +00001121def MOVCCs : AXI<(ops GPR:$dst, GPR:$false, so_reg:$true, ccop:$cc),
1122 "mov$cc $dst, $true",
1123 [(set GPR:$dst, (ARMcmov GPR:$false, so_reg:$true,imm:$cc))]>,
1124 RegConstraint<"$false = $dst">;
Rafael Espindola2dc0f2b2006-10-09 17:50:29 +00001125
Evan Cheng44bec522007-05-15 01:29:07 +00001126def MOVCCi : AXI<(ops GPR:$dst, GPR:$false, so_imm:$true, ccop:$cc),
1127 "mov$cc $dst, $true",
1128 [(set GPR:$dst, (ARMcmov GPR:$false, so_imm:$true,imm:$cc))]>,
1129 RegConstraint<"$false = $dst">;
Rafael Espindolad9ae7782006-10-07 13:46:42 +00001130
Rafael Espindola4b20fbc2006-10-10 12:56:00 +00001131
Evan Chenga8e29892007-01-19 07:51:42 +00001132// LEApcrel - Load a pc-relative address into a register without offending the
1133// assembler.
Evan Cheng44bec522007-05-15 01:29:07 +00001134def LEApcrel : AXI1<(ops GPR:$dst, i32imm:$label, pred:$p),
Evan Chenga8e29892007-01-19 07:51:42 +00001135 !strconcat(!strconcat(".set PCRELV${:uid}, ($label-(",
1136 "${:private}PCRELL${:uid}+8))\n"),
1137 !strconcat("${:private}PCRELL${:uid}:\n\t",
Evan Cheng44bec522007-05-15 01:29:07 +00001138 "add$p $dst, pc, #PCRELV${:uid}")),
Evan Chenga8e29892007-01-19 07:51:42 +00001139 []>;
Rafael Espindola667c3492006-10-10 19:35:01 +00001140
Evan Cheng44bec522007-05-15 01:29:07 +00001141def LEApcrelJT : AXI1<(ops GPR:$dst, i32imm:$label, i32imm:$id, pred:$p),
Evan Chenga8e29892007-01-19 07:51:42 +00001142 !strconcat(!strconcat(".set PCRELV${:uid}, (${label}_${id:no_hash}-(",
1143 "${:private}PCRELL${:uid}+8))\n"),
1144 !strconcat("${:private}PCRELL${:uid}:\n\t",
Evan Cheng44bec522007-05-15 01:29:07 +00001145 "add$p $dst, pc, #PCRELV${:uid}")),
Evan Chenga8e29892007-01-19 07:51:42 +00001146 []>;
Lauro Ramos Venancio64f4fa52007-04-27 13:54:47 +00001147//===----------------------------------------------------------------------===//
1148// TLS Instructions
1149//
1150
1151// __aeabi_read_tp preserves the registers r1-r3.
1152let isCall = 1,
1153 Defs = [R0, R12, LR] in {
Evan Chengdcc50a42007-05-18 01:53:54 +00001154 def TPsoft : AXI<(ops),
1155 "bl __aeabi_read_tp",
Lauro Ramos Venancio64f4fa52007-04-27 13:54:47 +00001156 [(set R0, ARMthread_pointer)]>;
1157}
Rafael Espindolac01c87c2006-10-17 20:33:13 +00001158
Evan Chenga8e29892007-01-19 07:51:42 +00001159//===----------------------------------------------------------------------===//
1160// Non-Instruction Patterns
1161//
Rafael Espindola5aca9272006-10-07 14:03:39 +00001162
Evan Chenga8e29892007-01-19 07:51:42 +00001163// ConstantPool, GlobalAddress, and JumpTable
1164def : ARMPat<(ARMWrapper tglobaladdr :$dst), (LEApcrel tglobaladdr :$dst)>;
1165def : ARMPat<(ARMWrapper tconstpool :$dst), (LEApcrel tconstpool :$dst)>;
1166def : ARMPat<(ARMWrapperJT tjumptable:$dst, imm:$id),
Evan Chengc70d1842007-03-20 08:11:30 +00001167 (LEApcrelJT tjumptable:$dst, imm:$id)>;
Rafael Espindola5aca9272006-10-07 14:03:39 +00001168
Evan Chenga8e29892007-01-19 07:51:42 +00001169// Large immediate handling.
Rafael Espindola0505be02006-10-16 21:10:32 +00001170
Evan Chenga8e29892007-01-19 07:51:42 +00001171// Two piece so_imms.
Evan Chengc70d1842007-03-20 08:11:30 +00001172let isReMaterializable = 1 in
1173def MOVi2pieces : AI1x2<(ops GPR:$dst, so_imm2part:$src),
Evan Cheng44bec522007-05-15 01:29:07 +00001174 "mov", " $dst, $src",
Evan Chengc70d1842007-03-20 08:11:30 +00001175 [(set GPR:$dst, so_imm2part:$src)]>;
Rafael Espindolaf621abc2006-10-17 13:36:07 +00001176
Evan Chenga8e29892007-01-19 07:51:42 +00001177def : ARMPat<(or GPR:$LHS, so_imm2part:$RHS),
1178 (ORRri (ORRri GPR:$LHS, (so_imm2part_1 imm:$RHS)),
1179 (so_imm2part_2 imm:$RHS))>;
1180def : ARMPat<(xor GPR:$LHS, so_imm2part:$RHS),
1181 (EORri (EORri GPR:$LHS, (so_imm2part_1 imm:$RHS)),
1182 (so_imm2part_2 imm:$RHS))>;
Rafael Espindolaf621abc2006-10-17 13:36:07 +00001183
Evan Chenga8e29892007-01-19 07:51:42 +00001184// TODO: add,sub,and, 3-instr forms?
Rafael Espindola0505be02006-10-16 21:10:32 +00001185
Rafael Espindola24357862006-10-19 17:05:03 +00001186
Evan Chenga8e29892007-01-19 07:51:42 +00001187// Direct calls
1188def : ARMPat<(ARMcall texternalsym:$func), (BL texternalsym:$func)>;
Rafael Espindola9dca7ad2006-11-01 14:13:27 +00001189
Evan Chenga8e29892007-01-19 07:51:42 +00001190// zextload i1 -> zextload i8
1191def : ARMPat<(zextloadi1 addrmode2:$addr), (LDRB addrmode2:$addr)>;
Lauro Ramos Venancioa8f9f4a2006-12-26 19:30:42 +00001192
Evan Chenga8e29892007-01-19 07:51:42 +00001193// extload -> zextload
1194def : ARMPat<(extloadi1 addrmode2:$addr), (LDRB addrmode2:$addr)>;
1195def : ARMPat<(extloadi8 addrmode2:$addr), (LDRB addrmode2:$addr)>;
1196def : ARMPat<(extloadi16 addrmode3:$addr), (LDRH addrmode3:$addr)>;
Rafael Espindola9dca7ad2006-11-01 14:13:27 +00001197
Evan Chenga8e29892007-01-19 07:51:42 +00001198// truncstore i1 -> truncstore i8
Dale Johannesen25c1f9e2007-04-27 22:17:18 +00001199def : ARMPat<(truncstorei1 GPR:$src, addrmode2:$dst),
Dale Johannesencaa80552007-04-28 00:36:37 +00001200 (STRB GPR:$src, addrmode2:$dst)>;
Dale Johannesen25c1f9e2007-04-27 22:17:18 +00001201def : ARMPat<(pre_truncsti1 GPR:$src, GPR:$base, am2offset:$offset),
Dale Johannesencaa80552007-04-28 00:36:37 +00001202 (STRB_PRE GPR:$src, GPR:$base, am2offset:$offset)>;
Dale Johannesen25c1f9e2007-04-27 22:17:18 +00001203def : ARMPat<(post_truncsti1 GPR:$src, GPR:$base, am2offset:$offset),
Dale Johannesencaa80552007-04-28 00:36:37 +00001204 (STRB_POST GPR:$src, GPR:$base, am2offset:$offset)>;
Evan Chenga8e29892007-01-19 07:51:42 +00001205
Evan Cheng34b12d22007-01-19 20:27:35 +00001206// smul* and smla*
1207def : ARMV5TEPat<(mul (sra (shl GPR:$a, 16), 16), (sra (shl GPR:$b, 16), 16)),
1208 (SMULBB GPR:$a, GPR:$b)>;
1209def : ARMV5TEPat<(mul sext_16_node:$a, sext_16_node:$b),
1210 (SMULBB GPR:$a, GPR:$b)>;
1211def : ARMV5TEPat<(mul (sra (shl GPR:$a, 16), 16), (sra GPR:$b, 16)),
1212 (SMULBT GPR:$a, GPR:$b)>;
1213def : ARMV5TEPat<(mul sext_16_node:$a, (sra GPR:$b, 16)),
1214 (SMULBT GPR:$a, GPR:$b)>;
1215def : ARMV5TEPat<(mul (sra GPR:$a, 16), (sra (shl GPR:$b, 16), 16)),
1216 (SMULTB GPR:$a, GPR:$b)>;
1217def : ARMV5TEPat<(mul (sra GPR:$a, 16), sext_16_node:$b),
1218 (SMULTB GPR:$a, GPR:$b)>;
1219def : ARMV5TEPat<(sra (mul GPR:$a, (sra (shl GPR:$b, 16), 16)), 16),
1220 (SMULWB GPR:$a, GPR:$b)>;
1221def : ARMV5TEPat<(sra (mul GPR:$a, sext_16_node:$b), 16),
1222 (SMULWB GPR:$a, GPR:$b)>;
1223
1224def : ARMV5TEPat<(add GPR:$acc,
1225 (mul (sra (shl GPR:$a, 16), 16),
1226 (sra (shl GPR:$b, 16), 16))),
1227 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
1228def : ARMV5TEPat<(add GPR:$acc,
1229 (mul sext_16_node:$a, sext_16_node:$b)),
1230 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
1231def : ARMV5TEPat<(add GPR:$acc,
1232 (mul (sra (shl GPR:$a, 16), 16), (sra GPR:$b, 16))),
1233 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
1234def : ARMV5TEPat<(add GPR:$acc,
1235 (mul sext_16_node:$a, (sra GPR:$b, 16))),
1236 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
1237def : ARMV5TEPat<(add GPR:$acc,
1238 (mul (sra GPR:$a, 16), (sra (shl GPR:$b, 16), 16))),
1239 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
1240def : ARMV5TEPat<(add GPR:$acc,
1241 (mul (sra GPR:$a, 16), sext_16_node:$b)),
1242 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
1243def : ARMV5TEPat<(add GPR:$acc,
1244 (sra (mul GPR:$a, (sra (shl GPR:$b, 16), 16)), 16)),
1245 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
1246def : ARMV5TEPat<(add GPR:$acc,
1247 (sra (mul GPR:$a, sext_16_node:$b), 16)),
1248 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
1249
Evan Chenga8e29892007-01-19 07:51:42 +00001250//===----------------------------------------------------------------------===//
1251// Thumb Support
1252//
1253
1254include "ARMInstrThumb.td"
1255
1256//===----------------------------------------------------------------------===//
1257// Floating Point Support
1258//
1259
1260include "ARMInstrVFP.td"