Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 1 | //===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===// |
Rafael Espindola | 7bc59bc | 2006-05-14 22:18:28 +0000 | [diff] [blame] | 2 | // |
| 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
| 5 | // This file was developed by the "Instituto Nokia de Tecnologia" and |
| 6 | // is distributed under the University of Illinois Open Source |
| 7 | // License. See LICENSE.TXT for details. |
| 8 | // |
| 9 | //===----------------------------------------------------------------------===// |
| 10 | // |
| 11 | // This file describes the ARM instructions in TableGen format. |
| 12 | // |
| 13 | //===----------------------------------------------------------------------===// |
| 14 | |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 15 | //===----------------------------------------------------------------------===// |
| 16 | // ARM specific DAG Nodes. |
| 17 | // |
Rafael Espindola | 7cca7c5 | 2006-09-11 17:25:40 +0000 | [diff] [blame] | 18 | |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 19 | // Type profiles. |
| 20 | def SDT_ARMCallSeq : SDTypeProfile<0, 1, [ SDTCisVT<0, i32> ]>; |
Rafael Espindola | 6e8c649 | 2006-11-08 17:07:32 +0000 | [diff] [blame] | 21 | |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 22 | def SDT_ARMSaveCallPC : SDTypeProfile<0, 1, []>; |
Rafael Espindola | 32bd5f4 | 2006-10-17 18:04:53 +0000 | [diff] [blame] | 23 | |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 24 | def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisInt<0>]>; |
Rafael Espindola | 7cca7c5 | 2006-09-11 17:25:40 +0000 | [diff] [blame] | 25 | |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 26 | def SDT_ARMCMov : SDTypeProfile<1, 3, |
| 27 | [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, |
| 28 | SDTCisVT<3, i32>]>; |
Rafael Espindola | 6e8c649 | 2006-11-08 17:07:32 +0000 | [diff] [blame] | 29 | |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 30 | def SDT_ARMBrcond : SDTypeProfile<0, 2, |
| 31 | [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>; |
| 32 | |
| 33 | def SDT_ARMBrJT : SDTypeProfile<0, 3, |
| 34 | [SDTCisPtrTy<0>, SDTCisVT<1, i32>, |
| 35 | SDTCisVT<2, i32>]>; |
| 36 | |
| 37 | def SDT_ARMCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>; |
| 38 | |
| 39 | def SDT_ARMPICAdd : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>, |
| 40 | SDTCisPtrTy<1>, SDTCisVT<2, i32>]>; |
| 41 | |
Lauro Ramos Venancio | 64f4fa5 | 2007-04-27 13:54:47 +0000 | [diff] [blame] | 42 | def SDT_ARMThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>; |
| 43 | |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 44 | // Node definitions. |
| 45 | def ARMWrapper : SDNode<"ARMISD::Wrapper", SDTIntUnaryOp>; |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 46 | def ARMWrapperJT : SDNode<"ARMISD::WrapperJT", SDTIntBinOp>; |
| 47 | |
| 48 | def ARMcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeq, |
| 49 | [SDNPHasChain, SDNPOutFlag]>; |
| 50 | def ARMcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeq, |
Evan Cheng | b38cba9 | 2007-02-03 09:11:58 +0000 | [diff] [blame] | 51 | [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>; |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 52 | |
| 53 | def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall, |
| 54 | [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>; |
| 55 | def ARMcall_nolink : SDNode<"ARMISD::CALL_NOLINK", SDT_ARMcall, |
| 56 | [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>; |
| 57 | |
| 58 | def ARMretflag : SDNode<"ARMISD::RET_FLAG", SDTRet, |
| 59 | [SDNPHasChain, SDNPOptInFlag]>; |
| 60 | |
| 61 | def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov, |
| 62 | [SDNPInFlag]>; |
| 63 | def ARMcneg : SDNode<"ARMISD::CNEG", SDT_ARMCMov, |
| 64 | [SDNPInFlag]>; |
| 65 | |
| 66 | def ARMbrcond : SDNode<"ARMISD::BRCOND", SDT_ARMBrcond, |
| 67 | [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>; |
| 68 | |
| 69 | def ARMbrjt : SDNode<"ARMISD::BR_JT", SDT_ARMBrJT, |
| 70 | [SDNPHasChain]>; |
| 71 | |
| 72 | def ARMcmp : SDNode<"ARMISD::CMP", SDT_ARMCmp, |
| 73 | [SDNPOutFlag]>; |
| 74 | |
Lauro Ramos Venancio | 9996663 | 2007-04-02 01:30:03 +0000 | [diff] [blame] | 75 | def ARMcmpNZ : SDNode<"ARMISD::CMPNZ", SDT_ARMCmp, |
| 76 | [SDNPOutFlag]>; |
| 77 | |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 78 | def ARMpic_add : SDNode<"ARMISD::PIC_ADD", SDT_ARMPICAdd>; |
| 79 | |
| 80 | def ARMsrl_flag : SDNode<"ARMISD::SRL_FLAG", SDTIntUnaryOp, [SDNPOutFlag]>; |
| 81 | def ARMsra_flag : SDNode<"ARMISD::SRA_FLAG", SDTIntUnaryOp, [SDNPOutFlag]>; |
| 82 | def ARMrrx : SDNode<"ARMISD::RRX" , SDTIntUnaryOp, [SDNPInFlag ]>; |
Rafael Espindola | 32bd5f4 | 2006-10-17 18:04:53 +0000 | [diff] [blame] | 83 | |
Lauro Ramos Venancio | 64f4fa5 | 2007-04-27 13:54:47 +0000 | [diff] [blame] | 84 | def ARMthread_pointer: SDNode<"ARMISD::THREAD_POINTER", SDT_ARMThreadPointer>; |
| 85 | |
Rafael Espindola | 7bc59bc | 2006-05-14 22:18:28 +0000 | [diff] [blame] | 86 | //===----------------------------------------------------------------------===// |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 87 | // ARM Instruction Predicate Definitions. |
| 88 | // |
| 89 | def HasV5T : Predicate<"Subtarget->hasV5TOps()">; |
| 90 | def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">; |
| 91 | def HasV6 : Predicate<"Subtarget->hasV6Ops()">; |
| 92 | def IsThumb : Predicate<"Subtarget->isThumb()">; |
| 93 | def IsARM : Predicate<"!Subtarget->isThumb()">; |
| 94 | |
Rafael Espindola | 7bc59bc | 2006-05-14 22:18:28 +0000 | [diff] [blame] | 95 | //===----------------------------------------------------------------------===// |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 96 | // ARM Flag Definitions. |
| 97 | |
| 98 | class RegConstraint<string C> { |
| 99 | string Constraints = C; |
| 100 | } |
| 101 | |
| 102 | //===----------------------------------------------------------------------===// |
| 103 | // ARM specific transformation functions and pattern fragments. |
| 104 | // |
| 105 | |
| 106 | // so_imm_XFORM - Return a so_imm value packed into the format described for |
| 107 | // so_imm def below. |
| 108 | def so_imm_XFORM : SDNodeXForm<imm, [{ |
| 109 | return CurDAG->getTargetConstant(ARM_AM::getSOImmVal(N->getValue()), |
| 110 | MVT::i32); |
| 111 | }]>; |
| 112 | |
| 113 | // so_imm_neg_XFORM - Return a so_imm value packed into the format described for |
| 114 | // so_imm_neg def below. |
| 115 | def so_imm_neg_XFORM : SDNodeXForm<imm, [{ |
| 116 | return CurDAG->getTargetConstant(ARM_AM::getSOImmVal(-(int)N->getValue()), |
| 117 | MVT::i32); |
| 118 | }]>; |
| 119 | |
| 120 | // so_imm_not_XFORM - Return a so_imm value packed into the format described for |
| 121 | // so_imm_not def below. |
| 122 | def so_imm_not_XFORM : SDNodeXForm<imm, [{ |
| 123 | return CurDAG->getTargetConstant(ARM_AM::getSOImmVal(~(int)N->getValue()), |
| 124 | MVT::i32); |
| 125 | }]>; |
| 126 | |
| 127 | // rot_imm predicate - True if the 32-bit immediate is equal to 8, 16, or 24. |
| 128 | def rot_imm : PatLeaf<(i32 imm), [{ |
| 129 | int32_t v = (int32_t)N->getValue(); |
| 130 | return v == 8 || v == 16 || v == 24; |
| 131 | }]>; |
| 132 | |
| 133 | /// imm1_15 predicate - True if the 32-bit immediate is in the range [1,15]. |
| 134 | def imm1_15 : PatLeaf<(i32 imm), [{ |
| 135 | return (int32_t)N->getValue() >= 1 && (int32_t)N->getValue() < 16; |
| 136 | }]>; |
| 137 | |
| 138 | /// imm16_31 predicate - True if the 32-bit immediate is in the range [16,31]. |
| 139 | def imm16_31 : PatLeaf<(i32 imm), [{ |
| 140 | return (int32_t)N->getValue() >= 16 && (int32_t)N->getValue() < 32; |
| 141 | }]>; |
| 142 | |
| 143 | def so_imm_neg : |
| 144 | PatLeaf<(imm), [{ return ARM_AM::getSOImmVal(-(int)N->getValue()) != -1; }], |
| 145 | so_imm_neg_XFORM>; |
| 146 | |
Evan Cheng | a251570 | 2007-03-19 07:09:02 +0000 | [diff] [blame] | 147 | def so_imm_not : |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 148 | PatLeaf<(imm), [{ return ARM_AM::getSOImmVal(~(int)N->getValue()) != -1; }], |
| 149 | so_imm_not_XFORM>; |
| 150 | |
| 151 | // sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits. |
| 152 | def sext_16_node : PatLeaf<(i32 GPR:$a), [{ |
| 153 | return TLI.ComputeNumSignBits(SDOperand(N,0)) >= 17; |
| 154 | }]>; |
| 155 | |
| 156 | |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 157 | |
| 158 | //===----------------------------------------------------------------------===// |
| 159 | // Operand Definitions. |
| 160 | // |
| 161 | |
| 162 | // Branch target. |
| 163 | def brtarget : Operand<OtherVT>; |
| 164 | |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 165 | // A list of registers separated by comma. Used by load/store multiple. |
| 166 | def reglist : Operand<i32> { |
| 167 | let PrintMethod = "printRegisterList"; |
| 168 | } |
| 169 | |
| 170 | // An operand for the CONSTPOOL_ENTRY pseudo-instruction. |
| 171 | def cpinst_operand : Operand<i32> { |
| 172 | let PrintMethod = "printCPInstOperand"; |
| 173 | } |
| 174 | |
| 175 | def jtblock_operand : Operand<i32> { |
| 176 | let PrintMethod = "printJTBlockOperand"; |
| 177 | } |
| 178 | |
| 179 | // Local PC labels. |
| 180 | def pclabel : Operand<i32> { |
| 181 | let PrintMethod = "printPCLabel"; |
| 182 | } |
| 183 | |
| 184 | // shifter_operand operands: so_reg and so_imm. |
| 185 | def so_reg : Operand<i32>, // reg reg imm |
| 186 | ComplexPattern<i32, 3, "SelectShifterOperandReg", |
| 187 | [shl,srl,sra,rotr]> { |
| 188 | let PrintMethod = "printSORegOperand"; |
| 189 | let MIOperandInfo = (ops GPR, GPR, i32imm); |
| 190 | } |
| 191 | |
| 192 | // so_imm - Match a 32-bit shifter_operand immediate operand, which is an |
| 193 | // 8-bit immediate rotated by an arbitrary number of bits. so_imm values are |
| 194 | // represented in the imm field in the same 12-bit form that they are encoded |
| 195 | // into so_imm instructions: the 8-bit immediate is the least significant bits |
| 196 | // [bits 0-7], the 4-bit shift amount is the next 4 bits [bits 8-11]. |
| 197 | def so_imm : Operand<i32>, |
| 198 | PatLeaf<(imm), |
| 199 | [{ return ARM_AM::getSOImmVal(N->getValue()) != -1; }], |
| 200 | so_imm_XFORM> { |
| 201 | let PrintMethod = "printSOImmOperand"; |
| 202 | } |
| 203 | |
Evan Cheng | c70d184 | 2007-03-20 08:11:30 +0000 | [diff] [blame] | 204 | // Break so_imm's up into two pieces. This handles immediates with up to 16 |
| 205 | // bits set in them. This uses so_imm2part to match and so_imm2part_[12] to |
| 206 | // get the first/second pieces. |
| 207 | def so_imm2part : Operand<i32>, |
| 208 | PatLeaf<(imm), |
| 209 | [{ return ARM_AM::isSOImmTwoPartVal((unsigned)N->getValue()); }]> { |
| 210 | let PrintMethod = "printSOImm2PartOperand"; |
| 211 | } |
| 212 | |
| 213 | def so_imm2part_1 : SDNodeXForm<imm, [{ |
| 214 | unsigned V = ARM_AM::getSOImmTwoPartFirst((unsigned)N->getValue()); |
| 215 | return CurDAG->getTargetConstant(ARM_AM::getSOImmVal(V), MVT::i32); |
| 216 | }]>; |
| 217 | |
| 218 | def so_imm2part_2 : SDNodeXForm<imm, [{ |
| 219 | unsigned V = ARM_AM::getSOImmTwoPartSecond((unsigned)N->getValue()); |
| 220 | return CurDAG->getTargetConstant(ARM_AM::getSOImmVal(V), MVT::i32); |
| 221 | }]>; |
| 222 | |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 223 | |
| 224 | // Define ARM specific addressing modes. |
| 225 | |
| 226 | // addrmode2 := reg +/- reg shop imm |
| 227 | // addrmode2 := reg +/- imm12 |
| 228 | // |
| 229 | def addrmode2 : Operand<i32>, |
| 230 | ComplexPattern<i32, 3, "SelectAddrMode2", []> { |
| 231 | let PrintMethod = "printAddrMode2Operand"; |
| 232 | let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm); |
| 233 | } |
| 234 | |
| 235 | def am2offset : Operand<i32>, |
| 236 | ComplexPattern<i32, 2, "SelectAddrMode2Offset", []> { |
| 237 | let PrintMethod = "printAddrMode2OffsetOperand"; |
| 238 | let MIOperandInfo = (ops GPR, i32imm); |
| 239 | } |
| 240 | |
| 241 | // addrmode3 := reg +/- reg |
| 242 | // addrmode3 := reg +/- imm8 |
| 243 | // |
| 244 | def addrmode3 : Operand<i32>, |
| 245 | ComplexPattern<i32, 3, "SelectAddrMode3", []> { |
| 246 | let PrintMethod = "printAddrMode3Operand"; |
| 247 | let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm); |
| 248 | } |
| 249 | |
| 250 | def am3offset : Operand<i32>, |
| 251 | ComplexPattern<i32, 2, "SelectAddrMode3Offset", []> { |
| 252 | let PrintMethod = "printAddrMode3OffsetOperand"; |
| 253 | let MIOperandInfo = (ops GPR, i32imm); |
| 254 | } |
| 255 | |
| 256 | // addrmode4 := reg, <mode|W> |
| 257 | // |
| 258 | def addrmode4 : Operand<i32>, |
| 259 | ComplexPattern<i32, 2, "", []> { |
| 260 | let PrintMethod = "printAddrMode4Operand"; |
| 261 | let MIOperandInfo = (ops GPR, i32imm); |
| 262 | } |
| 263 | |
| 264 | // addrmode5 := reg +/- imm8*4 |
| 265 | // |
| 266 | def addrmode5 : Operand<i32>, |
| 267 | ComplexPattern<i32, 2, "SelectAddrMode5", []> { |
| 268 | let PrintMethod = "printAddrMode5Operand"; |
| 269 | let MIOperandInfo = (ops GPR, i32imm); |
| 270 | } |
| 271 | |
| 272 | // addrmodepc := pc + reg |
| 273 | // |
| 274 | def addrmodepc : Operand<i32>, |
| 275 | ComplexPattern<i32, 2, "SelectAddrModePC", []> { |
| 276 | let PrintMethod = "printAddrModePCOperand"; |
| 277 | let MIOperandInfo = (ops GPR, i32imm); |
| 278 | } |
| 279 | |
Evan Cheng | 42d712b | 2007-05-08 21:08:43 +0000 | [diff] [blame] | 280 | // ARM branch / cmov condition code operand. |
Evan Cheng | 5ada199 | 2007-05-16 20:50:01 +0000 | [diff] [blame] | 281 | def ccop : Operand<i32> { |
Evan Cheng | 42d712b | 2007-05-08 21:08:43 +0000 | [diff] [blame] | 282 | let PrintMethod = "printPredicateOperand"; |
| 283 | } |
| 284 | |
| 285 | // ARM Predicate operand. Default to 14 = always (AL). |
| 286 | def pred : PredicateOperand<i32, (ops i32imm), (ops (i32 14))> { |
| 287 | let PrintMethod = "printPredicateOperand"; |
| 288 | } |
| 289 | |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 290 | //===----------------------------------------------------------------------===// |
| 291 | // ARM Instruction flags. These need to match ARMInstrInfo.h. |
| 292 | // |
| 293 | |
| 294 | // Addressing mode. |
| 295 | class AddrMode<bits<4> val> { |
| 296 | bits<4> Value = val; |
| 297 | } |
| 298 | def AddrModeNone : AddrMode<0>; |
| 299 | def AddrMode1 : AddrMode<1>; |
| 300 | def AddrMode2 : AddrMode<2>; |
| 301 | def AddrMode3 : AddrMode<3>; |
| 302 | def AddrMode4 : AddrMode<4>; |
| 303 | def AddrMode5 : AddrMode<5>; |
| 304 | def AddrModeT1 : AddrMode<6>; |
| 305 | def AddrModeT2 : AddrMode<7>; |
| 306 | def AddrModeT4 : AddrMode<8>; |
| 307 | def AddrModeTs : AddrMode<9>; |
| 308 | |
| 309 | // Instruction size. |
| 310 | class SizeFlagVal<bits<3> val> { |
| 311 | bits<3> Value = val; |
| 312 | } |
| 313 | def SizeInvalid : SizeFlagVal<0>; // Unset. |
| 314 | def SizeSpecial : SizeFlagVal<1>; // Pseudo or special. |
| 315 | def Size8Bytes : SizeFlagVal<2>; |
| 316 | def Size4Bytes : SizeFlagVal<3>; |
| 317 | def Size2Bytes : SizeFlagVal<4>; |
| 318 | |
| 319 | // Load / store index mode. |
| 320 | class IndexMode<bits<2> val> { |
| 321 | bits<2> Value = val; |
| 322 | } |
| 323 | def IndexModeNone : IndexMode<0>; |
| 324 | def IndexModePre : IndexMode<1>; |
| 325 | def IndexModePost : IndexMode<2>; |
| 326 | |
| 327 | //===----------------------------------------------------------------------===// |
| 328 | // ARM Instruction templates. |
| 329 | // |
| 330 | |
| 331 | // ARMPat - Same as Pat<>, but requires that the compiler be in ARM mode. |
| 332 | class ARMPat<dag pattern, dag result> : Pat<pattern, result> { |
| 333 | list<Predicate> Predicates = [IsARM]; |
| 334 | } |
Evan Cheng | 34b12d2 | 2007-01-19 20:27:35 +0000 | [diff] [blame] | 335 | class ARMV5TEPat<dag pattern, dag result> : Pat<pattern, result> { |
| 336 | list<Predicate> Predicates = [IsARM, HasV5TE]; |
| 337 | } |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 338 | class ARMV6Pat<dag pattern, dag result> : Pat<pattern, result> { |
| 339 | list<Predicate> Predicates = [IsARM, HasV6]; |
| 340 | } |
| 341 | |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 342 | class InstARM<bits<4> opcod, AddrMode am, SizeFlagVal sz, IndexMode im, |
Evan Cheng | 44bec52 | 2007-05-15 01:29:07 +0000 | [diff] [blame] | 343 | string cstr> |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 344 | : Instruction { |
Rafael Espindola | 7bc59bc | 2006-05-14 22:18:28 +0000 | [diff] [blame] | 345 | let Namespace = "ARM"; |
| 346 | |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 347 | bits<4> Opcode = opcod; |
| 348 | AddrMode AM = am; |
| 349 | bits<4> AddrModeBits = AM.Value; |
| 350 | |
| 351 | SizeFlagVal SZ = sz; |
| 352 | bits<3> SizeFlag = SZ.Value; |
| 353 | |
| 354 | IndexMode IM = im; |
| 355 | bits<2> IndexModeBits = IM.Value; |
| 356 | |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 357 | let Constraints = cstr; |
| 358 | } |
| 359 | |
| 360 | class PseudoInst<dag ops, string asm, list<dag> pattern> |
Evan Cheng | 44bec52 | 2007-05-15 01:29:07 +0000 | [diff] [blame] | 361 | : InstARM<0, AddrModeNone, SizeSpecial, IndexModeNone, ""> { |
| 362 | let OperandList = ops; |
| 363 | let AsmString = asm; |
Rafael Espindola | 7bc59bc | 2006-05-14 22:18:28 +0000 | [diff] [blame] | 364 | let Pattern = pattern; |
| 365 | } |
| 366 | |
Evan Cheng | 5ada199 | 2007-05-16 20:50:01 +0000 | [diff] [blame] | 367 | // Almost all ARM instructions are predicable. |
Evan Cheng | 44bec52 | 2007-05-15 01:29:07 +0000 | [diff] [blame] | 368 | class I<dag oprnds, AddrMode am, SizeFlagVal sz, IndexMode im, |
| 369 | string opc, string asm, string cstr, list<dag> pattern> |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 370 | // FIXME: Set all opcodes to 0 for now. |
Evan Cheng | 44bec52 | 2007-05-15 01:29:07 +0000 | [diff] [blame] | 371 | : InstARM<0, am, sz, im, cstr> { |
| 372 | let OperandList = !con(oprnds, (ops pred:$p)); |
| 373 | let AsmString = !strconcat(opc, !strconcat("$p", asm)); |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 374 | let Pattern = pattern; |
| 375 | list<Predicate> Predicates = [IsARM]; |
| 376 | } |
Rafael Espindola | 15a6c3e | 2006-10-16 17:57:20 +0000 | [diff] [blame] | 377 | |
Evan Cheng | 44bec52 | 2007-05-15 01:29:07 +0000 | [diff] [blame] | 378 | class AI<dag ops, string opc, string asm, list<dag> pattern> |
| 379 | : I<ops, AddrModeNone, Size4Bytes, IndexModeNone, opc, asm, "", pattern>; |
| 380 | class AI1<dag ops, string opc, string asm, list<dag> pattern> |
| 381 | : I<ops, AddrMode1, Size4Bytes, IndexModeNone, opc, asm, "", pattern>; |
| 382 | class AI2<dag ops, string opc, string asm, list<dag> pattern> |
| 383 | : I<ops, AddrMode2, Size4Bytes, IndexModeNone, opc, asm, "", pattern>; |
| 384 | class AI3<dag ops, string opc, string asm, list<dag> pattern> |
| 385 | : I<ops, AddrMode3, Size4Bytes, IndexModeNone, opc, asm, "", pattern>; |
| 386 | class AI4<dag ops, string opc, string asm, list<dag> pattern> |
| 387 | : I<ops, AddrMode4, Size4Bytes, IndexModeNone, opc, asm, "", pattern>; |
| 388 | class AI1x2<dag ops, string opc, string asm, list<dag> pattern> |
| 389 | : I<ops, AddrMode1, Size8Bytes, IndexModeNone, opc, asm, "", pattern>; |
Rafael Espindola | a6f149d | 2006-10-16 18:32:36 +0000 | [diff] [blame] | 390 | |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 391 | // Pre-indexed ops |
Evan Cheng | 44bec52 | 2007-05-15 01:29:07 +0000 | [diff] [blame] | 392 | class AI2pr<dag ops, string opc, string asm, string cstr, list<dag> pattern> |
| 393 | : I<ops, AddrMode2, Size4Bytes, IndexModePre, opc, asm, cstr, pattern>; |
| 394 | class AI3pr<dag ops, string opc, string asm, string cstr, list<dag> pattern> |
| 395 | : I<ops, AddrMode3, Size4Bytes, IndexModePre, opc, asm, cstr, pattern>; |
Rafael Espindola | 27e469e | 2006-10-16 18:39:22 +0000 | [diff] [blame] | 396 | |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 397 | // Post-indexed ops |
Evan Cheng | 44bec52 | 2007-05-15 01:29:07 +0000 | [diff] [blame] | 398 | class AI2po<dag ops, string opc, string asm, string cstr, list<dag> pattern> |
| 399 | : I<ops, AddrMode2, Size4Bytes, IndexModePost, opc, asm, cstr, pattern>; |
| 400 | class AI3po<dag ops, string opc, string asm, string cstr, list<dag> pattern> |
| 401 | : I<ops, AddrMode3, Size4Bytes, IndexModePost, opc, asm, cstr, pattern>; |
Rafael Espindola | 04d88ff | 2006-10-17 20:45:22 +0000 | [diff] [blame] | 402 | |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 403 | // BR_JT instructions |
Evan Cheng | 44bec52 | 2007-05-15 01:29:07 +0000 | [diff] [blame] | 404 | class JTI<dag ops, string opc, string asm, list<dag> pattern> |
| 405 | : I<ops, AddrModeNone, SizeSpecial, IndexModeNone, opc, asm, "", pattern>; |
| 406 | class JTI1<dag ops, string opc, string asm, list<dag> pattern> |
| 407 | : I<ops, AddrMode1, SizeSpecial, IndexModeNone, opc, asm, "", pattern>; |
| 408 | class JTI2<dag ops, string opc, string asm, list<dag> pattern> |
| 409 | : I<ops, AddrMode2, SizeSpecial, IndexModeNone, opc, asm, "", pattern>; |
Rafael Espindola | 04d88ff | 2006-10-17 20:45:22 +0000 | [diff] [blame] | 410 | |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 411 | |
| 412 | class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>; |
| 413 | class UnOpFrag <dag res> : PatFrag<(ops node:$Src), res>; |
| 414 | |
| 415 | |
| 416 | /// AI1_bin_irs - Defines a set of (op r, {so_imm|r|so_reg}) patterns for a |
| 417 | /// binop that produces a value. |
| 418 | multiclass AI1_bin_irs<string opc, PatFrag opnode> { |
| 419 | def ri : AI1<(ops GPR:$dst, GPR:$a, so_imm:$b), |
Evan Cheng | 44bec52 | 2007-05-15 01:29:07 +0000 | [diff] [blame] | 420 | opc, " $dst, $a, $b", |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 421 | [(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]>; |
| 422 | def rr : AI1<(ops GPR:$dst, GPR:$a, GPR:$b), |
Evan Cheng | 44bec52 | 2007-05-15 01:29:07 +0000 | [diff] [blame] | 423 | opc, " $dst, $a, $b", |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 424 | [(set GPR:$dst, (opnode GPR:$a, GPR:$b))]>; |
| 425 | def rs : AI1<(ops GPR:$dst, GPR:$a, so_reg:$b), |
Evan Cheng | 44bec52 | 2007-05-15 01:29:07 +0000 | [diff] [blame] | 426 | opc, " $dst, $a, $b", |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 427 | [(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]>; |
| 428 | } |
| 429 | |
| 430 | /// AI1_bin0_irs - Defines a set of (op r, {so_imm|r|so_reg}) patterns. |
| 431 | /// Similar to AI1_bin_irs except the instruction does not produce a result. |
| 432 | multiclass AI1_bin0_irs<string opc, PatFrag opnode> { |
| 433 | def ri : AI1<(ops GPR:$a, so_imm:$b), |
Evan Cheng | 44bec52 | 2007-05-15 01:29:07 +0000 | [diff] [blame] | 434 | opc, " $a, $b", |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 435 | [(opnode GPR:$a, so_imm:$b)]>; |
| 436 | def rr : AI1<(ops GPR:$a, GPR:$b), |
Evan Cheng | 44bec52 | 2007-05-15 01:29:07 +0000 | [diff] [blame] | 437 | opc, " $a, $b", |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 438 | [(opnode GPR:$a, GPR:$b)]>; |
| 439 | def rs : AI1<(ops GPR:$a, so_reg:$b), |
Evan Cheng | 44bec52 | 2007-05-15 01:29:07 +0000 | [diff] [blame] | 440 | opc, " $a, $b", |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 441 | [(opnode GPR:$a, so_reg:$b)]>; |
| 442 | } |
| 443 | |
| 444 | /// AI1_bin_is - Defines a set of (op r, {so_imm|so_reg}) patterns for a binop. |
| 445 | multiclass AI1_bin_is<string opc, PatFrag opnode> { |
| 446 | def ri : AI1<(ops GPR:$dst, GPR:$a, so_imm:$b), |
Evan Cheng | 44bec52 | 2007-05-15 01:29:07 +0000 | [diff] [blame] | 447 | opc, " $dst, $a, $b", |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 448 | [(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]>; |
| 449 | def rs : AI1<(ops GPR:$dst, GPR:$a, so_reg:$b), |
Evan Cheng | 44bec52 | 2007-05-15 01:29:07 +0000 | [diff] [blame] | 450 | opc, " $dst, $a, $b", |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 451 | [(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]>; |
| 452 | } |
| 453 | |
| 454 | /// AI1_unary_irs - Defines a set of (op {so_imm|r|so_reg}) patterns for unary |
| 455 | /// ops. |
| 456 | multiclass AI1_unary_irs<string opc, PatFrag opnode> { |
| 457 | def i : AI1<(ops GPR:$dst, so_imm:$a), |
Evan Cheng | 44bec52 | 2007-05-15 01:29:07 +0000 | [diff] [blame] | 458 | opc, " $dst, $a", |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 459 | [(set GPR:$dst, (opnode so_imm:$a))]>; |
| 460 | def r : AI1<(ops GPR:$dst, GPR:$a), |
Evan Cheng | 44bec52 | 2007-05-15 01:29:07 +0000 | [diff] [blame] | 461 | opc, " $dst, $a", |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 462 | [(set GPR:$dst, (opnode GPR:$a))]>; |
| 463 | def s : AI1<(ops GPR:$dst, so_reg:$a), |
Evan Cheng | 44bec52 | 2007-05-15 01:29:07 +0000 | [diff] [blame] | 464 | opc, " $dst, $a", |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 465 | [(set GPR:$dst, (opnode so_reg:$a))]>; |
| 466 | } |
| 467 | |
| 468 | /// AI_unary_rrot - A unary operation with two forms: one whose operand is a |
| 469 | /// register and one whose operand is a register rotated by 8/16/24. |
| 470 | multiclass AI_unary_rrot<string opc, PatFrag opnode> { |
| 471 | def r : AI<(ops GPR:$dst, GPR:$Src), |
Evan Cheng | 44bec52 | 2007-05-15 01:29:07 +0000 | [diff] [blame] | 472 | opc, " $dst, $Src", |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 473 | [(set GPR:$dst, (opnode GPR:$Src))]>, Requires<[IsARM, HasV6]>; |
| 474 | def r_rot : AI<(ops GPR:$dst, GPR:$Src, i32imm:$rot), |
Evan Cheng | 44bec52 | 2007-05-15 01:29:07 +0000 | [diff] [blame] | 475 | opc, " $dst, $Src, ror $rot", |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 476 | [(set GPR:$dst, (opnode (rotr GPR:$Src, rot_imm:$rot)))]>, |
| 477 | Requires<[IsARM, HasV6]>; |
| 478 | } |
| 479 | |
| 480 | /// AI_bin_rrot - A binary operation with two forms: one whose operand is a |
| 481 | /// register and one whose operand is a register rotated by 8/16/24. |
| 482 | multiclass AI_bin_rrot<string opc, PatFrag opnode> { |
| 483 | def rr : AI<(ops GPR:$dst, GPR:$LHS, GPR:$RHS), |
Evan Cheng | 44bec52 | 2007-05-15 01:29:07 +0000 | [diff] [blame] | 484 | opc, " $dst, $LHS, $RHS", |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 485 | [(set GPR:$dst, (opnode GPR:$LHS, GPR:$RHS))]>, |
| 486 | Requires<[IsARM, HasV6]>; |
| 487 | def rr_rot : AI<(ops GPR:$dst, GPR:$LHS, GPR:$RHS, i32imm:$rot), |
Evan Cheng | 44bec52 | 2007-05-15 01:29:07 +0000 | [diff] [blame] | 488 | opc, " $dst, $LHS, $RHS, ror $rot", |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 489 | [(set GPR:$dst, (opnode GPR:$LHS, |
| 490 | (rotr GPR:$RHS, rot_imm:$rot)))]>, |
| 491 | Requires<[IsARM, HasV6]>; |
| 492 | } |
| 493 | |
Evan Cheng | 44bec52 | 2007-05-15 01:29:07 +0000 | [diff] [blame] | 494 | // Special cases. |
| 495 | class XI<dag oprnds, AddrMode am, SizeFlagVal sz, IndexMode im, |
| 496 | string asm, string cstr, list<dag> pattern> |
| 497 | // FIXME: Set all opcodes to 0 for now. |
| 498 | : InstARM<0, am, sz, im, cstr> { |
| 499 | let OperandList = oprnds; |
| 500 | let AsmString = asm; |
| 501 | let Pattern = pattern; |
| 502 | list<Predicate> Predicates = [IsARM]; |
| 503 | } |
| 504 | |
| 505 | class AXI<dag ops, string asm, list<dag> pattern> |
| 506 | : XI<ops, AddrModeNone, Size4Bytes, IndexModeNone, asm, "", pattern>; |
| 507 | class AXI1<dag ops, string asm, list<dag> pattern> |
| 508 | : XI<ops, AddrMode1, Size4Bytes, IndexModeNone, asm, "", pattern>; |
| 509 | class AXI2<dag ops, string asm, list<dag> pattern> |
| 510 | : XI<ops, AddrMode2, Size4Bytes, IndexModeNone, asm, "", pattern>; |
Dale Johannesen | f23b8cf | 2007-05-21 22:42:04 +0000 | [diff] [blame^] | 511 | class AXI3<dag ops, string asm, list<dag> pattern> |
| 512 | : XI<ops, AddrMode3, Size4Bytes, IndexModeNone, asm, "", pattern>; |
Evan Cheng | 44bec52 | 2007-05-15 01:29:07 +0000 | [diff] [blame] | 513 | class AXI4<dag ops, string asm, list<dag> pattern> |
| 514 | : XI<ops, AddrMode4, Size4Bytes, IndexModeNone, asm, "", pattern>; |
| 515 | |
| 516 | class AXIx2<dag ops, string asm, list<dag> pattern> |
| 517 | : XI<ops, AddrModeNone, Size8Bytes, IndexModeNone, asm, "", pattern>; |
| 518 | |
Rafael Espindola | 90057aa | 2006-10-16 18:18:14 +0000 | [diff] [blame] | 519 | |
Rafael Espindola | 15a6c3e | 2006-10-16 17:57:20 +0000 | [diff] [blame] | 520 | //===----------------------------------------------------------------------===// |
| 521 | // Instructions |
| 522 | //===----------------------------------------------------------------------===// |
| 523 | |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 524 | //===----------------------------------------------------------------------===// |
| 525 | // Miscellaneous Instructions. |
| 526 | // |
| 527 | def IMPLICIT_DEF_GPR : |
Evan Cheng | 44bec52 | 2007-05-15 01:29:07 +0000 | [diff] [blame] | 528 | PseudoInst<(ops GPR:$rD, pred:$p), |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 529 | "@ IMPLICIT_DEF_GPR $rD", |
| 530 | [(set GPR:$rD, (undef))]>; |
Rafael Espindola | 687bc49 | 2006-08-24 13:45:55 +0000 | [diff] [blame] | 531 | |
Rafael Espindola | 6f602de | 2006-08-24 16:13:15 +0000 | [diff] [blame] | 532 | |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 533 | /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool in |
| 534 | /// the function. The first operand is the ID# for this instruction, the second |
| 535 | /// is the index into the MachineConstantPool that this is, the third is the |
| 536 | /// size in bytes of this constant pool entry. |
| 537 | def CONSTPOOL_ENTRY : |
| 538 | PseudoInst<(ops cpinst_operand:$instid, cpinst_operand:$cpidx, i32imm:$size), |
| 539 | "${instid:label} ${cpidx:cpentry}", []>; |
Rafael Espindola | 7bc59bc | 2006-05-14 22:18:28 +0000 | [diff] [blame] | 540 | |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 541 | def ADJCALLSTACKUP : |
Evan Cheng | 44bec52 | 2007-05-15 01:29:07 +0000 | [diff] [blame] | 542 | PseudoInst<(ops i32imm:$amt, pred:$p), |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 543 | "@ ADJCALLSTACKUP $amt", |
| 544 | [(ARMcallseq_end imm:$amt)]>, Imp<[SP],[SP]>; |
Rafael Espindola | cdda88c | 2006-08-24 17:19:08 +0000 | [diff] [blame] | 545 | |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 546 | def ADJCALLSTACKDOWN : |
Evan Cheng | 44bec52 | 2007-05-15 01:29:07 +0000 | [diff] [blame] | 547 | PseudoInst<(ops i32imm:$amt, pred:$p), |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 548 | "@ ADJCALLSTACKDOWN $amt", |
| 549 | [(ARMcallseq_start imm:$amt)]>, Imp<[SP],[SP]>; |
Rafael Espindola | 3c000bf | 2006-08-21 22:00:32 +0000 | [diff] [blame] | 550 | |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 551 | def DWARF_LOC : |
| 552 | PseudoInst<(ops i32imm:$line, i32imm:$col, i32imm:$file), |
| 553 | ".loc $file, $line, $col", |
| 554 | [(dwarf_loc (i32 imm:$line), (i32 imm:$col), (i32 imm:$file))]>; |
Rafael Espindola | 4b20fbc | 2006-10-10 12:56:00 +0000 | [diff] [blame] | 555 | |
Evan Cheng | 44bec52 | 2007-05-15 01:29:07 +0000 | [diff] [blame] | 556 | def PICADD : AXI1<(ops GPR:$dst, GPR:$a, pclabel:$cp, pred:$p), |
| 557 | "$cp:\n\tadd$p $dst, pc, $a", |
| 558 | [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>; |
Dale Johannesen | 86d4069 | 2007-05-21 22:14:33 +0000 | [diff] [blame] | 559 | |
| 560 | let isLoad = 1, AddedComplexity = 10 in { |
| 561 | def PICLD : AXI2<(ops GPR:$dst, addrmodepc:$addr, pred:$p), |
Evan Cheng | 44bec52 | 2007-05-15 01:29:07 +0000 | [diff] [blame] | 562 | "${addr:label}:\n\tldr$p $dst, $addr", |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 563 | [(set GPR:$dst, (load addrmodepc:$addr))]>; |
Rafael Espindola | 84b19be | 2006-07-16 01:02:57 +0000 | [diff] [blame] | 564 | |
Dale Johannesen | f23b8cf | 2007-05-21 22:42:04 +0000 | [diff] [blame^] | 565 | def PICLDZH : AXI3<(ops GPR:$dst, addrmodepc:$addr, pred:$p), |
Dale Johannesen | 86d4069 | 2007-05-21 22:14:33 +0000 | [diff] [blame] | 566 | "${addr:label}:\n\tldr${p}h $dst, $addr", |
| 567 | [(set GPR:$dst, (zextloadi16 addrmodepc:$addr))]>; |
| 568 | |
| 569 | def PICLDZB : AXI2<(ops GPR:$dst, addrmodepc:$addr, pred:$p), |
| 570 | "${addr:label}:\n\tldr${p}b $dst, $addr", |
| 571 | [(set GPR:$dst, (zextloadi8 addrmodepc:$addr))]>; |
| 572 | |
Dale Johannesen | f23b8cf | 2007-05-21 22:42:04 +0000 | [diff] [blame^] | 573 | def PICLDH : AXI3<(ops GPR:$dst, addrmodepc:$addr, pred:$p), |
Dale Johannesen | 86d4069 | 2007-05-21 22:14:33 +0000 | [diff] [blame] | 574 | "${addr:label}:\n\tldr${p}h $dst, $addr", |
| 575 | [(set GPR:$dst, (extloadi16 addrmodepc:$addr))]>; |
| 576 | |
| 577 | def PICLDB : AXI2<(ops GPR:$dst, addrmodepc:$addr, pred:$p), |
| 578 | "${addr:label}:\n\tldr${p}b $dst, $addr", |
| 579 | [(set GPR:$dst, (extloadi8 addrmodepc:$addr))]>; |
| 580 | |
Dale Johannesen | f23b8cf | 2007-05-21 22:42:04 +0000 | [diff] [blame^] | 581 | def PICLDSH : AXI3<(ops GPR:$dst, addrmodepc:$addr, pred:$p), |
Dale Johannesen | 86d4069 | 2007-05-21 22:14:33 +0000 | [diff] [blame] | 582 | "${addr:label}:\n\tldr${p}sh $dst, $addr", |
| 583 | [(set GPR:$dst, (sextloadi16 addrmodepc:$addr))]>; |
| 584 | |
Dale Johannesen | f23b8cf | 2007-05-21 22:42:04 +0000 | [diff] [blame^] | 585 | def PICLDSB : AXI3<(ops GPR:$dst, addrmodepc:$addr, pred:$p), |
Dale Johannesen | 86d4069 | 2007-05-21 22:14:33 +0000 | [diff] [blame] | 586 | "${addr:label}:\n\tldr${p}sb $dst, $addr", |
| 587 | [(set GPR:$dst, (sextloadi8 addrmodepc:$addr))]>; |
| 588 | } |
| 589 | let isStore = 1, AddedComplexity = 10 in { |
| 590 | def PICSTR : AXI2<(ops GPR:$src, addrmodepc:$addr, pred:$p), |
| 591 | "${addr:label}:\n\tstr$p $src, $addr", |
| 592 | [(store GPR:$src, addrmodepc:$addr)]>; |
| 593 | |
Dale Johannesen | f23b8cf | 2007-05-21 22:42:04 +0000 | [diff] [blame^] | 594 | def PICSTRH : AXI3<(ops GPR:$src, addrmodepc:$addr, pred:$p), |
Dale Johannesen | 86d4069 | 2007-05-21 22:14:33 +0000 | [diff] [blame] | 595 | "${addr:label}:\n\tstr${p}h $src, $addr", |
| 596 | [(truncstorei16 GPR:$src, addrmodepc:$addr)]>; |
| 597 | |
| 598 | def PICSTRB : AXI2<(ops GPR:$src, addrmodepc:$addr, pred:$p), |
| 599 | "${addr:label}:\n\tstr${p}b $src, $addr", |
| 600 | [(truncstorei8 GPR:$src, addrmodepc:$addr)]>; |
| 601 | } |
| 602 | |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 603 | //===----------------------------------------------------------------------===// |
| 604 | // Control Flow Instructions. |
| 605 | // |
Rafael Espindola | 9e071f0 | 2006-10-02 19:30:56 +0000 | [diff] [blame] | 606 | |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 607 | let isReturn = 1, isTerminator = 1 in |
Evan Cheng | 44bec52 | 2007-05-15 01:29:07 +0000 | [diff] [blame] | 608 | def BX_RET : AI<(ops), "bx", " lr", [(ARMretflag)]>; |
Rafael Espindola | 2718519 | 2006-09-29 21:20:16 +0000 | [diff] [blame] | 609 | |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 610 | // FIXME: remove when we have a way to marking a MI with these properties. |
| 611 | let isLoad = 1, isReturn = 1, isTerminator = 1 in |
Evan Cheng | 44bec52 | 2007-05-15 01:29:07 +0000 | [diff] [blame] | 612 | def LDM_RET : AXI4<(ops addrmode4:$addr, pred:$p, reglist:$dst1, variable_ops), |
| 613 | "ldm${p}${addr:submode} $addr, $dst1", |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 614 | []>; |
Rafael Espindola | a284584 | 2006-10-05 16:48:49 +0000 | [diff] [blame] | 615 | |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 616 | let isCall = 1, noResults = 1, |
| 617 | Defs = [R0, R1, R2, R3, R12, LR, |
| 618 | D0, D1, D2, D3, D4, D5, D6, D7] in { |
Evan Cheng | dcc50a4 | 2007-05-18 01:53:54 +0000 | [diff] [blame] | 619 | def BL : AXI<(ops i32imm:$func, variable_ops), |
| 620 | "bl ${func:call}", |
Evan Cheng | 44bec52 | 2007-05-15 01:29:07 +0000 | [diff] [blame] | 621 | [(ARMcall tglobaladdr:$func)]>; |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 622 | // ARMv5T and above |
Evan Cheng | dcc50a4 | 2007-05-18 01:53:54 +0000 | [diff] [blame] | 623 | def BLX : AXI<(ops GPR:$dst, variable_ops), |
| 624 | "blx $dst", |
Evan Cheng | 44bec52 | 2007-05-15 01:29:07 +0000 | [diff] [blame] | 625 | [(ARMcall GPR:$dst)]>, Requires<[IsARM, HasV5T]>; |
Lauro Ramos Venancio | 64c88d7 | 2007-03-20 17:57:23 +0000 | [diff] [blame] | 626 | let Uses = [LR] in { |
| 627 | // ARMv4T |
Evan Cheng | dcc50a4 | 2007-05-18 01:53:54 +0000 | [diff] [blame] | 628 | def BX : AXIx2<(ops GPR:$dst, variable_ops), |
| 629 | "mov lr, pc\n\tbx $dst", |
Lauro Ramos Venancio | b8a93a4 | 2007-03-27 16:19:21 +0000 | [diff] [blame] | 630 | [(ARMcall_nolink GPR:$dst)]>; |
Lauro Ramos Venancio | 64c88d7 | 2007-03-20 17:57:23 +0000 | [diff] [blame] | 631 | } |
Rafael Espindola | 3557463 | 2006-07-18 17:00:30 +0000 | [diff] [blame] | 632 | } |
Rafael Espindola | dc124a2 | 2006-05-18 21:45:49 +0000 | [diff] [blame] | 633 | |
Evan Cheng | aeafca0 | 2007-05-16 07:45:54 +0000 | [diff] [blame] | 634 | let isBranch = 1, isTerminator = 1, noResults = 1 in { |
Evan Cheng | 5ada199 | 2007-05-16 20:50:01 +0000 | [diff] [blame] | 635 | // B is "predicable" since it can be xformed into a Bcc. |
Evan Cheng | aeafca0 | 2007-05-16 07:45:54 +0000 | [diff] [blame] | 636 | let isBarrier = 1 in { |
Evan Cheng | 5ada199 | 2007-05-16 20:50:01 +0000 | [diff] [blame] | 637 | let isPredicable = 1 in |
| 638 | def B : AXI<(ops brtarget:$dst), "b $dst", |
| 639 | [(br bb:$dst)]>; |
Evan Cheng | 44bec52 | 2007-05-15 01:29:07 +0000 | [diff] [blame] | 640 | |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 641 | def BR_JTr : JTI<(ops GPR:$dst, jtblock_operand:$jt, i32imm:$id), |
Evan Cheng | 44bec52 | 2007-05-15 01:29:07 +0000 | [diff] [blame] | 642 | "mov", " pc, $dst \n$jt", |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 643 | [(ARMbrjt GPR:$dst, tjumptable:$jt, imm:$id)]>; |
| 644 | def BR_JTm : JTI2<(ops addrmode2:$dst, jtblock_operand:$jt, i32imm:$id), |
Evan Cheng | 44bec52 | 2007-05-15 01:29:07 +0000 | [diff] [blame] | 645 | "ldr", " pc, $dst \n$jt", |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 646 | [(ARMbrjt (i32 (load addrmode2:$dst)), tjumptable:$jt, |
| 647 | imm:$id)]>; |
| 648 | def BR_JTadd : JTI1<(ops GPR:$dst, GPR:$idx, jtblock_operand:$jt, i32imm:$id), |
Evan Cheng | 44bec52 | 2007-05-15 01:29:07 +0000 | [diff] [blame] | 649 | "add", " pc, $dst, $idx \n$jt", |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 650 | [(ARMbrjt (add GPR:$dst, GPR:$idx), tjumptable:$jt, |
| 651 | imm:$id)]>; |
Evan Cheng | aeafca0 | 2007-05-16 07:45:54 +0000 | [diff] [blame] | 652 | } |
| 653 | |
| 654 | def Bcc : AXI<(ops brtarget:$dst, ccop:$cc), "b$cc $dst", |
| 655 | [(ARMbrcond bb:$dst, imm:$cc)]>; |
Rafael Espindola | 1ed3af1 | 2006-08-01 18:53:10 +0000 | [diff] [blame] | 656 | } |
Rafael Espindola | 84b19be | 2006-07-16 01:02:57 +0000 | [diff] [blame] | 657 | |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 658 | //===----------------------------------------------------------------------===// |
| 659 | // Load / store Instructions. |
| 660 | // |
Rafael Espindola | 82c678b | 2006-10-16 17:17:22 +0000 | [diff] [blame] | 661 | |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 662 | // Load |
| 663 | let isLoad = 1 in { |
| 664 | def LDR : AI2<(ops GPR:$dst, addrmode2:$addr), |
Evan Cheng | 44bec52 | 2007-05-15 01:29:07 +0000 | [diff] [blame] | 665 | "ldr", " $dst, $addr", |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 666 | [(set GPR:$dst, (load addrmode2:$addr))]>; |
Rafael Espindola | 82c678b | 2006-10-16 17:17:22 +0000 | [diff] [blame] | 667 | |
Evan Cheng | fa775d0 | 2007-03-19 07:20:03 +0000 | [diff] [blame] | 668 | // Special LDR for loads from non-pc-relative constpools. |
| 669 | let isReMaterializable = 1 in |
| 670 | def LDRcp : AI2<(ops GPR:$dst, addrmode2:$addr), |
Evan Cheng | 44bec52 | 2007-05-15 01:29:07 +0000 | [diff] [blame] | 671 | "ldr", " $dst, $addr", []>; |
Evan Cheng | fa775d0 | 2007-03-19 07:20:03 +0000 | [diff] [blame] | 672 | |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 673 | // Loads with zero extension |
| 674 | def LDRH : AI3<(ops GPR:$dst, addrmode3:$addr), |
Evan Cheng | 44bec52 | 2007-05-15 01:29:07 +0000 | [diff] [blame] | 675 | "ldrh", " $dst, $addr", |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 676 | [(set GPR:$dst, (zextloadi16 addrmode3:$addr))]>; |
Rafael Espindola | 82c678b | 2006-10-16 17:17:22 +0000 | [diff] [blame] | 677 | |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 678 | def LDRB : AI2<(ops GPR:$dst, addrmode2:$addr), |
Evan Cheng | 44bec52 | 2007-05-15 01:29:07 +0000 | [diff] [blame] | 679 | "ldrb", " $dst, $addr", |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 680 | [(set GPR:$dst, (zextloadi8 addrmode2:$addr))]>; |
Rafael Espindola | 82c678b | 2006-10-16 17:17:22 +0000 | [diff] [blame] | 681 | |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 682 | // Loads with sign extension |
| 683 | def LDRSH : AI3<(ops GPR:$dst, addrmode3:$addr), |
Evan Cheng | 44bec52 | 2007-05-15 01:29:07 +0000 | [diff] [blame] | 684 | "ldrsh", " $dst, $addr", |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 685 | [(set GPR:$dst, (sextloadi16 addrmode3:$addr))]>; |
Rafael Espindola | 7bc59bc | 2006-05-14 22:18:28 +0000 | [diff] [blame] | 686 | |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 687 | def LDRSB : AI3<(ops GPR:$dst, addrmode3:$addr), |
Evan Cheng | 44bec52 | 2007-05-15 01:29:07 +0000 | [diff] [blame] | 688 | "ldrsb", " $dst, $addr", |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 689 | [(set GPR:$dst, (sextloadi8 addrmode3:$addr))]>; |
Rafael Espindola | c391d16 | 2006-10-23 20:34:27 +0000 | [diff] [blame] | 690 | |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 691 | // Load doubleword |
| 692 | def LDRD : AI3<(ops GPR:$dst, addrmode3:$addr), |
Evan Cheng | 44bec52 | 2007-05-15 01:29:07 +0000 | [diff] [blame] | 693 | "ldrd", " $dst, $addr", |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 694 | []>, Requires<[IsARM, HasV5T]>; |
Rafael Espindola | c391d16 | 2006-10-23 20:34:27 +0000 | [diff] [blame] | 695 | |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 696 | // Indexed loads |
| 697 | def LDR_PRE : AI2pr<(ops GPR:$dst, GPR:$base_wb, addrmode2:$addr), |
Evan Cheng | 44bec52 | 2007-05-15 01:29:07 +0000 | [diff] [blame] | 698 | "ldr", " $dst, $addr!", "$addr.base = $base_wb", []>; |
Rafael Espindola | dc124a2 | 2006-05-18 21:45:49 +0000 | [diff] [blame] | 699 | |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 700 | def LDR_POST : AI2po<(ops GPR:$dst, GPR:$base_wb, GPR:$base, am2offset:$offset), |
Evan Cheng | 44bec52 | 2007-05-15 01:29:07 +0000 | [diff] [blame] | 701 | "ldr", " $dst, [$base], $offset", "$base = $base_wb", []>; |
Rafael Espindola | 450856d | 2006-12-12 00:37:38 +0000 | [diff] [blame] | 702 | |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 703 | def LDRH_PRE : AI3pr<(ops GPR:$dst, GPR:$base_wb, addrmode3:$addr), |
Evan Cheng | 44bec52 | 2007-05-15 01:29:07 +0000 | [diff] [blame] | 704 | "ldrh", " $dst, $addr!", "$addr.base = $base_wb", []>; |
Rafael Espindola | 4e30764 | 2006-09-08 16:59:47 +0000 | [diff] [blame] | 705 | |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 706 | def LDRH_POST : AI3po<(ops GPR:$dst, GPR:$base_wb, GPR:$base,am3offset:$offset), |
Evan Cheng | 44bec52 | 2007-05-15 01:29:07 +0000 | [diff] [blame] | 707 | "ldrh", " $dst, [$base], $offset", "$base = $base_wb", []>; |
Lauro Ramos Venancio | 301009a | 2006-12-28 13:11:14 +0000 | [diff] [blame] | 708 | |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 709 | def LDRB_PRE : AI2pr<(ops GPR:$dst, GPR:$base_wb, addrmode2:$addr), |
Evan Cheng | 44bec52 | 2007-05-15 01:29:07 +0000 | [diff] [blame] | 710 | "ldrb", " $dst, $addr!", "$addr.base = $base_wb", []>; |
Lauro Ramos Venancio | 301009a | 2006-12-28 13:11:14 +0000 | [diff] [blame] | 711 | |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 712 | def LDRB_POST : AI2po<(ops GPR:$dst, GPR:$base_wb, GPR:$base,am2offset:$offset), |
Evan Cheng | 44bec52 | 2007-05-15 01:29:07 +0000 | [diff] [blame] | 713 | "ldrb", " $dst, [$base], $offset", "$base = $base_wb", []>; |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 714 | |
| 715 | def LDRSH_PRE : AI3pr<(ops GPR:$dst, GPR:$base_wb, addrmode3:$addr), |
Evan Cheng | 44bec52 | 2007-05-15 01:29:07 +0000 | [diff] [blame] | 716 | "ldrsh", " $dst, $addr!", "$addr.base = $base_wb", []>; |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 717 | |
| 718 | def LDRSH_POST: AI3po<(ops GPR:$dst, GPR:$base_wb, GPR:$base,am3offset:$offset), |
Evan Cheng | 44bec52 | 2007-05-15 01:29:07 +0000 | [diff] [blame] | 719 | "ldrsh", " $dst, [$base], $offset", "$base = $base_wb", []>; |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 720 | |
| 721 | def LDRSB_PRE : AI3pr<(ops GPR:$dst, GPR:$base_wb, addrmode3:$addr), |
Evan Cheng | 44bec52 | 2007-05-15 01:29:07 +0000 | [diff] [blame] | 722 | "ldrsb", " $dst, $addr!", "$addr.base = $base_wb", []>; |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 723 | |
| 724 | def LDRSB_POST: AI3po<(ops GPR:$dst, GPR:$base_wb, GPR:$base,am3offset:$offset), |
Evan Cheng | 44bec52 | 2007-05-15 01:29:07 +0000 | [diff] [blame] | 725 | "ldrsb", " $dst, [$base], $offset", "$base = $base_wb", []>; |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 726 | } // isLoad |
| 727 | |
| 728 | // Store |
| 729 | let isStore = 1 in { |
| 730 | def STR : AI2<(ops GPR:$src, addrmode2:$addr), |
Evan Cheng | 44bec52 | 2007-05-15 01:29:07 +0000 | [diff] [blame] | 731 | "str", " $src, $addr", |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 732 | [(store GPR:$src, addrmode2:$addr)]>; |
| 733 | |
| 734 | // Stores with truncate |
| 735 | def STRH : AI3<(ops GPR:$src, addrmode3:$addr), |
Evan Cheng | 44bec52 | 2007-05-15 01:29:07 +0000 | [diff] [blame] | 736 | "strh", " $src, $addr", |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 737 | [(truncstorei16 GPR:$src, addrmode3:$addr)]>; |
| 738 | |
| 739 | def STRB : AI2<(ops GPR:$src, addrmode2:$addr), |
Evan Cheng | 44bec52 | 2007-05-15 01:29:07 +0000 | [diff] [blame] | 740 | "strb", " $src, $addr", |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 741 | [(truncstorei8 GPR:$src, addrmode2:$addr)]>; |
| 742 | |
| 743 | // Store doubleword |
| 744 | def STRD : AI3<(ops GPR:$src, addrmode3:$addr), |
Evan Cheng | 44bec52 | 2007-05-15 01:29:07 +0000 | [diff] [blame] | 745 | "strd", " $src, $addr", |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 746 | []>, Requires<[IsARM, HasV5T]>; |
| 747 | |
| 748 | // Indexed stores |
| 749 | def STR_PRE : AI2pr<(ops GPR:$base_wb, GPR:$src, GPR:$base, am2offset:$offset), |
Evan Cheng | 44bec52 | 2007-05-15 01:29:07 +0000 | [diff] [blame] | 750 | "str", " $src, [$base, $offset]!", "$base = $base_wb", |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 751 | [(set GPR:$base_wb, |
| 752 | (pre_store GPR:$src, GPR:$base, am2offset:$offset))]>; |
| 753 | |
| 754 | def STR_POST : AI2po<(ops GPR:$base_wb, GPR:$src, GPR:$base,am2offset:$offset), |
Evan Cheng | 44bec52 | 2007-05-15 01:29:07 +0000 | [diff] [blame] | 755 | "str", " $src, [$base], $offset", "$base = $base_wb", |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 756 | [(set GPR:$base_wb, |
| 757 | (post_store GPR:$src, GPR:$base, am2offset:$offset))]>; |
| 758 | |
| 759 | def STRH_PRE : AI3pr<(ops GPR:$base_wb, GPR:$src, GPR:$base,am3offset:$offset), |
Evan Cheng | 44bec52 | 2007-05-15 01:29:07 +0000 | [diff] [blame] | 760 | "strh", " $src, [$base, $offset]!", "$base = $base_wb", |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 761 | [(set GPR:$base_wb, |
| 762 | (pre_truncsti16 GPR:$src, GPR:$base,am3offset:$offset))]>; |
| 763 | |
| 764 | def STRH_POST: AI3po<(ops GPR:$base_wb, GPR:$src, GPR:$base,am3offset:$offset), |
Evan Cheng | 44bec52 | 2007-05-15 01:29:07 +0000 | [diff] [blame] | 765 | "strh", " $src, [$base], $offset", "$base = $base_wb", |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 766 | [(set GPR:$base_wb, (post_truncsti16 GPR:$src, |
| 767 | GPR:$base, am3offset:$offset))]>; |
| 768 | |
| 769 | def STRB_PRE : AI2pr<(ops GPR:$base_wb, GPR:$src, GPR:$base,am2offset:$offset), |
Evan Cheng | 44bec52 | 2007-05-15 01:29:07 +0000 | [diff] [blame] | 770 | "strb", " $src, [$base, $offset]!", "$base = $base_wb", |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 771 | [(set GPR:$base_wb, (pre_truncsti8 GPR:$src, |
| 772 | GPR:$base, am2offset:$offset))]>; |
| 773 | |
| 774 | def STRB_POST: AI2po<(ops GPR:$base_wb, GPR:$src, GPR:$base,am2offset:$offset), |
Evan Cheng | 44bec52 | 2007-05-15 01:29:07 +0000 | [diff] [blame] | 775 | "strb", " $src, [$base], $offset", "$base = $base_wb", |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 776 | [(set GPR:$base_wb, (post_truncsti8 GPR:$src, |
| 777 | GPR:$base, am2offset:$offset))]>; |
| 778 | } // isStore |
| 779 | |
| 780 | //===----------------------------------------------------------------------===// |
| 781 | // Load / store multiple Instructions. |
| 782 | // |
| 783 | |
| 784 | let isLoad = 1 in |
Evan Cheng | 44bec52 | 2007-05-15 01:29:07 +0000 | [diff] [blame] | 785 | def LDM : AXI4<(ops addrmode4:$addr, pred:$p, reglist:$dst1, variable_ops), |
| 786 | "ldm${p}${addr:submode} $addr, $dst1", |
| 787 | []>; |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 788 | |
| 789 | let isStore = 1 in |
Evan Cheng | 44bec52 | 2007-05-15 01:29:07 +0000 | [diff] [blame] | 790 | def STM : AXI4<(ops addrmode4:$addr, pred:$p, reglist:$src1, variable_ops), |
| 791 | "stm${p}${addr:submode} $addr, $src1", |
| 792 | []>; |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 793 | |
| 794 | //===----------------------------------------------------------------------===// |
| 795 | // Move Instructions. |
| 796 | // |
| 797 | |
Evan Cheng | 9f6636f | 2007-03-19 07:48:02 +0000 | [diff] [blame] | 798 | def MOVr : AI1<(ops GPR:$dst, GPR:$src), |
Evan Cheng | 44bec52 | 2007-05-15 01:29:07 +0000 | [diff] [blame] | 799 | "mov", " $dst, $src", []>; |
Evan Cheng | 9f6636f | 2007-03-19 07:48:02 +0000 | [diff] [blame] | 800 | def MOVs : AI1<(ops GPR:$dst, so_reg:$src), |
Evan Cheng | 44bec52 | 2007-05-15 01:29:07 +0000 | [diff] [blame] | 801 | "mov", " $dst, $src", [(set GPR:$dst, so_reg:$src)]>; |
Evan Cheng | a251570 | 2007-03-19 07:09:02 +0000 | [diff] [blame] | 802 | |
| 803 | let isReMaterializable = 1 in |
Evan Cheng | 9f6636f | 2007-03-19 07:48:02 +0000 | [diff] [blame] | 804 | def MOVi : AI1<(ops GPR:$dst, so_imm:$src), |
Evan Cheng | 44bec52 | 2007-05-15 01:29:07 +0000 | [diff] [blame] | 805 | "mov", " $dst, $src", [(set GPR:$dst, so_imm:$src)]>; |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 806 | |
| 807 | // These aren't really mov instructions, but we have to define them this way |
| 808 | // due to flag operands. |
| 809 | |
| 810 | def MOVsrl_flag : AI1<(ops GPR:$dst, GPR:$src), |
Evan Cheng | 44bec52 | 2007-05-15 01:29:07 +0000 | [diff] [blame] | 811 | "movs", " $dst, $src, lsr #1", |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 812 | [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>; |
| 813 | def MOVsra_flag : AI1<(ops GPR:$dst, GPR:$src), |
Evan Cheng | 44bec52 | 2007-05-15 01:29:07 +0000 | [diff] [blame] | 814 | "movs", " $dst, $src, asr #1", |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 815 | [(set GPR:$dst, (ARMsra_flag GPR:$src))]>; |
Evan Cheng | 9f6636f | 2007-03-19 07:48:02 +0000 | [diff] [blame] | 816 | def MOVrx : AI1<(ops GPR:$dst, GPR:$src), |
Evan Cheng | 44bec52 | 2007-05-15 01:29:07 +0000 | [diff] [blame] | 817 | "mov", " $dst, $src, rrx", |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 818 | [(set GPR:$dst, (ARMrrx GPR:$src))]>; |
| 819 | |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 820 | //===----------------------------------------------------------------------===// |
| 821 | // Extend Instructions. |
| 822 | // |
| 823 | |
| 824 | // Sign extenders |
| 825 | |
| 826 | defm SXTB : AI_unary_rrot<"sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>; |
| 827 | defm SXTH : AI_unary_rrot<"sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>; |
| 828 | |
| 829 | defm SXTAB : AI_bin_rrot<"sxtab", |
| 830 | BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>; |
| 831 | defm SXTAH : AI_bin_rrot<"sxtah", |
| 832 | BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>; |
| 833 | |
| 834 | // TODO: SXT(A){B|H}16 |
| 835 | |
| 836 | // Zero extenders |
| 837 | |
| 838 | let AddedComplexity = 16 in { |
| 839 | defm UXTB : AI_unary_rrot<"uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>; |
| 840 | defm UXTH : AI_unary_rrot<"uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>; |
| 841 | defm UXTB16 : AI_unary_rrot<"uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>; |
| 842 | |
| 843 | def : ARMV6Pat<(and (shl GPR:$Src, 8), 0xFF00FF), |
| 844 | (UXTB16r_rot GPR:$Src, 24)>; |
| 845 | def : ARMV6Pat<(and (srl GPR:$Src, 8), 0xFF00FF), |
| 846 | (UXTB16r_rot GPR:$Src, 8)>; |
| 847 | |
| 848 | defm UXTAB : AI_bin_rrot<"uxtab", |
| 849 | BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>; |
| 850 | defm UXTAH : AI_bin_rrot<"uxtah", |
| 851 | BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>; |
Rafael Espindola | 3c000bf | 2006-08-21 22:00:32 +0000 | [diff] [blame] | 852 | } |
| 853 | |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 854 | // This isn't safe in general, the add is two 16-bit units, not a 32-bit add. |
| 855 | //defm UXTAB16 : xxx<"uxtab16", 0xff00ff>; |
Rafael Espindola | 817e7fd | 2006-09-11 19:24:19 +0000 | [diff] [blame] | 856 | |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 857 | // TODO: UXT(A){B|H}16 |
| 858 | |
| 859 | //===----------------------------------------------------------------------===// |
| 860 | // Arithmetic Instructions. |
| 861 | // |
| 862 | |
| 863 | defm ADD : AI1_bin_irs<"add" , BinOpFrag<(add node:$LHS, node:$RHS)>>; |
| 864 | defm ADDS : AI1_bin_irs<"adds", BinOpFrag<(addc node:$LHS, node:$RHS)>>; |
| 865 | defm ADC : AI1_bin_irs<"adc" , BinOpFrag<(adde node:$LHS, node:$RHS)>>; |
| 866 | defm SUB : AI1_bin_irs<"sub" , BinOpFrag<(sub node:$LHS, node:$RHS)>>; |
| 867 | defm SUBS : AI1_bin_irs<"subs", BinOpFrag<(subc node:$LHS, node:$RHS)>>; |
| 868 | defm SBC : AI1_bin_irs<"sbc" , BinOpFrag<(sube node:$LHS, node:$RHS)>>; |
| 869 | |
| 870 | // These don't define reg/reg forms, because they are handled above. |
| 871 | defm RSB : AI1_bin_is <"rsb" , BinOpFrag<(sub node:$RHS, node:$LHS)>>; |
| 872 | defm RSBS : AI1_bin_is <"rsbs", BinOpFrag<(subc node:$RHS, node:$LHS)>>; |
| 873 | defm RSC : AI1_bin_is <"rsc" , BinOpFrag<(sube node:$RHS, node:$LHS)>>; |
| 874 | |
| 875 | // (sub X, imm) gets canonicalized to (add X, -imm). Match this form. |
| 876 | def : ARMPat<(add GPR:$src, so_imm_neg:$imm), |
| 877 | (SUBri GPR:$src, so_imm_neg:$imm)>; |
| 878 | |
| 879 | //def : ARMPat<(addc GPR:$src, so_imm_neg:$imm), |
| 880 | // (SUBSri GPR:$src, so_imm_neg:$imm)>; |
| 881 | //def : ARMPat<(adde GPR:$src, so_imm_neg:$imm), |
| 882 | // (SBCri GPR:$src, so_imm_neg:$imm)>; |
| 883 | |
| 884 | // Note: These are implemented in C++ code, because they have to generate |
| 885 | // ADD/SUBrs instructions, which use a complex pattern that a xform function |
| 886 | // cannot produce. |
| 887 | // (mul X, 2^n+1) -> (add (X << n), X) |
| 888 | // (mul X, 2^n-1) -> (rsb X, (X << n)) |
| 889 | |
| 890 | |
| 891 | //===----------------------------------------------------------------------===// |
| 892 | // Bitwise Instructions. |
| 893 | // |
| 894 | |
| 895 | defm AND : AI1_bin_irs<"and", BinOpFrag<(and node:$LHS, node:$RHS)>>; |
| 896 | defm ORR : AI1_bin_irs<"orr", BinOpFrag<(or node:$LHS, node:$RHS)>>; |
| 897 | defm EOR : AI1_bin_irs<"eor", BinOpFrag<(xor node:$LHS, node:$RHS)>>; |
| 898 | defm BIC : AI1_bin_irs<"bic", BinOpFrag<(and node:$LHS, (not node:$RHS))>>; |
| 899 | |
Evan Cheng | a251570 | 2007-03-19 07:09:02 +0000 | [diff] [blame] | 900 | def MVNr : AI<(ops GPR:$dst, GPR:$src), |
Evan Cheng | 44bec52 | 2007-05-15 01:29:07 +0000 | [diff] [blame] | 901 | "mvn", " $dst, $src", [(set GPR:$dst, (not GPR:$src))]>; |
Evan Cheng | a251570 | 2007-03-19 07:09:02 +0000 | [diff] [blame] | 902 | def MVNs : AI<(ops GPR:$dst, so_reg:$src), |
Evan Cheng | 44bec52 | 2007-05-15 01:29:07 +0000 | [diff] [blame] | 903 | "mvn", " $dst, $src", [(set GPR:$dst, (not so_reg:$src))]>; |
Evan Cheng | a251570 | 2007-03-19 07:09:02 +0000 | [diff] [blame] | 904 | let isReMaterializable = 1 in |
| 905 | def MVNi : AI<(ops GPR:$dst, so_imm:$imm), |
Evan Cheng | 44bec52 | 2007-05-15 01:29:07 +0000 | [diff] [blame] | 906 | "mvn", " $dst, $imm", [(set GPR:$dst, so_imm_not:$imm)]>; |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 907 | |
| 908 | def : ARMPat<(and GPR:$src, so_imm_not:$imm), |
| 909 | (BICri GPR:$src, so_imm_not:$imm)>; |
| 910 | |
| 911 | //===----------------------------------------------------------------------===// |
| 912 | // Multiply Instructions. |
| 913 | // |
| 914 | |
| 915 | // AI_orr - Defines a (op r, r) pattern. |
| 916 | class AI_orr<string opc, SDNode opnode> |
| 917 | : AI<(ops GPR:$dst, GPR:$a, GPR:$b), |
Evan Cheng | 44bec52 | 2007-05-15 01:29:07 +0000 | [diff] [blame] | 918 | opc, " $dst, $a, $b", |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 919 | [(set GPR:$dst, (opnode GPR:$a, GPR:$b))]>; |
| 920 | |
| 921 | // AI_oorr - Defines a (op (op r, r), r) pattern. |
| 922 | class AI_oorr<string opc, SDNode opnode1, SDNode opnode2> |
| 923 | : AI<(ops GPR:$dst, GPR:$a, GPR:$b, GPR:$c), |
Evan Cheng | 44bec52 | 2007-05-15 01:29:07 +0000 | [diff] [blame] | 924 | opc, " $dst, $a, $b, $c", |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 925 | [(set GPR:$dst, (opnode1 (opnode2 GPR:$a, GPR:$b), GPR:$c))]>; |
| 926 | |
| 927 | def MUL : AI_orr<"mul", mul>; |
| 928 | def MLA : AI_oorr<"mla", add, mul>; |
| 929 | |
| 930 | // Extra precision multiplies with low / high results |
| 931 | def SMULL : AI<(ops GPR:$ldst, GPR:$hdst, GPR:$a, GPR:$b), |
Evan Cheng | 44bec52 | 2007-05-15 01:29:07 +0000 | [diff] [blame] | 932 | "smull", " $ldst, $hdst, $a, $b", |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 933 | []>; |
| 934 | |
| 935 | def UMULL : AI<(ops GPR:$ldst, GPR:$hdst, GPR:$a, GPR:$b), |
Evan Cheng | 44bec52 | 2007-05-15 01:29:07 +0000 | [diff] [blame] | 936 | "umull", " $ldst, $hdst, $a, $b", |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 937 | []>; |
| 938 | |
| 939 | // Multiply + accumulate |
| 940 | def SMLAL : AI<(ops GPR:$ldst, GPR:$hdst, GPR:$a, GPR:$b), |
Evan Cheng | 44bec52 | 2007-05-15 01:29:07 +0000 | [diff] [blame] | 941 | "smlal", " $ldst, $hdst, $a, $b", |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 942 | []>; |
| 943 | |
| 944 | def UMLAL : AI<(ops GPR:$ldst, GPR:$hdst, GPR:$a, GPR:$b), |
Evan Cheng | 44bec52 | 2007-05-15 01:29:07 +0000 | [diff] [blame] | 945 | "umlal", " $ldst, $hdst, $a, $b", |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 946 | []>; |
| 947 | |
| 948 | def UMAAL : AI<(ops GPR:$ldst, GPR:$hdst, GPR:$a, GPR:$b), |
Evan Cheng | 44bec52 | 2007-05-15 01:29:07 +0000 | [diff] [blame] | 949 | "umaal", " $ldst, $hdst, $a, $b", |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 950 | []>, Requires<[IsARM, HasV6]>; |
| 951 | |
| 952 | // Most significant word multiply |
| 953 | def SMMUL : AI_orr<"smmul", mulhs>, Requires<[IsARM, HasV6]>; |
| 954 | def SMMLA : AI_oorr<"smmla", add, mulhs>, Requires<[IsARM, HasV6]>; |
| 955 | |
| 956 | |
| 957 | def SMMLS : AI<(ops GPR:$dst, GPR:$a, GPR:$b, GPR:$c), |
Evan Cheng | 44bec52 | 2007-05-15 01:29:07 +0000 | [diff] [blame] | 958 | "smmls", " $dst, $a, $b, $c", |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 959 | [(set GPR:$dst, (sub GPR:$c, (mulhs GPR:$a, GPR:$b)))]>, |
| 960 | Requires<[IsARM, HasV6]>; |
| 961 | |
| 962 | multiclass AI_smul<string opc, PatFrag opnode> { |
Evan Cheng | 34b12d2 | 2007-01-19 20:27:35 +0000 | [diff] [blame] | 963 | def BB : AI<(ops GPR:$dst, GPR:$a, GPR:$b), |
Evan Cheng | 44bec52 | 2007-05-15 01:29:07 +0000 | [diff] [blame] | 964 | !strconcat(opc, "bb"), " $dst, $a, $b", |
Evan Cheng | 34b12d2 | 2007-01-19 20:27:35 +0000 | [diff] [blame] | 965 | [(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16), |
| 966 | (sext_inreg GPR:$b, i16)))]>, |
| 967 | Requires<[IsARM, HasV5TE]>; |
| 968 | def BT : AI<(ops GPR:$dst, GPR:$a, GPR:$b), |
Evan Cheng | 44bec52 | 2007-05-15 01:29:07 +0000 | [diff] [blame] | 969 | !strconcat(opc, "bt"), " $dst, $a, $b", |
Evan Cheng | 34b12d2 | 2007-01-19 20:27:35 +0000 | [diff] [blame] | 970 | [(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16), |
| 971 | (sra GPR:$b, 16)))]>, |
| 972 | Requires<[IsARM, HasV5TE]>; |
| 973 | def TB : AI<(ops GPR:$dst, GPR:$a, GPR:$b), |
Evan Cheng | 44bec52 | 2007-05-15 01:29:07 +0000 | [diff] [blame] | 974 | !strconcat(opc, "tb"), " $dst, $a, $b", |
Evan Cheng | 34b12d2 | 2007-01-19 20:27:35 +0000 | [diff] [blame] | 975 | [(set GPR:$dst, (opnode (sra GPR:$a, 16), |
| 976 | (sext_inreg GPR:$b, i16)))]>, |
| 977 | Requires<[IsARM, HasV5TE]>; |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 978 | def TT : AI<(ops GPR:$dst, GPR:$a, GPR:$b), |
Evan Cheng | 44bec52 | 2007-05-15 01:29:07 +0000 | [diff] [blame] | 979 | !strconcat(opc, "tt"), " $dst, $a, $b", |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 980 | [(set GPR:$dst, (opnode (sra GPR:$a, 16), |
| 981 | (sra GPR:$b, 16)))]>, |
| 982 | Requires<[IsARM, HasV5TE]>; |
Evan Cheng | 34b12d2 | 2007-01-19 20:27:35 +0000 | [diff] [blame] | 983 | def WB : AI<(ops GPR:$dst, GPR:$a, GPR:$b), |
Evan Cheng | 44bec52 | 2007-05-15 01:29:07 +0000 | [diff] [blame] | 984 | !strconcat(opc, "wb"), " $dst, $a, $b", |
Evan Cheng | 34b12d2 | 2007-01-19 20:27:35 +0000 | [diff] [blame] | 985 | [(set GPR:$dst, (sra (opnode GPR:$a, |
| 986 | (sext_inreg GPR:$b, i16)), 16))]>, |
| 987 | Requires<[IsARM, HasV5TE]>; |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 988 | def WT : AI<(ops GPR:$dst, GPR:$a, GPR:$b), |
Evan Cheng | 44bec52 | 2007-05-15 01:29:07 +0000 | [diff] [blame] | 989 | !strconcat(opc, "wt"), " $dst, $a, $b", |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 990 | [(set GPR:$dst, (sra (opnode GPR:$a, |
| 991 | (sra GPR:$b, 16)), 16))]>, |
| 992 | Requires<[IsARM, HasV5TE]>; |
Rafael Espindola | bec2e38 | 2006-10-16 16:33:29 +0000 | [diff] [blame] | 993 | } |
| 994 | |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 995 | multiclass AI_smla<string opc, PatFrag opnode> { |
Evan Cheng | 34b12d2 | 2007-01-19 20:27:35 +0000 | [diff] [blame] | 996 | def BB : AI<(ops GPR:$dst, GPR:$a, GPR:$b, GPR:$acc), |
Evan Cheng | 44bec52 | 2007-05-15 01:29:07 +0000 | [diff] [blame] | 997 | !strconcat(opc, "bb"), " $dst, $a, $b, $acc", |
Evan Cheng | 34b12d2 | 2007-01-19 20:27:35 +0000 | [diff] [blame] | 998 | [(set GPR:$dst, (add GPR:$acc, |
| 999 | (opnode (sext_inreg GPR:$a, i16), |
| 1000 | (sext_inreg GPR:$b, i16))))]>, |
| 1001 | Requires<[IsARM, HasV5TE]>; |
| 1002 | def BT : AI<(ops GPR:$dst, GPR:$a, GPR:$b, GPR:$acc), |
Evan Cheng | 44bec52 | 2007-05-15 01:29:07 +0000 | [diff] [blame] | 1003 | !strconcat(opc, "bt"), " $dst, $a, $b, $acc", |
Evan Cheng | 34b12d2 | 2007-01-19 20:27:35 +0000 | [diff] [blame] | 1004 | [(set GPR:$dst, (add GPR:$acc, (opnode (sext_inreg GPR:$a, i16), |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 1005 | (sra GPR:$b, 16))))]>, |
Evan Cheng | 34b12d2 | 2007-01-19 20:27:35 +0000 | [diff] [blame] | 1006 | Requires<[IsARM, HasV5TE]>; |
| 1007 | def TB : AI<(ops GPR:$dst, GPR:$a, GPR:$b, GPR:$acc), |
Evan Cheng | 44bec52 | 2007-05-15 01:29:07 +0000 | [diff] [blame] | 1008 | !strconcat(opc, "tb"), " $dst, $a, $b, $acc", |
Evan Cheng | 34b12d2 | 2007-01-19 20:27:35 +0000 | [diff] [blame] | 1009 | [(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, 16), |
| 1010 | (sext_inreg GPR:$b, i16))))]>, |
| 1011 | Requires<[IsARM, HasV5TE]>; |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 1012 | def TT : AI<(ops GPR:$dst, GPR:$a, GPR:$b, GPR:$acc), |
Evan Cheng | 44bec52 | 2007-05-15 01:29:07 +0000 | [diff] [blame] | 1013 | !strconcat(opc, "tt"), " $dst, $a, $b, $acc", |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 1014 | [(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, 16), |
| 1015 | (sra GPR:$b, 16))))]>, |
| 1016 | Requires<[IsARM, HasV5TE]>; |
| 1017 | |
Evan Cheng | 34b12d2 | 2007-01-19 20:27:35 +0000 | [diff] [blame] | 1018 | def WB : AI<(ops GPR:$dst, GPR:$a, GPR:$b, GPR:$acc), |
Evan Cheng | 44bec52 | 2007-05-15 01:29:07 +0000 | [diff] [blame] | 1019 | !strconcat(opc, "wb"), " $dst, $a, $b, $acc", |
Evan Cheng | 34b12d2 | 2007-01-19 20:27:35 +0000 | [diff] [blame] | 1020 | [(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a, |
| 1021 | (sext_inreg GPR:$b, i16)), 16)))]>, |
| 1022 | Requires<[IsARM, HasV5TE]>; |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 1023 | def WT : AI<(ops GPR:$dst, GPR:$a, GPR:$b, GPR:$acc), |
Evan Cheng | 44bec52 | 2007-05-15 01:29:07 +0000 | [diff] [blame] | 1024 | !strconcat(opc, "wt"), " $dst, $a, $b, $acc", |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 1025 | [(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a, |
| 1026 | (sra GPR:$b, 16)), 16)))]>, |
| 1027 | Requires<[IsARM, HasV5TE]>; |
Rafael Espindola | 70673a1 | 2006-10-18 16:20:57 +0000 | [diff] [blame] | 1028 | } |
Rafael Espindola | 5c2aa0a | 2006-09-08 12:47:03 +0000 | [diff] [blame] | 1029 | |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 1030 | defm SMUL : AI_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>; |
| 1031 | defm SMLA : AI_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>; |
Rafael Espindola | 2718519 | 2006-09-29 21:20:16 +0000 | [diff] [blame] | 1032 | |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 1033 | // TODO: Halfword multiple accumulate long: SMLAL<x><y> |
| 1034 | // TODO: Dual halfword multiple: SMUAD, SMUSD, SMLAD, SMLSD, SMLALD, SMLSLD |
Rafael Espindola | 42b62f3 | 2006-10-13 13:14:59 +0000 | [diff] [blame] | 1035 | |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 1036 | //===----------------------------------------------------------------------===// |
| 1037 | // Misc. Arithmetic Instructions. |
| 1038 | // |
Rafael Espindola | 0d9fe76 | 2006-10-10 16:33:47 +0000 | [diff] [blame] | 1039 | |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 1040 | def CLZ : AI<(ops GPR:$dst, GPR:$src), |
Evan Cheng | 44bec52 | 2007-05-15 01:29:07 +0000 | [diff] [blame] | 1041 | "clz", " $dst, $src", |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 1042 | [(set GPR:$dst, (ctlz GPR:$src))]>, Requires<[IsARM, HasV5T]>; |
Rafael Espindola | 199dd67 | 2006-10-17 13:13:23 +0000 | [diff] [blame] | 1043 | |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 1044 | def REV : AI<(ops GPR:$dst, GPR:$src), |
Evan Cheng | 44bec52 | 2007-05-15 01:29:07 +0000 | [diff] [blame] | 1045 | "rev", " $dst, $src", |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 1046 | [(set GPR:$dst, (bswap GPR:$src))]>, Requires<[IsARM, HasV6]>; |
Rafael Espindola | 199dd67 | 2006-10-17 13:13:23 +0000 | [diff] [blame] | 1047 | |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 1048 | def REV16 : AI<(ops GPR:$dst, GPR:$src), |
Evan Cheng | 44bec52 | 2007-05-15 01:29:07 +0000 | [diff] [blame] | 1049 | "rev16", " $dst, $src", |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 1050 | [(set GPR:$dst, |
| 1051 | (or (and (srl GPR:$src, 8), 0xFF), |
| 1052 | (or (and (shl GPR:$src, 8), 0xFF00), |
| 1053 | (or (and (srl GPR:$src, 8), 0xFF0000), |
| 1054 | (and (shl GPR:$src, 8), 0xFF000000)))))]>, |
| 1055 | Requires<[IsARM, HasV6]>; |
Rafael Espindola | 2718519 | 2006-09-29 21:20:16 +0000 | [diff] [blame] | 1056 | |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 1057 | def REVSH : AI<(ops GPR:$dst, GPR:$src), |
Evan Cheng | 44bec52 | 2007-05-15 01:29:07 +0000 | [diff] [blame] | 1058 | "revsh", " $dst, $src", |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 1059 | [(set GPR:$dst, |
| 1060 | (sext_inreg |
Chris Lattner | 120fba9 | 2007-04-17 22:39:58 +0000 | [diff] [blame] | 1061 | (or (srl (and GPR:$src, 0xFF00), 8), |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 1062 | (shl GPR:$src, 8)), i16))]>, |
| 1063 | Requires<[IsARM, HasV6]>; |
Rafael Espindola | 2718519 | 2006-09-29 21:20:16 +0000 | [diff] [blame] | 1064 | |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 1065 | def PKHBT : AI<(ops GPR:$dst, GPR:$src1, GPR:$src2, i32imm:$shamt), |
Evan Cheng | 44bec52 | 2007-05-15 01:29:07 +0000 | [diff] [blame] | 1066 | "pkhbt", " $dst, $src1, $src2, LSL $shamt", |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 1067 | [(set GPR:$dst, (or (and GPR:$src1, 0xFFFF), |
| 1068 | (and (shl GPR:$src2, (i32 imm:$shamt)), |
| 1069 | 0xFFFF0000)))]>, |
| 1070 | Requires<[IsARM, HasV6]>; |
Rafael Espindola | 2718519 | 2006-09-29 21:20:16 +0000 | [diff] [blame] | 1071 | |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 1072 | // Alternate cases for PKHBT where identities eliminate some nodes. |
| 1073 | def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF), (and GPR:$src2, 0xFFFF0000)), |
| 1074 | (PKHBT GPR:$src1, GPR:$src2, 0)>; |
| 1075 | def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF), (shl GPR:$src2, imm16_31:$shamt)), |
| 1076 | (PKHBT GPR:$src1, GPR:$src2, imm16_31:$shamt)>; |
Rafael Espindola | 9e071f0 | 2006-10-02 19:30:56 +0000 | [diff] [blame] | 1077 | |
Rafael Espindola | a284584 | 2006-10-05 16:48:49 +0000 | [diff] [blame] | 1078 | |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 1079 | def PKHTB : AI<(ops GPR:$dst, GPR:$src1, GPR:$src2, i32imm:$shamt), |
Evan Cheng | 44bec52 | 2007-05-15 01:29:07 +0000 | [diff] [blame] | 1080 | "pkhtb", " $dst, $src1, $src2, ASR $shamt", |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 1081 | [(set GPR:$dst, (or (and GPR:$src1, 0xFFFF0000), |
| 1082 | (and (sra GPR:$src2, imm16_31:$shamt), |
| 1083 | 0xFFFF)))]>, Requires<[IsARM, HasV6]>; |
Rafael Espindola | 9e071f0 | 2006-10-02 19:30:56 +0000 | [diff] [blame] | 1084 | |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 1085 | // Alternate cases for PKHTB where identities eliminate some nodes. Note that |
| 1086 | // a shift amount of 0 is *not legal* here, it is PKHBT instead. |
| 1087 | def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000), (srl GPR:$src2, 16)), |
| 1088 | (PKHTB GPR:$src1, GPR:$src2, 16)>; |
| 1089 | def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000), |
| 1090 | (and (srl GPR:$src2, imm1_15:$shamt), 0xFFFF)), |
| 1091 | (PKHTB GPR:$src1, GPR:$src2, imm1_15:$shamt)>; |
Rafael Espindola | b47e1d0 | 2006-10-10 18:55:14 +0000 | [diff] [blame] | 1092 | |
Rafael Espindola | d9ae778 | 2006-10-07 13:46:42 +0000 | [diff] [blame] | 1093 | |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 1094 | //===----------------------------------------------------------------------===// |
| 1095 | // Comparison Instructions... |
| 1096 | // |
Rafael Espindola | b47e1d0 | 2006-10-10 18:55:14 +0000 | [diff] [blame] | 1097 | |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 1098 | defm CMP : AI1_bin0_irs<"cmp", BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>; |
| 1099 | defm CMN : AI1_bin0_irs<"cmn", BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>; |
Rafael Espindola | e5bbd6d | 2006-10-07 14:24:52 +0000 | [diff] [blame] | 1100 | |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 1101 | def : ARMPat<(ARMcmp GPR:$src, so_imm_neg:$imm), |
| 1102 | (CMNri GPR:$src, so_imm_neg:$imm)>; |
Rafael Espindola | 493a7fc | 2006-10-10 20:38:57 +0000 | [diff] [blame] | 1103 | |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 1104 | // Note that TST/TEQ don't set all the same flags that CMP does! |
Lauro Ramos Venancio | 9996663 | 2007-04-02 01:30:03 +0000 | [diff] [blame] | 1105 | defm TST : AI1_bin0_irs<"tst", BinOpFrag<(ARMcmpNZ (and node:$LHS, node:$RHS), 0)>>; |
| 1106 | defm TEQ : AI1_bin0_irs<"teq", BinOpFrag<(ARMcmpNZ (xor node:$LHS, node:$RHS), 0)>>; |
| 1107 | |
| 1108 | defm CMPnz : AI1_bin0_irs<"cmp", BinOpFrag<(ARMcmpNZ node:$LHS, node:$RHS)>>; |
| 1109 | defm CMNnz : AI1_bin0_irs<"cmn", BinOpFrag<(ARMcmpNZ node:$LHS,(ineg node:$RHS))>>; |
| 1110 | |
| 1111 | def : ARMPat<(ARMcmpNZ GPR:$src, so_imm_neg:$imm), |
| 1112 | (CMNri GPR:$src, so_imm_neg:$imm)>; |
| 1113 | |
Rafael Espindola | e5bbd6d | 2006-10-07 14:24:52 +0000 | [diff] [blame] | 1114 | |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 1115 | // Conditional moves |
Evan Cheng | 44bec52 | 2007-05-15 01:29:07 +0000 | [diff] [blame] | 1116 | def MOVCCr : AXI<(ops GPR:$dst, GPR:$false, GPR:$true, ccop:$cc), |
| 1117 | "mov$cc $dst, $true", |
| 1118 | [(set GPR:$dst, (ARMcmov GPR:$false, GPR:$true, imm:$cc))]>, |
| 1119 | RegConstraint<"$false = $dst">; |
Rafael Espindola | 493a7fc | 2006-10-10 20:38:57 +0000 | [diff] [blame] | 1120 | |
Evan Cheng | 44bec52 | 2007-05-15 01:29:07 +0000 | [diff] [blame] | 1121 | def MOVCCs : AXI<(ops GPR:$dst, GPR:$false, so_reg:$true, ccop:$cc), |
| 1122 | "mov$cc $dst, $true", |
| 1123 | [(set GPR:$dst, (ARMcmov GPR:$false, so_reg:$true,imm:$cc))]>, |
| 1124 | RegConstraint<"$false = $dst">; |
Rafael Espindola | 2dc0f2b | 2006-10-09 17:50:29 +0000 | [diff] [blame] | 1125 | |
Evan Cheng | 44bec52 | 2007-05-15 01:29:07 +0000 | [diff] [blame] | 1126 | def MOVCCi : AXI<(ops GPR:$dst, GPR:$false, so_imm:$true, ccop:$cc), |
| 1127 | "mov$cc $dst, $true", |
| 1128 | [(set GPR:$dst, (ARMcmov GPR:$false, so_imm:$true,imm:$cc))]>, |
| 1129 | RegConstraint<"$false = $dst">; |
Rafael Espindola | d9ae778 | 2006-10-07 13:46:42 +0000 | [diff] [blame] | 1130 | |
Rafael Espindola | 4b20fbc | 2006-10-10 12:56:00 +0000 | [diff] [blame] | 1131 | |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 1132 | // LEApcrel - Load a pc-relative address into a register without offending the |
| 1133 | // assembler. |
Evan Cheng | 44bec52 | 2007-05-15 01:29:07 +0000 | [diff] [blame] | 1134 | def LEApcrel : AXI1<(ops GPR:$dst, i32imm:$label, pred:$p), |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 1135 | !strconcat(!strconcat(".set PCRELV${:uid}, ($label-(", |
| 1136 | "${:private}PCRELL${:uid}+8))\n"), |
| 1137 | !strconcat("${:private}PCRELL${:uid}:\n\t", |
Evan Cheng | 44bec52 | 2007-05-15 01:29:07 +0000 | [diff] [blame] | 1138 | "add$p $dst, pc, #PCRELV${:uid}")), |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 1139 | []>; |
Rafael Espindola | 667c349 | 2006-10-10 19:35:01 +0000 | [diff] [blame] | 1140 | |
Evan Cheng | 44bec52 | 2007-05-15 01:29:07 +0000 | [diff] [blame] | 1141 | def LEApcrelJT : AXI1<(ops GPR:$dst, i32imm:$label, i32imm:$id, pred:$p), |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 1142 | !strconcat(!strconcat(".set PCRELV${:uid}, (${label}_${id:no_hash}-(", |
| 1143 | "${:private}PCRELL${:uid}+8))\n"), |
| 1144 | !strconcat("${:private}PCRELL${:uid}:\n\t", |
Evan Cheng | 44bec52 | 2007-05-15 01:29:07 +0000 | [diff] [blame] | 1145 | "add$p $dst, pc, #PCRELV${:uid}")), |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 1146 | []>; |
Lauro Ramos Venancio | 64f4fa5 | 2007-04-27 13:54:47 +0000 | [diff] [blame] | 1147 | //===----------------------------------------------------------------------===// |
| 1148 | // TLS Instructions |
| 1149 | // |
| 1150 | |
| 1151 | // __aeabi_read_tp preserves the registers r1-r3. |
| 1152 | let isCall = 1, |
| 1153 | Defs = [R0, R12, LR] in { |
Evan Cheng | dcc50a4 | 2007-05-18 01:53:54 +0000 | [diff] [blame] | 1154 | def TPsoft : AXI<(ops), |
| 1155 | "bl __aeabi_read_tp", |
Lauro Ramos Venancio | 64f4fa5 | 2007-04-27 13:54:47 +0000 | [diff] [blame] | 1156 | [(set R0, ARMthread_pointer)]>; |
| 1157 | } |
Rafael Espindola | c01c87c | 2006-10-17 20:33:13 +0000 | [diff] [blame] | 1158 | |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 1159 | //===----------------------------------------------------------------------===// |
| 1160 | // Non-Instruction Patterns |
| 1161 | // |
Rafael Espindola | 5aca927 | 2006-10-07 14:03:39 +0000 | [diff] [blame] | 1162 | |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 1163 | // ConstantPool, GlobalAddress, and JumpTable |
| 1164 | def : ARMPat<(ARMWrapper tglobaladdr :$dst), (LEApcrel tglobaladdr :$dst)>; |
| 1165 | def : ARMPat<(ARMWrapper tconstpool :$dst), (LEApcrel tconstpool :$dst)>; |
| 1166 | def : ARMPat<(ARMWrapperJT tjumptable:$dst, imm:$id), |
Evan Cheng | c70d184 | 2007-03-20 08:11:30 +0000 | [diff] [blame] | 1167 | (LEApcrelJT tjumptable:$dst, imm:$id)>; |
Rafael Espindola | 5aca927 | 2006-10-07 14:03:39 +0000 | [diff] [blame] | 1168 | |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 1169 | // Large immediate handling. |
Rafael Espindola | 0505be0 | 2006-10-16 21:10:32 +0000 | [diff] [blame] | 1170 | |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 1171 | // Two piece so_imms. |
Evan Cheng | c70d184 | 2007-03-20 08:11:30 +0000 | [diff] [blame] | 1172 | let isReMaterializable = 1 in |
| 1173 | def MOVi2pieces : AI1x2<(ops GPR:$dst, so_imm2part:$src), |
Evan Cheng | 44bec52 | 2007-05-15 01:29:07 +0000 | [diff] [blame] | 1174 | "mov", " $dst, $src", |
Evan Cheng | c70d184 | 2007-03-20 08:11:30 +0000 | [diff] [blame] | 1175 | [(set GPR:$dst, so_imm2part:$src)]>; |
Rafael Espindola | f621abc | 2006-10-17 13:36:07 +0000 | [diff] [blame] | 1176 | |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 1177 | def : ARMPat<(or GPR:$LHS, so_imm2part:$RHS), |
| 1178 | (ORRri (ORRri GPR:$LHS, (so_imm2part_1 imm:$RHS)), |
| 1179 | (so_imm2part_2 imm:$RHS))>; |
| 1180 | def : ARMPat<(xor GPR:$LHS, so_imm2part:$RHS), |
| 1181 | (EORri (EORri GPR:$LHS, (so_imm2part_1 imm:$RHS)), |
| 1182 | (so_imm2part_2 imm:$RHS))>; |
Rafael Espindola | f621abc | 2006-10-17 13:36:07 +0000 | [diff] [blame] | 1183 | |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 1184 | // TODO: add,sub,and, 3-instr forms? |
Rafael Espindola | 0505be0 | 2006-10-16 21:10:32 +0000 | [diff] [blame] | 1185 | |
Rafael Espindola | 2435786 | 2006-10-19 17:05:03 +0000 | [diff] [blame] | 1186 | |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 1187 | // Direct calls |
| 1188 | def : ARMPat<(ARMcall texternalsym:$func), (BL texternalsym:$func)>; |
Rafael Espindola | 9dca7ad | 2006-11-01 14:13:27 +0000 | [diff] [blame] | 1189 | |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 1190 | // zextload i1 -> zextload i8 |
| 1191 | def : ARMPat<(zextloadi1 addrmode2:$addr), (LDRB addrmode2:$addr)>; |
Lauro Ramos Venancio | a8f9f4a | 2006-12-26 19:30:42 +0000 | [diff] [blame] | 1192 | |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 1193 | // extload -> zextload |
| 1194 | def : ARMPat<(extloadi1 addrmode2:$addr), (LDRB addrmode2:$addr)>; |
| 1195 | def : ARMPat<(extloadi8 addrmode2:$addr), (LDRB addrmode2:$addr)>; |
| 1196 | def : ARMPat<(extloadi16 addrmode3:$addr), (LDRH addrmode3:$addr)>; |
Rafael Espindola | 9dca7ad | 2006-11-01 14:13:27 +0000 | [diff] [blame] | 1197 | |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 1198 | // truncstore i1 -> truncstore i8 |
Dale Johannesen | 25c1f9e | 2007-04-27 22:17:18 +0000 | [diff] [blame] | 1199 | def : ARMPat<(truncstorei1 GPR:$src, addrmode2:$dst), |
Dale Johannesen | caa8055 | 2007-04-28 00:36:37 +0000 | [diff] [blame] | 1200 | (STRB GPR:$src, addrmode2:$dst)>; |
Dale Johannesen | 25c1f9e | 2007-04-27 22:17:18 +0000 | [diff] [blame] | 1201 | def : ARMPat<(pre_truncsti1 GPR:$src, GPR:$base, am2offset:$offset), |
Dale Johannesen | caa8055 | 2007-04-28 00:36:37 +0000 | [diff] [blame] | 1202 | (STRB_PRE GPR:$src, GPR:$base, am2offset:$offset)>; |
Dale Johannesen | 25c1f9e | 2007-04-27 22:17:18 +0000 | [diff] [blame] | 1203 | def : ARMPat<(post_truncsti1 GPR:$src, GPR:$base, am2offset:$offset), |
Dale Johannesen | caa8055 | 2007-04-28 00:36:37 +0000 | [diff] [blame] | 1204 | (STRB_POST GPR:$src, GPR:$base, am2offset:$offset)>; |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 1205 | |
Evan Cheng | 34b12d2 | 2007-01-19 20:27:35 +0000 | [diff] [blame] | 1206 | // smul* and smla* |
| 1207 | def : ARMV5TEPat<(mul (sra (shl GPR:$a, 16), 16), (sra (shl GPR:$b, 16), 16)), |
| 1208 | (SMULBB GPR:$a, GPR:$b)>; |
| 1209 | def : ARMV5TEPat<(mul sext_16_node:$a, sext_16_node:$b), |
| 1210 | (SMULBB GPR:$a, GPR:$b)>; |
| 1211 | def : ARMV5TEPat<(mul (sra (shl GPR:$a, 16), 16), (sra GPR:$b, 16)), |
| 1212 | (SMULBT GPR:$a, GPR:$b)>; |
| 1213 | def : ARMV5TEPat<(mul sext_16_node:$a, (sra GPR:$b, 16)), |
| 1214 | (SMULBT GPR:$a, GPR:$b)>; |
| 1215 | def : ARMV5TEPat<(mul (sra GPR:$a, 16), (sra (shl GPR:$b, 16), 16)), |
| 1216 | (SMULTB GPR:$a, GPR:$b)>; |
| 1217 | def : ARMV5TEPat<(mul (sra GPR:$a, 16), sext_16_node:$b), |
| 1218 | (SMULTB GPR:$a, GPR:$b)>; |
| 1219 | def : ARMV5TEPat<(sra (mul GPR:$a, (sra (shl GPR:$b, 16), 16)), 16), |
| 1220 | (SMULWB GPR:$a, GPR:$b)>; |
| 1221 | def : ARMV5TEPat<(sra (mul GPR:$a, sext_16_node:$b), 16), |
| 1222 | (SMULWB GPR:$a, GPR:$b)>; |
| 1223 | |
| 1224 | def : ARMV5TEPat<(add GPR:$acc, |
| 1225 | (mul (sra (shl GPR:$a, 16), 16), |
| 1226 | (sra (shl GPR:$b, 16), 16))), |
| 1227 | (SMLABB GPR:$a, GPR:$b, GPR:$acc)>; |
| 1228 | def : ARMV5TEPat<(add GPR:$acc, |
| 1229 | (mul sext_16_node:$a, sext_16_node:$b)), |
| 1230 | (SMLABB GPR:$a, GPR:$b, GPR:$acc)>; |
| 1231 | def : ARMV5TEPat<(add GPR:$acc, |
| 1232 | (mul (sra (shl GPR:$a, 16), 16), (sra GPR:$b, 16))), |
| 1233 | (SMLABT GPR:$a, GPR:$b, GPR:$acc)>; |
| 1234 | def : ARMV5TEPat<(add GPR:$acc, |
| 1235 | (mul sext_16_node:$a, (sra GPR:$b, 16))), |
| 1236 | (SMLABT GPR:$a, GPR:$b, GPR:$acc)>; |
| 1237 | def : ARMV5TEPat<(add GPR:$acc, |
| 1238 | (mul (sra GPR:$a, 16), (sra (shl GPR:$b, 16), 16))), |
| 1239 | (SMLATB GPR:$a, GPR:$b, GPR:$acc)>; |
| 1240 | def : ARMV5TEPat<(add GPR:$acc, |
| 1241 | (mul (sra GPR:$a, 16), sext_16_node:$b)), |
| 1242 | (SMLATB GPR:$a, GPR:$b, GPR:$acc)>; |
| 1243 | def : ARMV5TEPat<(add GPR:$acc, |
| 1244 | (sra (mul GPR:$a, (sra (shl GPR:$b, 16), 16)), 16)), |
| 1245 | (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>; |
| 1246 | def : ARMV5TEPat<(add GPR:$acc, |
| 1247 | (sra (mul GPR:$a, sext_16_node:$b), 16)), |
| 1248 | (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>; |
| 1249 | |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 1250 | //===----------------------------------------------------------------------===// |
| 1251 | // Thumb Support |
| 1252 | // |
| 1253 | |
| 1254 | include "ARMInstrThumb.td" |
| 1255 | |
| 1256 | //===----------------------------------------------------------------------===// |
| 1257 | // Floating Point Support |
| 1258 | // |
| 1259 | |
| 1260 | include "ARMInstrVFP.td" |