blob: 723383e04b8e66855d60ece28d35cd4cc7a0165e [file] [log] [blame]
Chad Rosier3901c3e2012-02-06 23:50:07 +00001; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM
2; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB
3
4; Test add with non-legal types
5
6define void @add_i1(i1 %a, i1 %b) nounwind ssp {
7entry:
8; ARM: add_i1
9; THUMB: add_i1
10 %a.addr = alloca i1, align 4
11 %0 = add i1 %a, %b
12; ARM: add r0, r0, r1
13; THUMB: add r0, r1
14 store i1 %0, i1* %a.addr, align 4
15 ret void
16}
17
18define void @add_i8(i8 %a, i8 %b) nounwind ssp {
19entry:
20; ARM: add_i8
21; THUMB: add_i8
22 %a.addr = alloca i8, align 4
23 %0 = add i8 %a, %b
24; ARM: add r0, r0, r1
25; THUMB: add r0, r1
26 store i8 %0, i8* %a.addr, align 4
27 ret void
28}
29
30define void @add_i16(i16 %a, i16 %b) nounwind ssp {
31entry:
32; ARM: add_i16
33; THUMB: add_i16
34 %a.addr = alloca i16, align 4
35 %0 = add i16 %a, %b
36; ARM: add r0, r0, r1
37; THUMB: add r0, r1
38 store i16 %0, i16* %a.addr, align 4
39 ret void
40}
Chad Rosier6fde8752012-02-08 02:29:21 +000041
Chad Rosier176346d2012-02-08 02:30:12 +000042; Test or with non-legal types
43
Chad Rosier6fde8752012-02-08 02:29:21 +000044define void @or_i1(i1 %a, i1 %b) nounwind ssp {
45entry:
46; ARM: or_i1
47; THUMB: or_i1
48 %a.addr = alloca i1, align 4
49 %0 = or i1 %a, %b
50; ARM: orr r0, r0, r1
51; THUMB: orrs r0, r1
52 store i1 %0, i1* %a.addr, align 4
53 ret void
54}
55
56define void @or_i8(i8 %a, i8 %b) nounwind ssp {
57entry:
58; ARM: or_i8
59; THUMB: or_i8
60 %a.addr = alloca i8, align 4
61 %0 = or i8 %a, %b
62; ARM: orr r0, r0, r1
63; THUMB: orrs r0, r1
64 store i8 %0, i8* %a.addr, align 4
65 ret void
66}
67
68define void @or_i16(i16 %a, i16 %b) nounwind ssp {
69entry:
70; ARM: or_i16
71; THUMB: or_i16
72 %a.addr = alloca i16, align 4
73 %0 = or i16 %a, %b
74; ARM: orr r0, r0, r1
75; THUMB: orrs r0, r1
76 store i16 %0, i16* %a.addr, align 4
77 ret void
78}
Chad Rosier743e1992012-02-08 02:45:44 +000079
80; Test sub with non-legal types
81
82define void @sub_i1(i1 %a, i1 %b) nounwind ssp {
83entry:
84; ARM: sub_i1
85; THUMB: sub_i1
86 %a.addr = alloca i1, align 4
87 %0 = sub i1 %a, %b
88; ARM: sub r0, r0, r1
89; THUMB: subs r0, r0, r1
90 store i1 %0, i1* %a.addr, align 4
91 ret void
92}
93
94define void @sub_i8(i8 %a, i8 %b) nounwind ssp {
95entry:
96; ARM: sub_i8
97; THUMB: sub_i8
98 %a.addr = alloca i8, align 4
99 %0 = sub i8 %a, %b
100; ARM: sub r0, r0, r1
101; THUMB: subs r0, r0, r1
102 store i8 %0, i8* %a.addr, align 4
103 ret void
104}
105
106define void @sub_i16(i16 %a, i16 %b) nounwind ssp {
107entry:
108; ARM: sub_i16
109; THUMB: sub_i16
110 %a.addr = alloca i16, align 4
111 %0 = sub i16 %a, %b
112; ARM: sub r0, r0, r1
113; THUMB: subs r0, r0, r1
114 store i16 %0, i16* %a.addr, align 4
115 ret void
116}