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Chris Lattner7c90f732006-02-05 05:50:24 +00001//===- SparcInstrInfo.h - Sparc Instruction Information ---------*- C++ -*-===//
Misha Brukmanb5f662f2005-04-21 23:30:14 +00002//
Brian Gaekee785e532004-02-25 19:28:19 +00003// The LLVM Compiler Infrastructure
4//
Chris Lattner4ee451d2007-12-29 20:36:04 +00005// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
Misha Brukmanb5f662f2005-04-21 23:30:14 +00007//
Brian Gaekee785e532004-02-25 19:28:19 +00008//===----------------------------------------------------------------------===//
9//
Chris Lattner7c90f732006-02-05 05:50:24 +000010// This file contains the Sparc implementation of the TargetInstrInfo class.
Brian Gaekee785e532004-02-25 19:28:19 +000011//
12//===----------------------------------------------------------------------===//
13
Chris Lattner7c90f732006-02-05 05:50:24 +000014#ifndef SPARCINSTRUCTIONINFO_H
15#define SPARCINSTRUCTIONINFO_H
Brian Gaekee785e532004-02-25 19:28:19 +000016
17#include "llvm/Target/TargetInstrInfo.h"
Chris Lattner7c90f732006-02-05 05:50:24 +000018#include "SparcRegisterInfo.h"
Brian Gaekee785e532004-02-25 19:28:19 +000019
20namespace llvm {
21
Chris Lattner7c90f732006-02-05 05:50:24 +000022/// SPII - This namespace holds all of the target specific flags that
Brian Gaeke7d7ac632004-07-16 10:31:59 +000023/// instruction info tracks.
24///
Chris Lattner7c90f732006-02-05 05:50:24 +000025namespace SPII {
Brian Gaeke7d7ac632004-07-16 10:31:59 +000026 enum {
27 Pseudo = (1<<0),
28 Load = (1<<1),
29 Store = (1<<2),
30 DelaySlot = (1<<3)
31 };
Chris Lattnerd74ea2b2006-05-24 17:04:05 +000032}
Brian Gaeke7d7ac632004-07-16 10:31:59 +000033
Chris Lattner64105522008-01-01 01:03:04 +000034class SparcInstrInfo : public TargetInstrInfoImpl {
Chris Lattner7c90f732006-02-05 05:50:24 +000035 const SparcRegisterInfo RI;
Owen Andersond10fd972007-12-31 06:32:00 +000036 const SparcSubtarget& Subtarget;
Brian Gaekee785e532004-02-25 19:28:19 +000037public:
Chris Lattner7c90f732006-02-05 05:50:24 +000038 SparcInstrInfo(SparcSubtarget &ST);
Brian Gaekee785e532004-02-25 19:28:19 +000039
40 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
41 /// such, whenever a client has an instance of instruction info, it should
42 /// always be able to get register info as well (through this method).
43 ///
44 virtual const MRegisterInfo &getRegisterInfo() const { return RI; }
Chris Lattner1d6dc972004-07-25 06:19:04 +000045
46 /// Return true if the instruction is a register to register move and
47 /// leave the source and dest operands in the passed parameters.
48 ///
49 virtual bool isMoveInstr(const MachineInstr &MI,
50 unsigned &SrcReg, unsigned &DstReg) const;
Chris Lattner5ccc7222006-02-03 06:44:54 +000051
52 /// isLoadFromStackSlot - If the specified machine instruction is a direct
53 /// load from a stack slot, return the virtual or physical register number of
54 /// the destination along with the FrameIndex of the loaded stack slot. If
55 /// not, return 0. This predicate must return 0 if the instruction has
56 /// any side effects other than loading from the stack slot.
57 virtual unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const;
58
59 /// isStoreToStackSlot - If the specified machine instruction is a direct
60 /// store to a stack slot, return the virtual or physical register number of
61 /// the source reg along with the FrameIndex of the loaded stack slot. If
62 /// not, return 0. This predicate must return 0 if the instruction has
63 /// any side effects other than storing to the stack slot.
64 virtual unsigned isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const;
Chris Lattnere87146a2006-10-24 16:39:19 +000065
66
Evan Cheng6ae36262007-05-18 00:18:17 +000067 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
68 MachineBasicBlock *FBB,
69 const std::vector<MachineOperand> &Cond) const;
Owen Andersond10fd972007-12-31 06:32:00 +000070
71 virtual void copyRegToReg(MachineBasicBlock &MBB,
72 MachineBasicBlock::iterator I,
73 unsigned DestReg, unsigned SrcReg,
74 const TargetRegisterClass *DestRC,
75 const TargetRegisterClass *SrcRC) const;
Brian Gaekee785e532004-02-25 19:28:19 +000076};
77
78}
79
80#endif