David Goodwin | 334c264 | 2009-07-08 16:09:28 +0000 | [diff] [blame] | 1 | //===- ARMBaseInstrInfo.h - ARM Base Instruction Information -------------*- C++ -*-===// |
| 2 | // |
| 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
| 5 | // This file is distributed under the University of Illinois Open Source |
| 6 | // License. See LICENSE.TXT for details. |
| 7 | // |
| 8 | //===----------------------------------------------------------------------===// |
| 9 | // |
| 10 | // This file contains the Base ARM implementation of the TargetInstrInfo class. |
| 11 | // |
| 12 | //===----------------------------------------------------------------------===// |
| 13 | |
| 14 | #ifndef ARMBASEINSTRUCTIONINFO_H |
| 15 | #define ARMBASEINSTRUCTIONINFO_H |
| 16 | |
David Goodwin | 334c264 | 2009-07-08 16:09:28 +0000 | [diff] [blame] | 17 | #include "ARM.h" |
Anton Korobeynikov | b8e9ac8 | 2009-07-16 23:26:06 +0000 | [diff] [blame] | 18 | #include "ARMRegisterInfo.h" |
| 19 | #include "llvm/CodeGen/MachineInstrBuilder.h" |
| 20 | #include "llvm/Target/TargetInstrInfo.h" |
David Goodwin | 334c264 | 2009-07-08 16:09:28 +0000 | [diff] [blame] | 21 | |
| 22 | namespace llvm { |
David Goodwin | 334c264 | 2009-07-08 16:09:28 +0000 | [diff] [blame] | 23 | |
| 24 | /// ARMII - This namespace holds all of the target specific flags that |
| 25 | /// instruction info tracks. |
| 26 | /// |
| 27 | namespace ARMII { |
| 28 | enum { |
| 29 | //===------------------------------------------------------------------===// |
| 30 | // Instruction Flags. |
| 31 | |
| 32 | //===------------------------------------------------------------------===// |
| 33 | // This four-bit field describes the addressing mode used. |
| 34 | |
| 35 | AddrModeMask = 0xf, |
| 36 | AddrModeNone = 0, |
| 37 | AddrMode1 = 1, |
| 38 | AddrMode2 = 2, |
| 39 | AddrMode3 = 3, |
| 40 | AddrMode4 = 4, |
| 41 | AddrMode5 = 5, |
| 42 | AddrMode6 = 6, |
| 43 | AddrModeT1_1 = 7, |
| 44 | AddrModeT1_2 = 8, |
| 45 | AddrModeT1_4 = 9, |
| 46 | AddrModeT1_s = 10, // i8 * 4 for pc and sp relative data |
| 47 | AddrModeT2_i12 = 11, |
| 48 | AddrModeT2_i8 = 12, |
| 49 | AddrModeT2_so = 13, |
| 50 | AddrModeT2_pc = 14, // +/- i12 for pc relative data |
| 51 | AddrModeT2_i8s4 = 15, // i8 * 4 |
| 52 | |
| 53 | // Size* - Flags to keep track of the size of an instruction. |
| 54 | SizeShift = 4, |
| 55 | SizeMask = 7 << SizeShift, |
| 56 | SizeSpecial = 1, // 0 byte pseudo or special case. |
| 57 | Size8Bytes = 2, |
| 58 | Size4Bytes = 3, |
| 59 | Size2Bytes = 4, |
| 60 | |
| 61 | // IndexMode - Unindex, pre-indexed, or post-indexed. Only valid for load |
| 62 | // and store ops |
| 63 | IndexModeShift = 7, |
| 64 | IndexModeMask = 3 << IndexModeShift, |
| 65 | IndexModePre = 1, |
| 66 | IndexModePost = 2, |
| 67 | |
| 68 | //===------------------------------------------------------------------===// |
| 69 | // Instruction encoding formats. |
| 70 | // |
| 71 | FormShift = 9, |
| 72 | FormMask = 0x3f << FormShift, |
| 73 | |
| 74 | // Pseudo instructions |
| 75 | Pseudo = 0 << FormShift, |
| 76 | |
| 77 | // Multiply instructions |
| 78 | MulFrm = 1 << FormShift, |
| 79 | |
| 80 | // Branch instructions |
| 81 | BrFrm = 2 << FormShift, |
| 82 | BrMiscFrm = 3 << FormShift, |
| 83 | |
| 84 | // Data Processing instructions |
| 85 | DPFrm = 4 << FormShift, |
| 86 | DPSoRegFrm = 5 << FormShift, |
| 87 | |
| 88 | // Load and Store |
| 89 | LdFrm = 6 << FormShift, |
| 90 | StFrm = 7 << FormShift, |
| 91 | LdMiscFrm = 8 << FormShift, |
| 92 | StMiscFrm = 9 << FormShift, |
| 93 | LdStMulFrm = 10 << FormShift, |
| 94 | |
| 95 | // Miscellaneous arithmetic instructions |
| 96 | ArithMiscFrm = 11 << FormShift, |
| 97 | |
| 98 | // Extend instructions |
| 99 | ExtFrm = 12 << FormShift, |
| 100 | |
| 101 | // VFP formats |
| 102 | VFPUnaryFrm = 13 << FormShift, |
| 103 | VFPBinaryFrm = 14 << FormShift, |
| 104 | VFPConv1Frm = 15 << FormShift, |
| 105 | VFPConv2Frm = 16 << FormShift, |
| 106 | VFPConv3Frm = 17 << FormShift, |
| 107 | VFPConv4Frm = 18 << FormShift, |
| 108 | VFPConv5Frm = 19 << FormShift, |
| 109 | VFPLdStFrm = 20 << FormShift, |
| 110 | VFPLdStMulFrm = 21 << FormShift, |
| 111 | VFPMiscFrm = 22 << FormShift, |
| 112 | |
| 113 | // Thumb format |
| 114 | ThumbFrm = 23 << FormShift, |
| 115 | |
| 116 | // NEON format |
| 117 | NEONFrm = 24 << FormShift, |
| 118 | NEONGetLnFrm = 25 << FormShift, |
| 119 | NEONSetLnFrm = 26 << FormShift, |
| 120 | NEONDupFrm = 27 << FormShift, |
| 121 | |
| 122 | //===------------------------------------------------------------------===// |
| 123 | // Misc flags. |
| 124 | |
| 125 | // UnaryDP - Indicates this is a unary data processing instruction, i.e. |
| 126 | // it doesn't have a Rn operand. |
| 127 | UnaryDP = 1 << 15, |
| 128 | |
| 129 | // Xform16Bit - Indicates this Thumb2 instruction may be transformed into |
| 130 | // a 16-bit Thumb instruction if certain conditions are met. |
| 131 | Xform16Bit = 1 << 16, |
| 132 | |
| 133 | //===------------------------------------------------------------------===// |
| 134 | // Field shifts - such shifts are used to set field while generating |
| 135 | // machine instructions. |
| 136 | M_BitShift = 5, |
| 137 | ShiftImmShift = 5, |
| 138 | ShiftShift = 7, |
| 139 | N_BitShift = 7, |
| 140 | ImmHiShift = 8, |
| 141 | SoRotImmShift = 8, |
| 142 | RegRsShift = 8, |
| 143 | ExtRotImmShift = 10, |
| 144 | RegRdLoShift = 12, |
| 145 | RegRdShift = 12, |
| 146 | RegRdHiShift = 16, |
| 147 | RegRnShift = 16, |
| 148 | S_BitShift = 20, |
| 149 | W_BitShift = 21, |
| 150 | AM3_I_BitShift = 22, |
| 151 | D_BitShift = 22, |
| 152 | U_BitShift = 23, |
| 153 | P_BitShift = 24, |
| 154 | I_BitShift = 25, |
| 155 | CondShift = 28 |
| 156 | }; |
Evan Cheng | b46aaa3 | 2009-07-19 19:16:46 +0000 | [diff] [blame] | 157 | } |
| 158 | |
David Goodwin | 334c264 | 2009-07-08 16:09:28 +0000 | [diff] [blame] | 159 | class ARMBaseInstrInfo : public TargetInstrInfoImpl { |
| 160 | protected: |
| 161 | // Can be only subclassed. |
Chris Lattner | d90183d | 2009-08-02 05:20:37 +0000 | [diff] [blame] | 162 | explicit ARMBaseInstrInfo(); |
David Goodwin | 334c264 | 2009-07-08 16:09:28 +0000 | [diff] [blame] | 163 | public: |
| 164 | // Return the non-pre/post incrementing version of 'Opc'. Return 0 |
| 165 | // if there is not such an opcode. |
| 166 | virtual unsigned getUnindexedOpcode(unsigned Opc) const =0; |
| 167 | |
David Goodwin | 334c264 | 2009-07-08 16:09:28 +0000 | [diff] [blame] | 168 | // Return true if the block does not fall through. |
| 169 | virtual bool BlockHasNoFallThrough(const MachineBasicBlock &MBB) const =0; |
| 170 | |
| 171 | virtual MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI, |
| 172 | MachineBasicBlock::iterator &MBBI, |
| 173 | LiveVariables *LV) const; |
| 174 | |
| 175 | virtual const ARMBaseRegisterInfo &getRegisterInfo() const =0; |
| 176 | |
| 177 | // Branch analysis. |
| 178 | virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, |
| 179 | MachineBasicBlock *&FBB, |
| 180 | SmallVectorImpl<MachineOperand> &Cond, |
| 181 | bool AllowModify) const; |
| 182 | virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const; |
| 183 | virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, |
| 184 | MachineBasicBlock *FBB, |
| 185 | const SmallVectorImpl<MachineOperand> &Cond) const; |
| 186 | |
| 187 | virtual |
| 188 | bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const; |
| 189 | |
| 190 | // Predication support. |
Evan Cheng | ab33150 | 2009-07-10 01:38:27 +0000 | [diff] [blame] | 191 | bool isPredicated(const MachineInstr *MI) const { |
| 192 | int PIdx = MI->findFirstPredOperandIdx(); |
| 193 | return PIdx != -1 && MI->getOperand(PIdx).getImm() != ARMCC::AL; |
| 194 | } |
David Goodwin | 334c264 | 2009-07-08 16:09:28 +0000 | [diff] [blame] | 195 | |
| 196 | ARMCC::CondCodes getPredicate(const MachineInstr *MI) const { |
| 197 | int PIdx = MI->findFirstPredOperandIdx(); |
| 198 | return PIdx != -1 ? (ARMCC::CondCodes)MI->getOperand(PIdx).getImm() |
| 199 | : ARMCC::AL; |
| 200 | } |
| 201 | |
| 202 | virtual |
| 203 | bool PredicateInstruction(MachineInstr *MI, |
| 204 | const SmallVectorImpl<MachineOperand> &Pred) const; |
| 205 | |
| 206 | virtual |
| 207 | bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1, |
| 208 | const SmallVectorImpl<MachineOperand> &Pred2) const; |
| 209 | |
| 210 | virtual bool DefinesPredicate(MachineInstr *MI, |
| 211 | std::vector<MachineOperand> &Pred) const; |
| 212 | |
| 213 | /// GetInstSize - Returns the size of the specified MachineInstr. |
| 214 | /// |
| 215 | virtual unsigned GetInstSizeInBytes(const MachineInstr* MI) const; |
| 216 | |
| 217 | /// Return true if the instruction is a register to register move and return |
| 218 | /// the source and dest operands and their sub-register indices by reference. |
| 219 | virtual bool isMoveInstr(const MachineInstr &MI, |
| 220 | unsigned &SrcReg, unsigned &DstReg, |
| 221 | unsigned &SrcSubIdx, unsigned &DstSubIdx) const; |
| 222 | |
| 223 | virtual unsigned isLoadFromStackSlot(const MachineInstr *MI, |
| 224 | int &FrameIndex) const; |
| 225 | virtual unsigned isStoreToStackSlot(const MachineInstr *MI, |
| 226 | int &FrameIndex) const; |
| 227 | |
| 228 | virtual bool copyRegToReg(MachineBasicBlock &MBB, |
| 229 | MachineBasicBlock::iterator I, |
| 230 | unsigned DestReg, unsigned SrcReg, |
| 231 | const TargetRegisterClass *DestRC, |
| 232 | const TargetRegisterClass *SrcRC) const; |
Evan Cheng | 5732ca0 | 2009-07-27 03:14:20 +0000 | [diff] [blame] | 233 | |
David Goodwin | 334c264 | 2009-07-08 16:09:28 +0000 | [diff] [blame] | 234 | virtual void storeRegToStackSlot(MachineBasicBlock &MBB, |
| 235 | MachineBasicBlock::iterator MBBI, |
| 236 | unsigned SrcReg, bool isKill, int FrameIndex, |
| 237 | const TargetRegisterClass *RC) const; |
| 238 | |
David Goodwin | 334c264 | 2009-07-08 16:09:28 +0000 | [diff] [blame] | 239 | virtual void loadRegFromStackSlot(MachineBasicBlock &MBB, |
| 240 | MachineBasicBlock::iterator MBBI, |
| 241 | unsigned DestReg, int FrameIndex, |
| 242 | const TargetRegisterClass *RC) const; |
| 243 | |
David Goodwin | 334c264 | 2009-07-08 16:09:28 +0000 | [diff] [blame] | 244 | virtual bool canFoldMemoryOperand(const MachineInstr *MI, |
| 245 | const SmallVectorImpl<unsigned> &Ops) const; |
Jim Grosbach | 764ab52 | 2009-08-11 15:33:49 +0000 | [diff] [blame] | 246 | |
David Goodwin | 334c264 | 2009-07-08 16:09:28 +0000 | [diff] [blame] | 247 | virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF, |
| 248 | MachineInstr* MI, |
| 249 | const SmallVectorImpl<unsigned> &Ops, |
| 250 | int FrameIndex) const; |
| 251 | |
| 252 | virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF, |
| 253 | MachineInstr* MI, |
| 254 | const SmallVectorImpl<unsigned> &Ops, |
| 255 | MachineInstr* LoadMI) const; |
Evan Cheng | 5ca53a7 | 2009-07-27 18:20:05 +0000 | [diff] [blame] | 256 | |
David Goodwin | 334c264 | 2009-07-08 16:09:28 +0000 | [diff] [blame] | 257 | }; |
Evan Cheng | 6495f63 | 2009-07-28 05:48:47 +0000 | [diff] [blame] | 258 | |
| 259 | static inline |
| 260 | const MachineInstrBuilder &AddDefaultPred(const MachineInstrBuilder &MIB) { |
| 261 | return MIB.addImm((int64_t)ARMCC::AL).addReg(0); |
David Goodwin | 334c264 | 2009-07-08 16:09:28 +0000 | [diff] [blame] | 262 | } |
| 263 | |
Evan Cheng | 6495f63 | 2009-07-28 05:48:47 +0000 | [diff] [blame] | 264 | static inline |
| 265 | const MachineInstrBuilder &AddDefaultCC(const MachineInstrBuilder &MIB) { |
| 266 | return MIB.addReg(0); |
| 267 | } |
| 268 | |
| 269 | static inline |
Evan Cheng | e8af1f9 | 2009-08-10 02:37:24 +0000 | [diff] [blame] | 270 | const MachineInstrBuilder &AddDefaultT1CC(const MachineInstrBuilder &MIB, |
| 271 | bool isDead = false) { |
| 272 | return MIB.addReg(ARM::CPSR, getDefRegState(true) | getDeadRegState(isDead)); |
Evan Cheng | 6495f63 | 2009-07-28 05:48:47 +0000 | [diff] [blame] | 273 | } |
| 274 | |
| 275 | static inline |
Evan Cheng | bc9b754 | 2009-08-15 07:59:10 +0000 | [diff] [blame] | 276 | const MachineInstrBuilder &AddNoT1CC(const MachineInstrBuilder &MIB) { |
| 277 | return MIB.addReg(0); |
| 278 | } |
| 279 | |
| 280 | static inline |
Evan Cheng | 6495f63 | 2009-07-28 05:48:47 +0000 | [diff] [blame] | 281 | bool isUncondBranchOpcode(int Opc) { |
| 282 | return Opc == ARM::B || Opc == ARM::tB || Opc == ARM::t2B; |
| 283 | } |
| 284 | |
| 285 | static inline |
| 286 | bool isCondBranchOpcode(int Opc) { |
| 287 | return Opc == ARM::Bcc || Opc == ARM::tBcc || Opc == ARM::t2Bcc; |
| 288 | } |
| 289 | |
| 290 | static inline |
| 291 | bool isJumpTableBranchOpcode(int Opc) { |
| 292 | return Opc == ARM::BR_JTr || Opc == ARM::BR_JTm || Opc == ARM::BR_JTadd || |
| 293 | Opc == ARM::tBR_JTr || Opc == ARM::t2BR_JT; |
| 294 | } |
| 295 | |
Evan Cheng | 8fb9036 | 2009-08-08 03:20:32 +0000 | [diff] [blame] | 296 | /// getInstrPredicate - If instruction is predicated, returns its predicate |
| 297 | /// condition, otherwise returns AL. It also returns the condition code |
| 298 | /// register by reference. |
| 299 | ARMCC::CondCodes getInstrPredicate(MachineInstr *MI, unsigned &PredReg); |
| 300 | |
Evan Cheng | 6495f63 | 2009-07-28 05:48:47 +0000 | [diff] [blame] | 301 | int getMatchingCondBranchOpcode(int Opc); |
| 302 | |
| 303 | /// emitARMRegPlusImmediate / emitT2RegPlusImmediate - Emits a series of |
| 304 | /// instructions to materializea destreg = basereg + immediate in ARM / Thumb2 |
| 305 | /// code. |
| 306 | void emitARMRegPlusImmediate(MachineBasicBlock &MBB, |
| 307 | MachineBasicBlock::iterator &MBBI, DebugLoc dl, |
| 308 | unsigned DestReg, unsigned BaseReg, int NumBytes, |
| 309 | ARMCC::CondCodes Pred, unsigned PredReg, |
| 310 | const ARMBaseInstrInfo &TII); |
| 311 | |
| 312 | void emitT2RegPlusImmediate(MachineBasicBlock &MBB, |
| 313 | MachineBasicBlock::iterator &MBBI, DebugLoc dl, |
| 314 | unsigned DestReg, unsigned BaseReg, int NumBytes, |
| 315 | ARMCC::CondCodes Pred, unsigned PredReg, |
| 316 | const ARMBaseInstrInfo &TII); |
| 317 | |
| 318 | |
Jim Grosbach | 764ab52 | 2009-08-11 15:33:49 +0000 | [diff] [blame] | 319 | /// rewriteARMFrameIndex / rewriteT2FrameIndex - |
Evan Cheng | cdbb3f5 | 2009-08-27 01:23:50 +0000 | [diff] [blame] | 320 | /// Rewrite MI to access 'Offset' bytes from the FP. Return false if the |
| 321 | /// offset could not be handled directly in MI, and return the left-over |
| 322 | /// portion by reference. |
| 323 | bool rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx, |
| 324 | unsigned FrameReg, int &Offset, |
| 325 | const ARMBaseInstrInfo &TII); |
Evan Cheng | 6495f63 | 2009-07-28 05:48:47 +0000 | [diff] [blame] | 326 | |
Evan Cheng | cdbb3f5 | 2009-08-27 01:23:50 +0000 | [diff] [blame] | 327 | bool rewriteT2FrameIndex(MachineInstr &MI, unsigned FrameRegIdx, |
| 328 | unsigned FrameReg, int &Offset, |
| 329 | const ARMBaseInstrInfo &TII); |
Evan Cheng | 6495f63 | 2009-07-28 05:48:47 +0000 | [diff] [blame] | 330 | |
| 331 | } // End llvm namespace |
| 332 | |
David Goodwin | 334c264 | 2009-07-08 16:09:28 +0000 | [diff] [blame] | 333 | #endif |