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gerrit-public.fairphone.software / fp2-dev / platform / external / llvm / f854597fc1a183a9d13827a6eeb9f53a69819497 / . / docs / CommandGuide / tblgen.rst
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Daniel Dunbar3b709d52012-05-08 16:50:35 +0000[diff] [blame]1tblgen - Target Description To C++ Code Generator
2=================================================
3
4
5SYNOPSIS
6--------
7
8
9**tblgen** [*options*] [*filename*]
10
11
12DESCRIPTION
13-----------
14
15
16**tblgen** translates from target description (.td) files into C++ code that can
17be included in the definition of an LLVM target library. Most users of LLVM will
18not need to use this program. It is only for assisting with writing an LLVM
19target backend.
20
21The input and output of **tblgen** is beyond the scope of this short
22introduction. Please see the *CodeGeneration* page in the LLVM documentation.
23
24The *filename* argument specifies the name of a Target Description (.td) file
25to read as input.
26
27
28OPTIONS
29-------
30
31
32
33**-help**
34
35 Print a summary of command line options.
36
37
38
39**-o** *filename*
40
41 Specify the output file name. If *filename* is ``-``, then **tblgen**
42 sends its output to standard output.
43
44
45
46**-I** *directory*
47
48 Specify where to find other target description files for inclusion. The
49 *directory* value should be a full or partial path to a directory that contains
50 target description files.
51
52
53
54**-asmparsernum** *N*
55
56 Make -gen-asm-parser emit assembly writer number *N*.
57
58
59
60**-asmwriternum** *N*
61
62 Make -gen-asm-writer emit assembly writer number *N*.
63
64
65
66**-class** *class Name*
67
68 Print the enumeration list for this class.
69
70
71
72**-print-records**
73
74 Print all records to standard output (default).
75
76
77
78**-print-enums**
79
80 Print enumeration values for a class
81
82
83
84**-print-sets**
85
86 Print expanded sets for testing DAG exprs.
87
88
89
90**-gen-emitter**
91
92 Generate machine code emitter.
93
94
95
96**-gen-register-info**
97
98 Generate registers and register classes info.
99
100
101
102**-gen-instr-info**
103
104 Generate instruction descriptions.
105
106
107
108**-gen-asm-writer**
109
110 Generate the assembly writer.
111
112
113
114**-gen-disassembler**
115
116 Generate disassembler.
117
118
119
120**-gen-pseudo-lowering**
121
122 Generate pseudo instruction lowering.
123
124
125
126**-gen-dag-isel**
127
128 Generate a DAG (Directed Acycle Graph) instruction selector.
129
130
131
132**-gen-asm-matcher**
133
134 Generate assembly instruction matcher.
135
136
137
138**-gen-dfa-packetizer**
139
140 Generate DFA Packetizer for VLIW targets.
141
142
143
144**-gen-fast-isel**
145
146 Generate a "fast" instruction selector.
147
148
149
150**-gen-subtarget**
151
152 Generate subtarget enumerations.
153
154
155
156**-gen-intrinsic**
157
158 Generate intrinsic information.
159
160
161
162**-gen-tgt-intrinsic**
163
164 Generate target intrinsic information.
165
166
167
168**-gen-enhanced-disassembly-info**
169
170 Generate enhanced disassembly info.
171
172
173
174**-version**
175
176 Show the version number of this program.
177
178
179
180
181EXIT STATUS
182-----------
183
184
185If **tblgen** succeeds, it will exit with 0. Otherwise, if an error
186occurs, it will exit with a non-zero value.