blob: 5e6f7b1fd5685fa7a60c27c001198653e3dd4312 [file] [log] [blame]
Venkatraman Govindaraju7d29ffb2011-01-12 03:18:21 +00001
Chris Lattnerd23405e2008-03-17 03:21:36 +00002//===-- SparcISelLowering.cpp - Sparc DAG Lowering Implementation ---------===//
3//
4// The LLVM Compiler Infrastructure
5//
6// This file is distributed under the University of Illinois Open Source
7// License. See LICENSE.TXT for details.
8//
9//===----------------------------------------------------------------------===//
10//
11// This file implements the interfaces that Sparc uses to lower LLVM code into a
12// selection DAG.
13//
14//===----------------------------------------------------------------------===//
15
16#include "SparcISelLowering.h"
17#include "SparcTargetMachine.h"
Dan Gohman1e93df62010-04-17 14:41:14 +000018#include "SparcMachineFunctionInfo.h"
Venkatraman Govindaraju58269b92011-02-21 03:42:44 +000019#include "llvm/DerivedTypes.h"
Chris Lattnerd23405e2008-03-17 03:21:36 +000020#include "llvm/Function.h"
Venkatraman Govindaraju58269b92011-02-21 03:42:44 +000021#include "llvm/Module.h"
Chris Lattner5a65b922008-03-17 05:41:48 +000022#include "llvm/CodeGen/CallingConvLower.h"
Chris Lattnerd23405e2008-03-17 03:21:36 +000023#include "llvm/CodeGen/MachineFrameInfo.h"
24#include "llvm/CodeGen/MachineFunction.h"
25#include "llvm/CodeGen/MachineInstrBuilder.h"
26#include "llvm/CodeGen/MachineRegisterInfo.h"
27#include "llvm/CodeGen/SelectionDAG.h"
Anton Korobeynikov362dd0b2010-02-15 22:37:53 +000028#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
Anton Korobeynikov0eefda12008-10-10 20:28:10 +000029#include "llvm/ADT/VectorExtras.h"
Torok Edwinc25e7582009-07-11 20:10:48 +000030#include "llvm/Support/ErrorHandling.h"
Chris Lattnerd23405e2008-03-17 03:21:36 +000031using namespace llvm;
32
Chris Lattner5a65b922008-03-17 05:41:48 +000033
34//===----------------------------------------------------------------------===//
35// Calling Convention Implementation
36//===----------------------------------------------------------------------===//
37
Venkatraman Govindaraju8184e282011-01-22 13:05:16 +000038static bool CC_Sparc_Assign_SRet(unsigned &ValNo, MVT &ValVT,
39 MVT &LocVT, CCValAssign::LocInfo &LocInfo,
40 ISD::ArgFlagsTy &ArgFlags, CCState &State)
41{
42 assert (ArgFlags.isSRet());
43
44 //Assign SRet argument
45 State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT,
46 0,
47 LocVT, LocInfo));
48 return true;
49}
50
Venkatraman Govindaraju687ae962011-01-18 06:09:55 +000051static bool CC_Sparc_Assign_f64(unsigned &ValNo, MVT &ValVT,
52 MVT &LocVT, CCValAssign::LocInfo &LocInfo,
53 ISD::ArgFlagsTy &ArgFlags, CCState &State)
54{
55 static const unsigned RegList[] = {
56 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5
57 };
58 //Try to get first reg
59 if (unsigned Reg = State.AllocateReg(RegList, 6)) {
60 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
61 } else {
62 //Assign whole thing in stack
63 State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT,
64 State.AllocateStack(8,4),
65 LocVT, LocInfo));
66 return true;
67 }
68
69 //Try to get second reg
70 if (unsigned Reg = State.AllocateReg(RegList, 6))
71 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
72 else
73 State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT,
74 State.AllocateStack(4,4),
75 LocVT, LocInfo));
76 return true;
77}
78
Chris Lattner5a65b922008-03-17 05:41:48 +000079#include "SparcGenCallingConv.inc"
80
Dan Gohman98ca4f22009-08-05 01:29:28 +000081SDValue
82SparcTargetLowering::LowerReturn(SDValue Chain,
Sandeep Patel65c3c8f2009-09-02 08:44:58 +000083 CallingConv::ID CallConv, bool isVarArg,
Dan Gohman98ca4f22009-08-05 01:29:28 +000084 const SmallVectorImpl<ISD::OutputArg> &Outs,
Dan Gohmanc9403652010-07-07 15:54:55 +000085 const SmallVectorImpl<SDValue> &OutVals,
Dan Gohmand858e902010-04-17 15:26:15 +000086 DebugLoc dl, SelectionDAG &DAG) const {
Dan Gohman98ca4f22009-08-05 01:29:28 +000087
Venkatraman Govindaraju8184e282011-01-22 13:05:16 +000088 MachineFunction &MF = DAG.getMachineFunction();
89
Chris Lattner5a65b922008-03-17 05:41:48 +000090 // CCValAssign - represent the assignment of the return value to locations.
91 SmallVector<CCValAssign, 16> RVLocs;
Anton Korobeynikov53835702008-10-10 20:27:31 +000092
Chris Lattner5a65b922008-03-17 05:41:48 +000093 // CCState - Info about the registers and stack slot.
Dan Gohman98ca4f22009-08-05 01:29:28 +000094 CCState CCInfo(CallConv, isVarArg, DAG.getTarget(),
95 RVLocs, *DAG.getContext());
Anton Korobeynikov53835702008-10-10 20:27:31 +000096
Dan Gohman98ca4f22009-08-05 01:29:28 +000097 // Analize return values.
98 CCInfo.AnalyzeReturn(Outs, RetCC_Sparc32);
Anton Korobeynikov53835702008-10-10 20:27:31 +000099
Chris Lattner5a65b922008-03-17 05:41:48 +0000100 // If this is the first return lowered for this function, add the regs to the
101 // liveout set for the function.
Venkatraman Govindaraju8184e282011-01-22 13:05:16 +0000102 if (MF.getRegInfo().liveout_empty()) {
Chris Lattner5a65b922008-03-17 05:41:48 +0000103 for (unsigned i = 0; i != RVLocs.size(); ++i)
104 if (RVLocs[i].isRegLoc())
Venkatraman Govindaraju8184e282011-01-22 13:05:16 +0000105 MF.getRegInfo().addLiveOut(RVLocs[i].getLocReg());
Chris Lattner5a65b922008-03-17 05:41:48 +0000106 }
Anton Korobeynikov53835702008-10-10 20:27:31 +0000107
Dan Gohman475871a2008-07-27 21:46:04 +0000108 SDValue Flag;
Chris Lattner5a65b922008-03-17 05:41:48 +0000109
110 // Copy the result values into the output registers.
111 for (unsigned i = 0; i != RVLocs.size(); ++i) {
112 CCValAssign &VA = RVLocs[i];
113 assert(VA.isRegLoc() && "Can only return in registers!");
Anton Korobeynikov53835702008-10-10 20:27:31 +0000114
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000115 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
Dan Gohmanc9403652010-07-07 15:54:55 +0000116 OutVals[i], Flag);
Anton Korobeynikov53835702008-10-10 20:27:31 +0000117
Chris Lattner5a65b922008-03-17 05:41:48 +0000118 // Guarantee that all emitted copies are stuck together with flags.
119 Flag = Chain.getValue(1);
120 }
Venkatraman Govindaraju58269b92011-02-21 03:42:44 +0000121
122 unsigned RetAddrOffset = 8; //Call Inst + Delay Slot
Venkatraman Govindaraju8184e282011-01-22 13:05:16 +0000123 // If the function returns a struct, copy the SRetReturnReg to I0
124 if (MF.getFunction()->hasStructRetAttr()) {
125 SparcMachineFunctionInfo *SFI = MF.getInfo<SparcMachineFunctionInfo>();
126 unsigned Reg = SFI->getSRetReturnReg();
127 if (!Reg)
128 llvm_unreachable("sret virtual register not created in the entry block");
129 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
130 Chain = DAG.getCopyToReg(Chain, dl, SP::I0, Val, Flag);
131 Flag = Chain.getValue(1);
132 if (MF.getRegInfo().liveout_empty())
133 MF.getRegInfo().addLiveOut(SP::I0);
Venkatraman Govindaraju58269b92011-02-21 03:42:44 +0000134 RetAddrOffset = 12; // CallInst + Delay Slot + Unimp
Venkatraman Govindaraju8184e282011-01-22 13:05:16 +0000135 }
Anton Korobeynikov53835702008-10-10 20:27:31 +0000136
Venkatraman Govindaraju58269b92011-02-21 03:42:44 +0000137 SDValue RetAddrOffsetNode = DAG.getConstant(RetAddrOffset, MVT::i32);
138
Gabor Greifba36cb52008-08-28 21:40:38 +0000139 if (Flag.getNode())
Venkatraman Govindaraju58269b92011-02-21 03:42:44 +0000140 return DAG.getNode(SPISD::RET_FLAG, dl, MVT::Other, Chain,
141 RetAddrOffsetNode, Flag);
142 return DAG.getNode(SPISD::RET_FLAG, dl, MVT::Other, Chain,
143 RetAddrOffsetNode);
Chris Lattner5a65b922008-03-17 05:41:48 +0000144}
145
Dan Gohman98ca4f22009-08-05 01:29:28 +0000146/// LowerFormalArguments - V8 uses a very simple ABI, where all values are
147/// passed in either one or two GPRs, including FP values. TODO: we should
148/// pass FP values in FP registers for fastcc functions.
Eli Friedmana786c7b2009-07-19 19:53:46 +0000149SDValue
Dan Gohman98ca4f22009-08-05 01:29:28 +0000150SparcTargetLowering::LowerFormalArguments(SDValue Chain,
Sandeep Patel65c3c8f2009-09-02 08:44:58 +0000151 CallingConv::ID CallConv, bool isVarArg,
Dan Gohman98ca4f22009-08-05 01:29:28 +0000152 const SmallVectorImpl<ISD::InputArg>
153 &Ins,
154 DebugLoc dl, SelectionDAG &DAG,
Dan Gohmand858e902010-04-17 15:26:15 +0000155 SmallVectorImpl<SDValue> &InVals)
156 const {
Dan Gohman98ca4f22009-08-05 01:29:28 +0000157
Chris Lattner5a65b922008-03-17 05:41:48 +0000158 MachineFunction &MF = DAG.getMachineFunction();
159 MachineRegisterInfo &RegInfo = MF.getRegInfo();
Dan Gohman1e93df62010-04-17 14:41:14 +0000160 SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>();
Eli Friedmana786c7b2009-07-19 19:53:46 +0000161
162 // Assign locations to all of the incoming arguments.
163 SmallVector<CCValAssign, 16> ArgLocs;
Dan Gohman98ca4f22009-08-05 01:29:28 +0000164 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
165 ArgLocs, *DAG.getContext());
166 CCInfo.AnalyzeFormalArguments(Ins, CC_Sparc32);
Anton Korobeynikov53835702008-10-10 20:27:31 +0000167
Venkatraman Govindaraju687ae962011-01-18 06:09:55 +0000168 const unsigned StackOffset = 92;
Anton Korobeynikov53835702008-10-10 20:27:31 +0000169
Eli Friedmana786c7b2009-07-19 19:53:46 +0000170 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
Eli Friedmana786c7b2009-07-19 19:53:46 +0000171 CCValAssign &VA = ArgLocs[i];
Chris Lattner5a65b922008-03-17 05:41:48 +0000172
Venkatraman Govindaraju8184e282011-01-22 13:05:16 +0000173 if (i == 0 && Ins[i].Flags.isSRet()) {
174 //Get SRet from [%fp+64]
175 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, 64, true);
176 SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
177 SDValue Arg = DAG.getLoad(MVT::i32, dl, Chain, FIPtr,
178 MachinePointerInfo(),
179 false, false, 0);
180 InVals.push_back(Arg);
181 continue;
182 }
183
Venkatraman Govindaraju687ae962011-01-18 06:09:55 +0000184 if (VA.isRegLoc()) {
Venkatraman Govindaraju687ae962011-01-18 06:09:55 +0000185 if (VA.needsCustom()) {
186 assert(VA.getLocVT() == MVT::f64);
187 unsigned VRegHi = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
188 MF.getRegInfo().addLiveIn(VA.getLocReg(), VRegHi);
189 SDValue HiVal = DAG.getCopyFromReg(Chain, dl, VRegHi, MVT::i32);
Chris Lattner5a65b922008-03-17 05:41:48 +0000190
Venkatraman Govindaraju687ae962011-01-18 06:09:55 +0000191 assert(i+1 < e);
192 CCValAssign &NextVA = ArgLocs[++i];
Anton Korobeynikov53835702008-10-10 20:27:31 +0000193
Dan Gohman475871a2008-07-27 21:46:04 +0000194 SDValue LoVal;
Venkatraman Govindaraju687ae962011-01-18 06:09:55 +0000195 if (NextVA.isMemLoc()) {
196 int FrameIdx = MF.getFrameInfo()->
197 CreateFixedObject(4, StackOffset+NextVA.getLocMemOffset(),true);
Owen Anderson825b72b2009-08-11 20:47:22 +0000198 SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
Venkatraman Govindaraju687ae962011-01-18 06:09:55 +0000199 LoVal = DAG.getLoad(MVT::i32, dl, Chain, FIPtr,
200 MachinePointerInfo(),
David Greene54a7aa82010-02-15 16:57:02 +0000201 false, false, 0);
Venkatraman Govindaraju687ae962011-01-18 06:09:55 +0000202 } else {
203 unsigned loReg = MF.addLiveIn(NextVA.getLocReg(),
Devang Patel68e6bee2011-02-21 23:21:26 +0000204 &SP::IntRegsRegClass);
Venkatraman Govindaraju687ae962011-01-18 06:09:55 +0000205 LoVal = DAG.getCopyFromReg(Chain, dl, loReg, MVT::i32);
Chris Lattner5a65b922008-03-17 05:41:48 +0000206 }
Anton Korobeynikov53835702008-10-10 20:27:31 +0000207 SDValue WholeValue =
Owen Anderson825b72b2009-08-11 20:47:22 +0000208 DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, LoVal, HiVal);
Venkatraman Govindaraju687ae962011-01-18 06:09:55 +0000209 WholeValue = DAG.getNode(ISD::BITCAST, dl, MVT::f64, WholeValue);
Dan Gohman98ca4f22009-08-05 01:29:28 +0000210 InVals.push_back(WholeValue);
Venkatraman Govindaraju687ae962011-01-18 06:09:55 +0000211 continue;
Chris Lattner5a65b922008-03-17 05:41:48 +0000212 }
Venkatraman Govindaraju687ae962011-01-18 06:09:55 +0000213 unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
214 MF.getRegInfo().addLiveIn(VA.getLocReg(), VReg);
215 SDValue Arg = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
216 if (VA.getLocVT() == MVT::f32)
217 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::f32, Arg);
218 else if (VA.getLocVT() != MVT::i32) {
219 Arg = DAG.getNode(ISD::AssertSext, dl, MVT::i32, Arg,
220 DAG.getValueType(VA.getLocVT()));
221 Arg = DAG.getNode(ISD::TRUNCATE, dl, VA.getLocVT(), Arg);
222 }
223 InVals.push_back(Arg);
224 continue;
Chris Lattner5a65b922008-03-17 05:41:48 +0000225 }
Venkatraman Govindaraju687ae962011-01-18 06:09:55 +0000226
227 assert(VA.isMemLoc());
228
229 unsigned Offset = VA.getLocMemOffset()+StackOffset;
230
231 if (VA.needsCustom()) {
232 assert(VA.getValVT() == MVT::f64);
233 //If it is double-word aligned, just load.
234 if (Offset % 8 == 0) {
235 int FI = MF.getFrameInfo()->CreateFixedObject(8,
236 Offset,
237 true);
238 SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy());
239 SDValue Load = DAG.getLoad(VA.getValVT(), dl, Chain, FIPtr,
240 MachinePointerInfo(),
241 false,false, 0);
242 InVals.push_back(Load);
243 continue;
244 }
245
246 int FI = MF.getFrameInfo()->CreateFixedObject(4,
247 Offset,
248 true);
249 SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy());
250 SDValue HiVal = DAG.getLoad(MVT::i32, dl, Chain, FIPtr,
251 MachinePointerInfo(),
252 false, false, 0);
253 int FI2 = MF.getFrameInfo()->CreateFixedObject(4,
254 Offset+4,
255 true);
256 SDValue FIPtr2 = DAG.getFrameIndex(FI2, getPointerTy());
257
258 SDValue LoVal = DAG.getLoad(MVT::i32, dl, Chain, FIPtr2,
259 MachinePointerInfo(),
260 false, false, 0);
261
262 SDValue WholeValue =
263 DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, LoVal, HiVal);
264 WholeValue = DAG.getNode(ISD::BITCAST, dl, MVT::f64, WholeValue);
265 InVals.push_back(WholeValue);
266 continue;
267 }
268
269 int FI = MF.getFrameInfo()->CreateFixedObject(4,
270 Offset,
271 true);
272 SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy());
273 SDValue Load ;
274 if (VA.getValVT() == MVT::i32 || VA.getValVT() == MVT::f32) {
275 Load = DAG.getLoad(VA.getValVT(), dl, Chain, FIPtr,
276 MachinePointerInfo(),
277 false, false, 0);
278 } else {
279 ISD::LoadExtType LoadOp = ISD::SEXTLOAD;
280 // Sparc is big endian, so add an offset based on the ObjectVT.
281 unsigned Offset = 4-std::max(1U, VA.getValVT().getSizeInBits()/8);
282 FIPtr = DAG.getNode(ISD::ADD, dl, MVT::i32, FIPtr,
283 DAG.getConstant(Offset, MVT::i32));
Stuart Hastingsa9011292011-02-16 16:23:55 +0000284 Load = DAG.getExtLoad(LoadOp, dl, MVT::i32, Chain, FIPtr,
Venkatraman Govindaraju687ae962011-01-18 06:09:55 +0000285 MachinePointerInfo(),
286 VA.getValVT(), false, false,0);
287 Load = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Load);
288 }
289 InVals.push_back(Load);
Chris Lattner5a65b922008-03-17 05:41:48 +0000290 }
Anton Korobeynikov53835702008-10-10 20:27:31 +0000291
Venkatraman Govindaraju8184e282011-01-22 13:05:16 +0000292 if (MF.getFunction()->hasStructRetAttr()) {
293 //Copy the SRet Argument to SRetReturnReg
294 SparcMachineFunctionInfo *SFI = MF.getInfo<SparcMachineFunctionInfo>();
295 unsigned Reg = SFI->getSRetReturnReg();
296 if (!Reg) {
297 Reg = MF.getRegInfo().createVirtualRegister(&SP::IntRegsRegClass);
298 SFI->setSRetReturnReg(Reg);
299 }
300 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
301 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
302 }
303
Chris Lattner5a65b922008-03-17 05:41:48 +0000304 // Store remaining ArgRegs to the stack if this is a varargs function.
Eli Friedmana786c7b2009-07-19 19:53:46 +0000305 if (isVarArg) {
Venkatraman Govindaraju687ae962011-01-18 06:09:55 +0000306 static const unsigned ArgRegs[] = {
307 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5
308 };
309 unsigned NumAllocated = CCInfo.getFirstUnallocated(ArgRegs, 6);
310 const unsigned *CurArgReg = ArgRegs+NumAllocated, *ArgRegEnd = ArgRegs+6;
311 unsigned ArgOffset = CCInfo.getNextStackOffset();
312 if (NumAllocated == 6)
313 ArgOffset += StackOffset;
314 else {
315 assert(!ArgOffset);
316 ArgOffset = 68+4*NumAllocated;
317 }
318
Chris Lattner5a65b922008-03-17 05:41:48 +0000319 // Remember the vararg offset for the va_start implementation.
Dan Gohman1e93df62010-04-17 14:41:14 +0000320 FuncInfo->setVarArgsFrameOffset(ArgOffset);
Anton Korobeynikov53835702008-10-10 20:27:31 +0000321
Eli Friedmana786c7b2009-07-19 19:53:46 +0000322 std::vector<SDValue> OutChains;
323
Chris Lattner5a65b922008-03-17 05:41:48 +0000324 for (; CurArgReg != ArgRegEnd; ++CurArgReg) {
325 unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
326 MF.getRegInfo().addLiveIn(*CurArgReg, VReg);
Owen Anderson825b72b2009-08-11 20:47:22 +0000327 SDValue Arg = DAG.getCopyFromReg(DAG.getRoot(), dl, VReg, MVT::i32);
Chris Lattner5a65b922008-03-17 05:41:48 +0000328
David Greene3f2bf852009-11-12 20:49:22 +0000329 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset,
Evan Chenged2ae132010-07-03 00:40:23 +0000330 true);
Owen Anderson825b72b2009-08-11 20:47:22 +0000331 SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
Chris Lattner5a65b922008-03-17 05:41:48 +0000332
Chris Lattner6229d0a2010-09-21 18:41:36 +0000333 OutChains.push_back(DAG.getStore(DAG.getRoot(), dl, Arg, FIPtr,
334 MachinePointerInfo(),
David Greene54a7aa82010-02-15 16:57:02 +0000335 false, false, 0));
Chris Lattner5a65b922008-03-17 05:41:48 +0000336 ArgOffset += 4;
337 }
Eli Friedmana786c7b2009-07-19 19:53:46 +0000338
339 if (!OutChains.empty()) {
Dan Gohman98ca4f22009-08-05 01:29:28 +0000340 OutChains.push_back(Chain);
Owen Anderson825b72b2009-08-11 20:47:22 +0000341 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
Dan Gohman98ca4f22009-08-05 01:29:28 +0000342 &OutChains[0], OutChains.size());
Eli Friedmana786c7b2009-07-19 19:53:46 +0000343 }
Chris Lattner5a65b922008-03-17 05:41:48 +0000344 }
Anton Korobeynikov53835702008-10-10 20:27:31 +0000345
Dan Gohman98ca4f22009-08-05 01:29:28 +0000346 return Chain;
Chris Lattner5a65b922008-03-17 05:41:48 +0000347}
348
Dan Gohman98ca4f22009-08-05 01:29:28 +0000349SDValue
Evan Cheng022d9e12010-02-02 23:55:14 +0000350SparcTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
Sandeep Patel65c3c8f2009-09-02 08:44:58 +0000351 CallingConv::ID CallConv, bool isVarArg,
Evan Cheng0c439eb2010-01-27 00:07:07 +0000352 bool &isTailCall,
Dan Gohman98ca4f22009-08-05 01:29:28 +0000353 const SmallVectorImpl<ISD::OutputArg> &Outs,
Dan Gohmanc9403652010-07-07 15:54:55 +0000354 const SmallVectorImpl<SDValue> &OutVals,
Dan Gohman98ca4f22009-08-05 01:29:28 +0000355 const SmallVectorImpl<ISD::InputArg> &Ins,
356 DebugLoc dl, SelectionDAG &DAG,
Dan Gohmand858e902010-04-17 15:26:15 +0000357 SmallVectorImpl<SDValue> &InVals) const {
Evan Cheng0c439eb2010-01-27 00:07:07 +0000358 // Sparc target does not yet support tail call optimization.
359 isTailCall = false;
Chris Lattner98949a62008-03-17 06:01:07 +0000360
Chris Lattner315123f2008-03-17 06:58:37 +0000361 // Analyze operands of the call, assigning locations to each operand.
362 SmallVector<CCValAssign, 16> ArgLocs;
Venkatraman Govindaraju687ae962011-01-18 06:09:55 +0000363 CCState CCInfo(CallConv, isVarArg, DAG.getTarget(), ArgLocs,
364 *DAG.getContext());
Dan Gohman98ca4f22009-08-05 01:29:28 +0000365 CCInfo.AnalyzeCallOperands(Outs, CC_Sparc32);
Anton Korobeynikov53835702008-10-10 20:27:31 +0000366
Chris Lattner315123f2008-03-17 06:58:37 +0000367 // Get the size of the outgoing arguments stack space requirement.
368 unsigned ArgsSize = CCInfo.getNextStackOffset();
Anton Korobeynikov53835702008-10-10 20:27:31 +0000369
Chris Lattner5a65b922008-03-17 05:41:48 +0000370 // Keep stack frames 8-byte aligned.
371 ArgsSize = (ArgsSize+7) & ~7;
372
Venkatraman Govindaraju46713292011-01-21 14:00:01 +0000373 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
374
375 //Create local copies for byval args.
376 SmallVector<SDValue, 8> ByValArgs;
377 for (unsigned i = 0, e = Outs.size(); i != e; ++i) {
378 ISD::ArgFlagsTy Flags = Outs[i].Flags;
379 if (!Flags.isByVal())
380 continue;
381
382 SDValue Arg = OutVals[i];
383 unsigned Size = Flags.getByValSize();
384 unsigned Align = Flags.getByValAlign();
385
386 int FI = MFI->CreateStackObject(Size, Align, false);
387 SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy());
388 SDValue SizeNode = DAG.getConstant(Size, MVT::i32);
389
390 Chain = DAG.getMemcpy(Chain, dl, FIPtr, Arg, SizeNode, Align,
391 false, //isVolatile,
392 (Size <= 32), //AlwaysInline if size <= 32
393 MachinePointerInfo(), MachinePointerInfo());
394 ByValArgs.push_back(FIPtr);
395 }
396
Chris Lattnere563bbc2008-10-11 22:08:30 +0000397 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(ArgsSize, true));
Anton Korobeynikov53835702008-10-10 20:27:31 +0000398
Dan Gohman475871a2008-07-27 21:46:04 +0000399 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
400 SmallVector<SDValue, 8> MemOpChains;
Anton Korobeynikov53835702008-10-10 20:27:31 +0000401
Venkatraman Govindaraju687ae962011-01-18 06:09:55 +0000402 const unsigned StackOffset = 92;
Venkatraman Govindaraju58269b92011-02-21 03:42:44 +0000403 bool hasStructRetAttr = false;
Chris Lattner315123f2008-03-17 06:58:37 +0000404 // Walk the register/memloc assignments, inserting copies/loads.
Venkatraman Govindaraju46713292011-01-21 14:00:01 +0000405 for (unsigned i = 0, realArgIdx = 0, byvalArgIdx = 0, e = ArgLocs.size();
Venkatraman Govindaraju687ae962011-01-18 06:09:55 +0000406 i != e;
407 ++i, ++realArgIdx) {
Chris Lattner315123f2008-03-17 06:58:37 +0000408 CCValAssign &VA = ArgLocs[i];
Venkatraman Govindaraju687ae962011-01-18 06:09:55 +0000409 SDValue Arg = OutVals[realArgIdx];
Chris Lattner315123f2008-03-17 06:58:37 +0000410
Venkatraman Govindaraju46713292011-01-21 14:00:01 +0000411 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
412
413 //Use local copy if it is a byval arg.
414 if (Flags.isByVal())
415 Arg = ByValArgs[byvalArgIdx++];
416
Chris Lattner315123f2008-03-17 06:58:37 +0000417 // Promote the value if needed.
418 switch (VA.getLocInfo()) {
Torok Edwinc23197a2009-07-14 16:55:14 +0000419 default: llvm_unreachable("Unknown loc info!");
Chris Lattner315123f2008-03-17 06:58:37 +0000420 case CCValAssign::Full: break;
421 case CCValAssign::SExt:
Venkatraman Govindaraju687ae962011-01-18 06:09:55 +0000422 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
Chris Lattner315123f2008-03-17 06:58:37 +0000423 break;
424 case CCValAssign::ZExt:
Venkatraman Govindaraju687ae962011-01-18 06:09:55 +0000425 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
Chris Lattner315123f2008-03-17 06:58:37 +0000426 break;
427 case CCValAssign::AExt:
Venkatraman Govindaraju687ae962011-01-18 06:09:55 +0000428 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
429 break;
430 case CCValAssign::BCvt:
431 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
Chris Lattner315123f2008-03-17 06:58:37 +0000432 break;
433 }
Anton Korobeynikov53835702008-10-10 20:27:31 +0000434
Venkatraman Govindaraju8184e282011-01-22 13:05:16 +0000435 if (Flags.isSRet()) {
436 assert(VA.needsCustom());
437 // store SRet argument in %sp+64
438 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
439 SDValue PtrOff = DAG.getIntPtrConstant(64);
440 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
441 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
442 MachinePointerInfo(),
443 false, false, 0));
Venkatraman Govindaraju58269b92011-02-21 03:42:44 +0000444 hasStructRetAttr = true;
Venkatraman Govindaraju8184e282011-01-22 13:05:16 +0000445 continue;
446 }
447
Venkatraman Govindaraju687ae962011-01-18 06:09:55 +0000448 if (VA.needsCustom()) {
449 assert(VA.getLocVT() == MVT::f64);
Anton Korobeynikov53835702008-10-10 20:27:31 +0000450
Venkatraman Govindaraju687ae962011-01-18 06:09:55 +0000451 if (VA.isMemLoc()) {
452 unsigned Offset = VA.getLocMemOffset() + StackOffset;
453 //if it is double-word aligned, just store.
454 if (Offset % 8 == 0) {
455 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
456 SDValue PtrOff = DAG.getIntPtrConstant(Offset);
457 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
458 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
459 MachinePointerInfo(),
460 false, false, 0));
461 continue;
Venkatraman Govindaraju12db7b62010-12-29 05:37:15 +0000462 }
463 }
Venkatraman Govindaraju687ae962011-01-18 06:09:55 +0000464
Owen Anderson825b72b2009-08-11 20:47:22 +0000465 SDValue StackPtr = DAG.CreateStackTemporary(MVT::f64, MVT::i32);
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000466 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl,
Venkatraman Govindaraju687ae962011-01-18 06:09:55 +0000467 Arg, StackPtr, MachinePointerInfo(),
David Greene54a7aa82010-02-15 16:57:02 +0000468 false, false, 0);
Duncan Sands8c0f2442008-12-12 08:05:40 +0000469 // Sparc is big-endian, so the high part comes first.
Chris Lattnerd1c24ed2010-09-21 06:44:06 +0000470 SDValue Hi = DAG.getLoad(MVT::i32, dl, Store, StackPtr,
471 MachinePointerInfo(), false, false, 0);
Duncan Sands8c0f2442008-12-12 08:05:40 +0000472 // Increment the pointer to the other half.
Dale Johannesen33c960f2009-02-04 20:06:27 +0000473 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
Duncan Sands8c0f2442008-12-12 08:05:40 +0000474 DAG.getIntPtrConstant(4));
475 // Load the low part.
Chris Lattnerd1c24ed2010-09-21 06:44:06 +0000476 SDValue Lo = DAG.getLoad(MVT::i32, dl, Store, StackPtr,
477 MachinePointerInfo(), false, false, 0);
Duncan Sands8c0f2442008-12-12 08:05:40 +0000478
Venkatraman Govindaraju687ae962011-01-18 06:09:55 +0000479 if (VA.isRegLoc()) {
480 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Hi));
481 assert(i+1 != e);
482 CCValAssign &NextVA = ArgLocs[++i];
483 if (NextVA.isRegLoc()) {
484 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), Lo));
485 } else {
486 //Store the low part in stack.
487 unsigned Offset = NextVA.getLocMemOffset() + StackOffset;
488 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
489 SDValue PtrOff = DAG.getIntPtrConstant(Offset);
490 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
491 MemOpChains.push_back(DAG.getStore(Chain, dl, Lo, PtrOff,
492 MachinePointerInfo(),
493 false, false, 0));
Venkatraman Govindaraju12db7b62010-12-29 05:37:15 +0000494 }
Venkatraman Govindaraju12db7b62010-12-29 05:37:15 +0000495 } else {
Venkatraman Govindaraju687ae962011-01-18 06:09:55 +0000496 unsigned Offset = VA.getLocMemOffset() + StackOffset;
497 // Store the high part.
498 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
499 SDValue PtrOff = DAG.getIntPtrConstant(Offset);
500 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
501 MemOpChains.push_back(DAG.getStore(Chain, dl, Hi, PtrOff,
502 MachinePointerInfo(),
503 false, false, 0));
504 // Store the low part.
505 PtrOff = DAG.getIntPtrConstant(Offset+4);
506 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
507 MemOpChains.push_back(DAG.getStore(Chain, dl, Lo, PtrOff,
508 MachinePointerInfo(),
509 false, false, 0));
Venkatraman Govindaraju12db7b62010-12-29 05:37:15 +0000510 }
Venkatraman Govindaraju687ae962011-01-18 06:09:55 +0000511 continue;
Duncan Sands8c0f2442008-12-12 08:05:40 +0000512 }
Anton Korobeynikov53835702008-10-10 20:27:31 +0000513
Venkatraman Govindaraju687ae962011-01-18 06:09:55 +0000514 // Arguments that can be passed on register must be kept at
515 // RegsToPass vector
516 if (VA.isRegLoc()) {
517 if (VA.getLocVT() != MVT::f32) {
518 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
519 continue;
520 }
521 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg);
522 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
523 continue;
Chris Lattner5a65b922008-03-17 05:41:48 +0000524 }
Venkatraman Govindaraju687ae962011-01-18 06:09:55 +0000525
526 assert(VA.isMemLoc());
527
528 // Create a store off the stack pointer for this argument.
529 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
530 SDValue PtrOff = DAG.getIntPtrConstant(VA.getLocMemOffset()+StackOffset);
531 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
532 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
533 MachinePointerInfo(),
534 false, false, 0));
Chris Lattner5a65b922008-03-17 05:41:48 +0000535 }
Venkatraman Govindaraju687ae962011-01-18 06:09:55 +0000536
Anton Korobeynikov53835702008-10-10 20:27:31 +0000537
Chris Lattner5a65b922008-03-17 05:41:48 +0000538 // Emit all stores, make sure the occur before any copies into physregs.
Chris Lattner315123f2008-03-17 06:58:37 +0000539 if (!MemOpChains.empty())
Owen Anderson825b72b2009-08-11 20:47:22 +0000540 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
Chris Lattner315123f2008-03-17 06:58:37 +0000541 &MemOpChains[0], MemOpChains.size());
Anton Korobeynikov53835702008-10-10 20:27:31 +0000542
543 // Build a sequence of copy-to-reg nodes chained together with token
Chris Lattner315123f2008-03-17 06:58:37 +0000544 // chain and flag operands which copy the outgoing args into registers.
Chris Lattner7a2bdde2011-04-15 05:18:47 +0000545 // The InFlag in necessary since all emitted instructions must be
Chris Lattner315123f2008-03-17 06:58:37 +0000546 // stuck together.
Dan Gohman475871a2008-07-27 21:46:04 +0000547 SDValue InFlag;
Chris Lattner315123f2008-03-17 06:58:37 +0000548 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
549 unsigned Reg = RegsToPass[i].first;
550 // Remap I0->I7 -> O0->O7.
551 if (Reg >= SP::I0 && Reg <= SP::I7)
552 Reg = Reg-SP::I0+SP::O0;
553
Dale Johannesen33c960f2009-02-04 20:06:27 +0000554 Chain = DAG.getCopyToReg(Chain, dl, Reg, RegsToPass[i].second, InFlag);
Chris Lattner5a65b922008-03-17 05:41:48 +0000555 InFlag = Chain.getValue(1);
556 }
557
Venkatraman Govindaraju58269b92011-02-21 03:42:44 +0000558 unsigned SRetArgSize = (hasStructRetAttr)? getSRetArgSize(DAG, Callee):0;
559
Chris Lattner5a65b922008-03-17 05:41:48 +0000560 // If the callee is a GlobalAddress node (quite common, every direct call is)
561 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
Bill Wendling056292f2008-09-16 21:48:12 +0000562 // Likewise ExternalSymbol -> TargetExternalSymbol.
Chris Lattner5a65b922008-03-17 05:41:48 +0000563 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
Devang Patel0d881da2010-07-06 22:08:15 +0000564 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, MVT::i32);
Bill Wendling056292f2008-09-16 21:48:12 +0000565 else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
Owen Anderson825b72b2009-08-11 20:47:22 +0000566 Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i32);
Chris Lattner5a65b922008-03-17 05:41:48 +0000567
Venkatraman Govindaraju7d29ffb2011-01-12 03:18:21 +0000568 // Returns a chain & a flag for retval copy to use
569 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
570 SmallVector<SDValue, 8> Ops;
571 Ops.push_back(Chain);
572 Ops.push_back(Callee);
Venkatraman Govindaraju58269b92011-02-21 03:42:44 +0000573 if (hasStructRetAttr)
574 Ops.push_back(DAG.getTargetConstant(SRetArgSize, MVT::i32));
Venkatraman Govindaraju7d29ffb2011-01-12 03:18:21 +0000575 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
576 unsigned Reg = RegsToPass[i].first;
577 if (Reg >= SP::I0 && Reg <= SP::I7)
578 Reg = Reg-SP::I0+SP::O0;
579
580 Ops.push_back(DAG.getRegister(Reg, RegsToPass[i].second.getValueType()));
581 }
582 if (InFlag.getNode())
583 Ops.push_back(InFlag);
584
585 Chain = DAG.getNode(SPISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
Chris Lattner5a65b922008-03-17 05:41:48 +0000586 InFlag = Chain.getValue(1);
Anton Korobeynikov53835702008-10-10 20:27:31 +0000587
Chris Lattnere563bbc2008-10-11 22:08:30 +0000588 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(ArgsSize, true),
589 DAG.getIntPtrConstant(0, true), InFlag);
Chris Lattner98949a62008-03-17 06:01:07 +0000590 InFlag = Chain.getValue(1);
Anton Korobeynikov53835702008-10-10 20:27:31 +0000591
Chris Lattner98949a62008-03-17 06:01:07 +0000592 // Assign locations to each value returned by this call.
593 SmallVector<CCValAssign, 16> RVLocs;
Dan Gohman98ca4f22009-08-05 01:29:28 +0000594 CCState RVInfo(CallConv, isVarArg, DAG.getTarget(),
Owen Andersone922c022009-07-22 00:24:57 +0000595 RVLocs, *DAG.getContext());
Anton Korobeynikov53835702008-10-10 20:27:31 +0000596
Dan Gohman98ca4f22009-08-05 01:29:28 +0000597 RVInfo.AnalyzeCallResult(Ins, RetCC_Sparc32);
Anton Korobeynikov53835702008-10-10 20:27:31 +0000598
Chris Lattner98949a62008-03-17 06:01:07 +0000599 // Copy all of the result registers out of their specified physreg.
600 for (unsigned i = 0; i != RVLocs.size(); ++i) {
601 unsigned Reg = RVLocs[i].getLocReg();
Anton Korobeynikov53835702008-10-10 20:27:31 +0000602
Chris Lattner98949a62008-03-17 06:01:07 +0000603 // Remap I0->I7 -> O0->O7.
604 if (Reg >= SP::I0 && Reg <= SP::I7)
605 Reg = Reg-SP::I0+SP::O0;
Anton Korobeynikov53835702008-10-10 20:27:31 +0000606
Dale Johannesen33c960f2009-02-04 20:06:27 +0000607 Chain = DAG.getCopyFromReg(Chain, dl, Reg,
Chris Lattner98949a62008-03-17 06:01:07 +0000608 RVLocs[i].getValVT(), InFlag).getValue(1);
609 InFlag = Chain.getValue(2);
Dan Gohman98ca4f22009-08-05 01:29:28 +0000610 InVals.push_back(Chain.getValue(0));
Chris Lattner5a65b922008-03-17 05:41:48 +0000611 }
Anton Korobeynikov53835702008-10-10 20:27:31 +0000612
Dan Gohman98ca4f22009-08-05 01:29:28 +0000613 return Chain;
Chris Lattner5a65b922008-03-17 05:41:48 +0000614}
615
Venkatraman Govindaraju58269b92011-02-21 03:42:44 +0000616unsigned
617SparcTargetLowering::getSRetArgSize(SelectionDAG &DAG, SDValue Callee) const
618{
619 const Function *CalleeFn = 0;
620 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
621 CalleeFn = dyn_cast<Function>(G->getGlobal());
622 } else if (ExternalSymbolSDNode *E =
623 dyn_cast<ExternalSymbolSDNode>(Callee)) {
624 const Function *Fn = DAG.getMachineFunction().getFunction();
625 const Module *M = Fn->getParent();
626 CalleeFn = M->getFunction(E->getSymbol());
627 }
Chris Lattner5a65b922008-03-17 05:41:48 +0000628
Venkatraman Govindaraju58269b92011-02-21 03:42:44 +0000629 if (!CalleeFn)
630 return 0;
631
632 assert(CalleeFn->hasStructRetAttr() &&
633 "Callee does not have the StructRet attribute.");
634
635 const PointerType *Ty = cast<PointerType>(CalleeFn->arg_begin()->getType());
636 const Type *ElementTy = Ty->getElementType();
637 return getTargetData()->getTypeAllocSize(ElementTy);
638}
Chris Lattner5a65b922008-03-17 05:41:48 +0000639
Chris Lattnerd23405e2008-03-17 03:21:36 +0000640//===----------------------------------------------------------------------===//
641// TargetLowering Implementation
642//===----------------------------------------------------------------------===//
643
644/// IntCondCCodeToICC - Convert a DAG integer condition code to a SPARC ICC
645/// condition.
646static SPCC::CondCodes IntCondCCodeToICC(ISD::CondCode CC) {
647 switch (CC) {
Torok Edwinc23197a2009-07-14 16:55:14 +0000648 default: llvm_unreachable("Unknown integer condition code!");
Chris Lattnerd23405e2008-03-17 03:21:36 +0000649 case ISD::SETEQ: return SPCC::ICC_E;
650 case ISD::SETNE: return SPCC::ICC_NE;
651 case ISD::SETLT: return SPCC::ICC_L;
652 case ISD::SETGT: return SPCC::ICC_G;
653 case ISD::SETLE: return SPCC::ICC_LE;
654 case ISD::SETGE: return SPCC::ICC_GE;
655 case ISD::SETULT: return SPCC::ICC_CS;
656 case ISD::SETULE: return SPCC::ICC_LEU;
657 case ISD::SETUGT: return SPCC::ICC_GU;
658 case ISD::SETUGE: return SPCC::ICC_CC;
659 }
660}
661
662/// FPCondCCodeToFCC - Convert a DAG floatingp oint condition code to a SPARC
663/// FCC condition.
664static SPCC::CondCodes FPCondCCodeToFCC(ISD::CondCode CC) {
665 switch (CC) {
Torok Edwinc23197a2009-07-14 16:55:14 +0000666 default: llvm_unreachable("Unknown fp condition code!");
Chris Lattnerd23405e2008-03-17 03:21:36 +0000667 case ISD::SETEQ:
668 case ISD::SETOEQ: return SPCC::FCC_E;
669 case ISD::SETNE:
670 case ISD::SETUNE: return SPCC::FCC_NE;
671 case ISD::SETLT:
672 case ISD::SETOLT: return SPCC::FCC_L;
673 case ISD::SETGT:
674 case ISD::SETOGT: return SPCC::FCC_G;
675 case ISD::SETLE:
676 case ISD::SETOLE: return SPCC::FCC_LE;
677 case ISD::SETGE:
678 case ISD::SETOGE: return SPCC::FCC_GE;
679 case ISD::SETULT: return SPCC::FCC_UL;
680 case ISD::SETULE: return SPCC::FCC_ULE;
681 case ISD::SETUGT: return SPCC::FCC_UG;
682 case ISD::SETUGE: return SPCC::FCC_UGE;
683 case ISD::SETUO: return SPCC::FCC_U;
684 case ISD::SETO: return SPCC::FCC_O;
685 case ISD::SETONE: return SPCC::FCC_LG;
686 case ISD::SETUEQ: return SPCC::FCC_UE;
687 }
688}
689
Chris Lattnerd23405e2008-03-17 03:21:36 +0000690SparcTargetLowering::SparcTargetLowering(TargetMachine &TM)
Chris Lattner5277b222009-08-08 20:43:12 +0000691 : TargetLowering(TM, new TargetLoweringObjectFileELF()) {
Anton Korobeynikov53835702008-10-10 20:27:31 +0000692
Chris Lattnerd23405e2008-03-17 03:21:36 +0000693 // Set up the register classes.
Owen Anderson825b72b2009-08-11 20:47:22 +0000694 addRegisterClass(MVT::i32, SP::IntRegsRegisterClass);
695 addRegisterClass(MVT::f32, SP::FPRegsRegisterClass);
696 addRegisterClass(MVT::f64, SP::DFPRegsRegisterClass);
Chris Lattnerd23405e2008-03-17 03:21:36 +0000697
698 // Turn FP extload into load/fextend
Owen Anderson825b72b2009-08-11 20:47:22 +0000699 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
Chris Lattnerd23405e2008-03-17 03:21:36 +0000700 // Sparc doesn't have i1 sign extending load
Owen Anderson825b72b2009-08-11 20:47:22 +0000701 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
Chris Lattnerd23405e2008-03-17 03:21:36 +0000702 // Turn FP truncstore into trunc + store.
Owen Anderson825b72b2009-08-11 20:47:22 +0000703 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
Chris Lattnerd23405e2008-03-17 03:21:36 +0000704
705 // Custom legalize GlobalAddress nodes into LO/HI parts.
Owen Anderson825b72b2009-08-11 20:47:22 +0000706 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
707 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
708 setOperationAction(ISD::ConstantPool , MVT::i32, Custom);
Anton Korobeynikov53835702008-10-10 20:27:31 +0000709
Chris Lattnerd23405e2008-03-17 03:21:36 +0000710 // Sparc doesn't have sext_inreg, replace them with shl/sra
Owen Anderson825b72b2009-08-11 20:47:22 +0000711 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
712 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand);
713 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
Chris Lattnerd23405e2008-03-17 03:21:36 +0000714
715 // Sparc has no REM or DIVREM operations.
Owen Anderson825b72b2009-08-11 20:47:22 +0000716 setOperationAction(ISD::UREM, MVT::i32, Expand);
717 setOperationAction(ISD::SREM, MVT::i32, Expand);
718 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
719 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
Chris Lattnerd23405e2008-03-17 03:21:36 +0000720
721 // Custom expand fp<->sint
Owen Anderson825b72b2009-08-11 20:47:22 +0000722 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
723 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
Chris Lattnerd23405e2008-03-17 03:21:36 +0000724
725 // Expand fp<->uint
Owen Anderson825b72b2009-08-11 20:47:22 +0000726 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
727 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
Anton Korobeynikov53835702008-10-10 20:27:31 +0000728
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000729 setOperationAction(ISD::BITCAST, MVT::f32, Expand);
730 setOperationAction(ISD::BITCAST, MVT::i32, Expand);
Anton Korobeynikov53835702008-10-10 20:27:31 +0000731
Chris Lattnerd23405e2008-03-17 03:21:36 +0000732 // Sparc has no select or setcc: expand to SELECT_CC.
Owen Anderson825b72b2009-08-11 20:47:22 +0000733 setOperationAction(ISD::SELECT, MVT::i32, Expand);
734 setOperationAction(ISD::SELECT, MVT::f32, Expand);
735 setOperationAction(ISD::SELECT, MVT::f64, Expand);
736 setOperationAction(ISD::SETCC, MVT::i32, Expand);
737 setOperationAction(ISD::SETCC, MVT::f32, Expand);
738 setOperationAction(ISD::SETCC, MVT::f64, Expand);
Anton Korobeynikov53835702008-10-10 20:27:31 +0000739
Chris Lattnerd23405e2008-03-17 03:21:36 +0000740 // Sparc doesn't have BRCOND either, it has BR_CC.
Owen Anderson825b72b2009-08-11 20:47:22 +0000741 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
742 setOperationAction(ISD::BRIND, MVT::Other, Expand);
743 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
744 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
745 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
746 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
Anton Korobeynikov53835702008-10-10 20:27:31 +0000747
Owen Anderson825b72b2009-08-11 20:47:22 +0000748 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
749 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
750 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
Anton Korobeynikov53835702008-10-10 20:27:31 +0000751
Chris Lattnerd23405e2008-03-17 03:21:36 +0000752 // SPARC has no intrinsics for these particular operations.
Owen Anderson825b72b2009-08-11 20:47:22 +0000753 setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
Chris Lattnerd23405e2008-03-17 03:21:36 +0000754
Owen Anderson825b72b2009-08-11 20:47:22 +0000755 setOperationAction(ISD::FSIN , MVT::f64, Expand);
756 setOperationAction(ISD::FCOS , MVT::f64, Expand);
757 setOperationAction(ISD::FREM , MVT::f64, Expand);
758 setOperationAction(ISD::FSIN , MVT::f32, Expand);
759 setOperationAction(ISD::FCOS , MVT::f32, Expand);
760 setOperationAction(ISD::FREM , MVT::f32, Expand);
761 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
762 setOperationAction(ISD::CTTZ , MVT::i32, Expand);
763 setOperationAction(ISD::CTLZ , MVT::i32, Expand);
764 setOperationAction(ISD::ROTL , MVT::i32, Expand);
765 setOperationAction(ISD::ROTR , MVT::i32, Expand);
766 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
767 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
768 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
769 setOperationAction(ISD::FPOW , MVT::f64, Expand);
770 setOperationAction(ISD::FPOW , MVT::f32, Expand);
Chris Lattnerd23405e2008-03-17 03:21:36 +0000771
Owen Anderson825b72b2009-08-11 20:47:22 +0000772 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
773 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
774 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
Chris Lattnerd23405e2008-03-17 03:21:36 +0000775
776 // FIXME: Sparc provides these multiplies, but we don't have them yet.
Owen Anderson825b72b2009-08-11 20:47:22 +0000777 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
778 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
Anton Korobeynikov53835702008-10-10 20:27:31 +0000779
Owen Anderson825b72b2009-08-11 20:47:22 +0000780 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
Chris Lattnerd23405e2008-03-17 03:21:36 +0000781
Chris Lattnerd23405e2008-03-17 03:21:36 +0000782 // VASTART needs to be custom lowered to use the VarArgsFrameIndex.
Owen Anderson825b72b2009-08-11 20:47:22 +0000783 setOperationAction(ISD::VASTART , MVT::Other, Custom);
Chris Lattnerd23405e2008-03-17 03:21:36 +0000784 // VAARG needs to be lowered to not do unaligned accesses for doubles.
Owen Anderson825b72b2009-08-11 20:47:22 +0000785 setOperationAction(ISD::VAARG , MVT::Other, Custom);
Anton Korobeynikov53835702008-10-10 20:27:31 +0000786
Chris Lattnerd23405e2008-03-17 03:21:36 +0000787 // Use the default implementation.
Owen Anderson825b72b2009-08-11 20:47:22 +0000788 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
789 setOperationAction(ISD::VAEND , MVT::Other, Expand);
790 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
791 setOperationAction(ISD::STACKRESTORE , MVT::Other, Expand);
792 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom);
Chris Lattnerd23405e2008-03-17 03:21:36 +0000793
794 // No debug info support yet.
Owen Anderson825b72b2009-08-11 20:47:22 +0000795 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
Anton Korobeynikov53835702008-10-10 20:27:31 +0000796
Chris Lattnerd23405e2008-03-17 03:21:36 +0000797 setStackPointerRegisterToSaveRestore(SP::O6);
798
799 if (TM.getSubtarget<SparcSubtarget>().isV9())
Owen Anderson825b72b2009-08-11 20:47:22 +0000800 setOperationAction(ISD::CTPOP, MVT::i32, Legal);
Anton Korobeynikov53835702008-10-10 20:27:31 +0000801
Chris Lattnerd23405e2008-03-17 03:21:36 +0000802 computeRegisterProperties();
803}
804
805const char *SparcTargetLowering::getTargetNodeName(unsigned Opcode) const {
806 switch (Opcode) {
807 default: return 0;
808 case SPISD::CMPICC: return "SPISD::CMPICC";
809 case SPISD::CMPFCC: return "SPISD::CMPFCC";
810 case SPISD::BRICC: return "SPISD::BRICC";
811 case SPISD::BRFCC: return "SPISD::BRFCC";
812 case SPISD::SELECT_ICC: return "SPISD::SELECT_ICC";
813 case SPISD::SELECT_FCC: return "SPISD::SELECT_FCC";
814 case SPISD::Hi: return "SPISD::Hi";
815 case SPISD::Lo: return "SPISD::Lo";
816 case SPISD::FTOI: return "SPISD::FTOI";
817 case SPISD::ITOF: return "SPISD::ITOF";
818 case SPISD::CALL: return "SPISD::CALL";
819 case SPISD::RET_FLAG: return "SPISD::RET_FLAG";
Venkatraman Govindaraju860b64c2011-01-12 05:08:36 +0000820 case SPISD::GLOBAL_BASE_REG: return "SPISD::GLOBAL_BASE_REG";
Venkatraman Govindarajufc3faa72011-01-21 22:00:00 +0000821 case SPISD::FLUSHW: return "SPISD::FLUSHW";
Chris Lattnerd23405e2008-03-17 03:21:36 +0000822 }
823}
824
825/// isMaskedValueZeroForTargetNode - Return true if 'Op & Mask' is known to
826/// be zero. Op is expected to be a target specific node. Used by DAG
827/// combiner.
Dan Gohman475871a2008-07-27 21:46:04 +0000828void SparcTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
Chris Lattnerd23405e2008-03-17 03:21:36 +0000829 const APInt &Mask,
Anton Korobeynikov53835702008-10-10 20:27:31 +0000830 APInt &KnownZero,
Chris Lattnerd23405e2008-03-17 03:21:36 +0000831 APInt &KnownOne,
832 const SelectionDAG &DAG,
833 unsigned Depth) const {
834 APInt KnownZero2, KnownOne2;
835 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); // Don't know anything.
Anton Korobeynikov53835702008-10-10 20:27:31 +0000836
Chris Lattnerd23405e2008-03-17 03:21:36 +0000837 switch (Op.getOpcode()) {
838 default: break;
839 case SPISD::SELECT_ICC:
840 case SPISD::SELECT_FCC:
841 DAG.ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne,
842 Depth+1);
843 DAG.ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero2, KnownOne2,
844 Depth+1);
Anton Korobeynikov53835702008-10-10 20:27:31 +0000845 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
846 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
847
Chris Lattnerd23405e2008-03-17 03:21:36 +0000848 // Only known if known in both the LHS and RHS.
849 KnownOne &= KnownOne2;
850 KnownZero &= KnownZero2;
851 break;
852 }
853}
854
Chris Lattnerd23405e2008-03-17 03:21:36 +0000855// Look at LHS/RHS/CC and see if they are a lowered setcc instruction. If so
856// set LHS/RHS and SPCC to the LHS/RHS of the setcc and SPCC to the condition.
Dan Gohman475871a2008-07-27 21:46:04 +0000857static void LookThroughSetCC(SDValue &LHS, SDValue &RHS,
Chris Lattnerd23405e2008-03-17 03:21:36 +0000858 ISD::CondCode CC, unsigned &SPCC) {
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +0000859 if (isa<ConstantSDNode>(RHS) &&
Dan Gohmane368b462010-06-18 14:22:04 +0000860 cast<ConstantSDNode>(RHS)->isNullValue() &&
Anton Korobeynikov53835702008-10-10 20:27:31 +0000861 CC == ISD::SETNE &&
Chris Lattnerd23405e2008-03-17 03:21:36 +0000862 ((LHS.getOpcode() == SPISD::SELECT_ICC &&
863 LHS.getOperand(3).getOpcode() == SPISD::CMPICC) ||
864 (LHS.getOpcode() == SPISD::SELECT_FCC &&
865 LHS.getOperand(3).getOpcode() == SPISD::CMPFCC)) &&
866 isa<ConstantSDNode>(LHS.getOperand(0)) &&
867 isa<ConstantSDNode>(LHS.getOperand(1)) &&
Dan Gohmane368b462010-06-18 14:22:04 +0000868 cast<ConstantSDNode>(LHS.getOperand(0))->isOne() &&
869 cast<ConstantSDNode>(LHS.getOperand(1))->isNullValue()) {
Dan Gohman475871a2008-07-27 21:46:04 +0000870 SDValue CMPCC = LHS.getOperand(3);
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +0000871 SPCC = cast<ConstantSDNode>(LHS.getOperand(2))->getZExtValue();
Chris Lattnerd23405e2008-03-17 03:21:36 +0000872 LHS = CMPCC.getOperand(0);
873 RHS = CMPCC.getOperand(1);
874 }
875}
876
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000877SDValue SparcTargetLowering::LowerGlobalAddress(SDValue Op,
Dan Gohmand858e902010-04-17 15:26:15 +0000878 SelectionDAG &DAG) const {
Dan Gohman46510a72010-04-15 01:51:59 +0000879 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
Dale Johannesende064702009-02-06 21:50:26 +0000880 // FIXME there isn't really any debug info here
881 DebugLoc dl = Op.getDebugLoc();
Devang Patel0d881da2010-07-06 22:08:15 +0000882 SDValue GA = DAG.getTargetGlobalAddress(GV, dl, MVT::i32);
Owen Anderson825b72b2009-08-11 20:47:22 +0000883 SDValue Hi = DAG.getNode(SPISD::Hi, dl, MVT::i32, GA);
884 SDValue Lo = DAG.getNode(SPISD::Lo, dl, MVT::i32, GA);
Chris Lattnerdb486a62009-09-15 17:46:24 +0000885
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000886 if (getTargetMachine().getRelocationModel() != Reloc::PIC_)
Chris Lattnerdb486a62009-09-15 17:46:24 +0000887 return DAG.getNode(ISD::ADD, dl, MVT::i32, Lo, Hi);
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000888
Chris Lattnerdb486a62009-09-15 17:46:24 +0000889 SDValue GlobalBase = DAG.getNode(SPISD::GLOBAL_BASE_REG, dl,
890 getPointerTy());
891 SDValue RelAddr = DAG.getNode(ISD::ADD, dl, MVT::i32, Lo, Hi);
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000892 SDValue AbsAddr = DAG.getNode(ISD::ADD, dl, MVT::i32,
Chris Lattnerdb486a62009-09-15 17:46:24 +0000893 GlobalBase, RelAddr);
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000894 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
Chris Lattnerd1c24ed2010-09-21 06:44:06 +0000895 AbsAddr, MachinePointerInfo(), false, false, 0);
Chris Lattnerd23405e2008-03-17 03:21:36 +0000896}
897
Chris Lattnerdb486a62009-09-15 17:46:24 +0000898SDValue SparcTargetLowering::LowerConstantPool(SDValue Op,
Dan Gohmand858e902010-04-17 15:26:15 +0000899 SelectionDAG &DAG) const {
Chris Lattnerd23405e2008-03-17 03:21:36 +0000900 ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op);
Dale Johannesende064702009-02-06 21:50:26 +0000901 // FIXME there isn't really any debug info here
902 DebugLoc dl = Op.getDebugLoc();
Dan Gohman46510a72010-04-15 01:51:59 +0000903 const Constant *C = N->getConstVal();
Owen Anderson825b72b2009-08-11 20:47:22 +0000904 SDValue CP = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment());
905 SDValue Hi = DAG.getNode(SPISD::Hi, dl, MVT::i32, CP);
906 SDValue Lo = DAG.getNode(SPISD::Lo, dl, MVT::i32, CP);
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000907 if (getTargetMachine().getRelocationModel() != Reloc::PIC_)
Chris Lattnerdb486a62009-09-15 17:46:24 +0000908 return DAG.getNode(ISD::ADD, dl, MVT::i32, Lo, Hi);
909
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000910 SDValue GlobalBase = DAG.getNode(SPISD::GLOBAL_BASE_REG, dl,
Chris Lattnerdb486a62009-09-15 17:46:24 +0000911 getPointerTy());
912 SDValue RelAddr = DAG.getNode(ISD::ADD, dl, MVT::i32, Lo, Hi);
913 SDValue AbsAddr = DAG.getNode(ISD::ADD, dl, MVT::i32,
914 GlobalBase, RelAddr);
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000915 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
Chris Lattnerd1c24ed2010-09-21 06:44:06 +0000916 AbsAddr, MachinePointerInfo(), false, false, 0);
Chris Lattnerd23405e2008-03-17 03:21:36 +0000917}
918
Dan Gohman475871a2008-07-27 21:46:04 +0000919static SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) {
Dale Johannesenb300d2a2009-02-07 00:55:49 +0000920 DebugLoc dl = Op.getDebugLoc();
Chris Lattnerd23405e2008-03-17 03:21:36 +0000921 // Convert the fp value to integer in an FP register.
Owen Anderson825b72b2009-08-11 20:47:22 +0000922 assert(Op.getValueType() == MVT::i32);
923 Op = DAG.getNode(SPISD::FTOI, dl, MVT::f32, Op.getOperand(0));
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000924 return DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
Chris Lattnerd23405e2008-03-17 03:21:36 +0000925}
926
Dan Gohman475871a2008-07-27 21:46:04 +0000927static SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
Dale Johannesenb300d2a2009-02-07 00:55:49 +0000928 DebugLoc dl = Op.getDebugLoc();
Owen Anderson825b72b2009-08-11 20:47:22 +0000929 assert(Op.getOperand(0).getValueType() == MVT::i32);
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000930 SDValue Tmp = DAG.getNode(ISD::BITCAST, dl, MVT::f32, Op.getOperand(0));
Chris Lattnerd23405e2008-03-17 03:21:36 +0000931 // Convert the int value to FP in an FP register.
Dale Johannesenb300d2a2009-02-07 00:55:49 +0000932 return DAG.getNode(SPISD::ITOF, dl, Op.getValueType(), Tmp);
Chris Lattnerd23405e2008-03-17 03:21:36 +0000933}
934
Dan Gohman475871a2008-07-27 21:46:04 +0000935static SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) {
936 SDValue Chain = Op.getOperand(0);
Chris Lattnerd23405e2008-03-17 03:21:36 +0000937 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
Dan Gohman475871a2008-07-27 21:46:04 +0000938 SDValue LHS = Op.getOperand(2);
939 SDValue RHS = Op.getOperand(3);
940 SDValue Dest = Op.getOperand(4);
Dale Johannesen3484c092009-02-05 22:07:54 +0000941 DebugLoc dl = Op.getDebugLoc();
Chris Lattnerd23405e2008-03-17 03:21:36 +0000942 unsigned Opc, SPCC = ~0U;
Anton Korobeynikov53835702008-10-10 20:27:31 +0000943
Chris Lattnerd23405e2008-03-17 03:21:36 +0000944 // If this is a br_cc of a "setcc", and if the setcc got lowered into
945 // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values.
946 LookThroughSetCC(LHS, RHS, CC, SPCC);
Anton Korobeynikov53835702008-10-10 20:27:31 +0000947
Chris Lattnerd23405e2008-03-17 03:21:36 +0000948 // Get the condition flag.
Dan Gohman475871a2008-07-27 21:46:04 +0000949 SDValue CompareFlag;
Owen Anderson825b72b2009-08-11 20:47:22 +0000950 if (LHS.getValueType() == MVT::i32) {
Owen Andersone50ed302009-08-10 22:56:29 +0000951 std::vector<EVT> VTs;
Owen Anderson825b72b2009-08-11 20:47:22 +0000952 VTs.push_back(MVT::i32);
Chris Lattnerf1b4eaf2010-12-21 02:38:05 +0000953 VTs.push_back(MVT::Glue);
Dan Gohman475871a2008-07-27 21:46:04 +0000954 SDValue Ops[2] = { LHS, RHS };
Dale Johannesen3484c092009-02-05 22:07:54 +0000955 CompareFlag = DAG.getNode(SPISD::CMPICC, dl, VTs, Ops, 2).getValue(1);
Chris Lattnerd23405e2008-03-17 03:21:36 +0000956 if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC);
957 Opc = SPISD::BRICC;
958 } else {
Chris Lattnerf1b4eaf2010-12-21 02:38:05 +0000959 CompareFlag = DAG.getNode(SPISD::CMPFCC, dl, MVT::Glue, LHS, RHS);
Chris Lattnerd23405e2008-03-17 03:21:36 +0000960 if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
961 Opc = SPISD::BRFCC;
962 }
Owen Anderson825b72b2009-08-11 20:47:22 +0000963 return DAG.getNode(Opc, dl, MVT::Other, Chain, Dest,
964 DAG.getConstant(SPCC, MVT::i32), CompareFlag);
Chris Lattnerd23405e2008-03-17 03:21:36 +0000965}
966
Dan Gohman475871a2008-07-27 21:46:04 +0000967static SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) {
968 SDValue LHS = Op.getOperand(0);
969 SDValue RHS = Op.getOperand(1);
Chris Lattnerd23405e2008-03-17 03:21:36 +0000970 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
Dan Gohman475871a2008-07-27 21:46:04 +0000971 SDValue TrueVal = Op.getOperand(2);
972 SDValue FalseVal = Op.getOperand(3);
Dale Johannesen3484c092009-02-05 22:07:54 +0000973 DebugLoc dl = Op.getDebugLoc();
Chris Lattnerd23405e2008-03-17 03:21:36 +0000974 unsigned Opc, SPCC = ~0U;
Anton Korobeynikov53835702008-10-10 20:27:31 +0000975
Chris Lattnerd23405e2008-03-17 03:21:36 +0000976 // If this is a select_cc of a "setcc", and if the setcc got lowered into
977 // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values.
978 LookThroughSetCC(LHS, RHS, CC, SPCC);
Anton Korobeynikov53835702008-10-10 20:27:31 +0000979
Dan Gohman475871a2008-07-27 21:46:04 +0000980 SDValue CompareFlag;
Owen Anderson825b72b2009-08-11 20:47:22 +0000981 if (LHS.getValueType() == MVT::i32) {
Owen Andersone50ed302009-08-10 22:56:29 +0000982 std::vector<EVT> VTs;
Chris Lattnerd23405e2008-03-17 03:21:36 +0000983 VTs.push_back(LHS.getValueType()); // subcc returns a value
Chris Lattnerf1b4eaf2010-12-21 02:38:05 +0000984 VTs.push_back(MVT::Glue);
Dan Gohman475871a2008-07-27 21:46:04 +0000985 SDValue Ops[2] = { LHS, RHS };
Dale Johannesen3484c092009-02-05 22:07:54 +0000986 CompareFlag = DAG.getNode(SPISD::CMPICC, dl, VTs, Ops, 2).getValue(1);
Chris Lattnerd23405e2008-03-17 03:21:36 +0000987 Opc = SPISD::SELECT_ICC;
988 if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC);
989 } else {
Chris Lattnerf1b4eaf2010-12-21 02:38:05 +0000990 CompareFlag = DAG.getNode(SPISD::CMPFCC, dl, MVT::Glue, LHS, RHS);
Chris Lattnerd23405e2008-03-17 03:21:36 +0000991 Opc = SPISD::SELECT_FCC;
992 if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
993 }
Dale Johannesen3484c092009-02-05 22:07:54 +0000994 return DAG.getNode(Opc, dl, TrueVal.getValueType(), TrueVal, FalseVal,
Owen Anderson825b72b2009-08-11 20:47:22 +0000995 DAG.getConstant(SPCC, MVT::i32), CompareFlag);
Chris Lattnerd23405e2008-03-17 03:21:36 +0000996}
997
Dan Gohman475871a2008-07-27 21:46:04 +0000998static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG,
Dan Gohmand858e902010-04-17 15:26:15 +0000999 const SparcTargetLowering &TLI) {
Dan Gohman1e93df62010-04-17 14:41:14 +00001000 MachineFunction &MF = DAG.getMachineFunction();
1001 SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>();
1002
Chris Lattnerd23405e2008-03-17 03:21:36 +00001003 // vastart just stores the address of the VarArgsFrameIndex slot into the
1004 // memory location argument.
Dale Johannesen6f38cb62009-02-07 19:59:05 +00001005 DebugLoc dl = Op.getDebugLoc();
Dan Gohman1e93df62010-04-17 14:41:14 +00001006 SDValue Offset =
1007 DAG.getNode(ISD::ADD, dl, MVT::i32,
1008 DAG.getRegister(SP::I6, MVT::i32),
1009 DAG.getConstant(FuncInfo->getVarArgsFrameOffset(),
1010 MVT::i32));
Chris Lattnerd23405e2008-03-17 03:21:36 +00001011 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
Chris Lattner6229d0a2010-09-21 18:41:36 +00001012 return DAG.getStore(Op.getOperand(0), dl, Offset, Op.getOperand(1),
1013 MachinePointerInfo(SV), false, false, 0);
Chris Lattnerd23405e2008-03-17 03:21:36 +00001014}
1015
Dan Gohman475871a2008-07-27 21:46:04 +00001016static SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) {
Gabor Greifba36cb52008-08-28 21:40:38 +00001017 SDNode *Node = Op.getNode();
Owen Andersone50ed302009-08-10 22:56:29 +00001018 EVT VT = Node->getValueType(0);
Dan Gohman475871a2008-07-27 21:46:04 +00001019 SDValue InChain = Node->getOperand(0);
1020 SDValue VAListPtr = Node->getOperand(1);
Chris Lattnerd23405e2008-03-17 03:21:36 +00001021 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
Dale Johannesen33c960f2009-02-04 20:06:27 +00001022 DebugLoc dl = Node->getDebugLoc();
Chris Lattnerd1c24ed2010-09-21 06:44:06 +00001023 SDValue VAList = DAG.getLoad(MVT::i32, dl, InChain, VAListPtr,
1024 MachinePointerInfo(SV), false, false, 0);
Chris Lattnerd23405e2008-03-17 03:21:36 +00001025 // Increment the pointer, VAList, to the next vaarg
Owen Anderson825b72b2009-08-11 20:47:22 +00001026 SDValue NextPtr = DAG.getNode(ISD::ADD, dl, MVT::i32, VAList,
Duncan Sands83ec4b62008-06-06 12:08:01 +00001027 DAG.getConstant(VT.getSizeInBits()/8,
Owen Anderson825b72b2009-08-11 20:47:22 +00001028 MVT::i32));
Chris Lattnerd23405e2008-03-17 03:21:36 +00001029 // Store the incremented VAList to the legalized pointer
Dale Johannesen33c960f2009-02-04 20:06:27 +00001030 InChain = DAG.getStore(VAList.getValue(1), dl, NextPtr,
Chris Lattner6229d0a2010-09-21 18:41:36 +00001031 VAListPtr, MachinePointerInfo(SV), false, false, 0);
Chris Lattnerd23405e2008-03-17 03:21:36 +00001032 // Load the actual argument out of the pointer VAList, unless this is an
1033 // f64 load.
Owen Anderson825b72b2009-08-11 20:47:22 +00001034 if (VT != MVT::f64)
Chris Lattnerd1c24ed2010-09-21 06:44:06 +00001035 return DAG.getLoad(VT, dl, InChain, VAList, MachinePointerInfo(),
1036 false, false, 0);
Anton Korobeynikov53835702008-10-10 20:27:31 +00001037
Chris Lattnerd23405e2008-03-17 03:21:36 +00001038 // Otherwise, load it as i64, then do a bitconvert.
Chris Lattnerd1c24ed2010-09-21 06:44:06 +00001039 SDValue V = DAG.getLoad(MVT::i64, dl, InChain, VAList, MachinePointerInfo(),
David Greene54a7aa82010-02-15 16:57:02 +00001040 false, false, 0);
Anton Korobeynikov53835702008-10-10 20:27:31 +00001041
Chris Lattnerd23405e2008-03-17 03:21:36 +00001042 // Bit-Convert the value to f64.
Dan Gohman475871a2008-07-27 21:46:04 +00001043 SDValue Ops[2] = {
Wesley Peckbf17cfa2010-11-23 03:31:01 +00001044 DAG.getNode(ISD::BITCAST, dl, MVT::f64, V),
Chris Lattnerd23405e2008-03-17 03:21:36 +00001045 V.getValue(1)
1046 };
Dale Johannesen33c960f2009-02-04 20:06:27 +00001047 return DAG.getMergeValues(Ops, 2, dl);
Chris Lattnerd23405e2008-03-17 03:21:36 +00001048}
1049
Dan Gohman475871a2008-07-27 21:46:04 +00001050static SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) {
1051 SDValue Chain = Op.getOperand(0); // Legalize the chain.
1052 SDValue Size = Op.getOperand(1); // Legalize the size.
Dale Johannesena05dca42009-02-04 23:02:30 +00001053 DebugLoc dl = Op.getDebugLoc();
Anton Korobeynikov53835702008-10-10 20:27:31 +00001054
Chris Lattnerd23405e2008-03-17 03:21:36 +00001055 unsigned SPReg = SP::O6;
Owen Anderson825b72b2009-08-11 20:47:22 +00001056 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, MVT::i32);
1057 SDValue NewSP = DAG.getNode(ISD::SUB, dl, MVT::i32, SP, Size); // Value
Dale Johannesena05dca42009-02-04 23:02:30 +00001058 Chain = DAG.getCopyToReg(SP.getValue(1), dl, SPReg, NewSP); // Output chain
Anton Korobeynikov53835702008-10-10 20:27:31 +00001059
Chris Lattnerd23405e2008-03-17 03:21:36 +00001060 // The resultant pointer is actually 16 words from the bottom of the stack,
1061 // to provide a register spill area.
Owen Anderson825b72b2009-08-11 20:47:22 +00001062 SDValue NewVal = DAG.getNode(ISD::ADD, dl, MVT::i32, NewSP,
1063 DAG.getConstant(96, MVT::i32));
Dan Gohman475871a2008-07-27 21:46:04 +00001064 SDValue Ops[2] = { NewVal, Chain };
Dale Johannesena05dca42009-02-04 23:02:30 +00001065 return DAG.getMergeValues(Ops, 2, dl);
Chris Lattnerd23405e2008-03-17 03:21:36 +00001066}
1067
Chris Lattnerd23405e2008-03-17 03:21:36 +00001068
Venkatraman Govindarajufc3faa72011-01-21 22:00:00 +00001069static SDValue getFLUSHW(SDValue Op, SelectionDAG &DAG) {
Venkatraman Govindaraju860b64c2011-01-12 05:08:36 +00001070 DebugLoc dl = Op.getDebugLoc();
Venkatraman Govindarajufc3faa72011-01-21 22:00:00 +00001071 SDValue Chain = DAG.getNode(SPISD::FLUSHW,
Venkatraman Govindaraju860b64c2011-01-12 05:08:36 +00001072 dl, MVT::Other, DAG.getEntryNode());
1073 return Chain;
1074}
1075
1076static SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) {
1077 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
1078 MFI->setFrameAddressIsTaken(true);
1079
1080 EVT VT = Op.getValueType();
1081 DebugLoc dl = Op.getDebugLoc();
1082 unsigned FrameReg = SP::I6;
1083
1084 uint64_t depth = Op.getConstantOperandVal(0);
1085
1086 SDValue FrameAddr;
Venkatraman Govindarajufc3faa72011-01-21 22:00:00 +00001087 if (depth == 0)
Venkatraman Govindaraju860b64c2011-01-12 05:08:36 +00001088 FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
1089 else {
1090 // flush first to make sure the windowed registers' values are in stack
Venkatraman Govindarajufc3faa72011-01-21 22:00:00 +00001091 SDValue Chain = getFLUSHW(Op, DAG);
Venkatraman Govindaraju860b64c2011-01-12 05:08:36 +00001092 FrameAddr = DAG.getCopyFromReg(Chain, dl, FrameReg, VT);
Venkatraman Govindarajufc3faa72011-01-21 22:00:00 +00001093
Venkatraman Govindaraju860b64c2011-01-12 05:08:36 +00001094 for (uint64_t i = 0; i != depth; ++i) {
Venkatraman Govindarajufc3faa72011-01-21 22:00:00 +00001095 SDValue Ptr = DAG.getNode(ISD::ADD,
Venkatraman Govindaraju860b64c2011-01-12 05:08:36 +00001096 dl, MVT::i32,
1097 FrameAddr, DAG.getIntPtrConstant(56));
Venkatraman Govindarajufc3faa72011-01-21 22:00:00 +00001098 FrameAddr = DAG.getLoad(MVT::i32, dl,
1099 Chain,
Venkatraman Govindaraju860b64c2011-01-12 05:08:36 +00001100 Ptr,
1101 MachinePointerInfo(), false, false, 0);
1102 }
1103 }
1104 return FrameAddr;
1105}
1106
1107static SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) {
1108 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
1109 MFI->setReturnAddressIsTaken(true);
1110
1111 EVT VT = Op.getValueType();
1112 DebugLoc dl = Op.getDebugLoc();
1113 unsigned RetReg = SP::I7;
1114
1115 uint64_t depth = Op.getConstantOperandVal(0);
1116
1117 SDValue RetAddr;
Venkatraman Govindarajufc3faa72011-01-21 22:00:00 +00001118 if (depth == 0)
Venkatraman Govindaraju860b64c2011-01-12 05:08:36 +00001119 RetAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, RetReg, VT);
1120 else {
1121 // flush first to make sure the windowed registers' values are in stack
Venkatraman Govindarajufc3faa72011-01-21 22:00:00 +00001122 SDValue Chain = getFLUSHW(Op, DAG);
Venkatraman Govindaraju860b64c2011-01-12 05:08:36 +00001123 RetAddr = DAG.getCopyFromReg(Chain, dl, SP::I6, VT);
Venkatraman Govindarajufc3faa72011-01-21 22:00:00 +00001124
Venkatraman Govindaraju860b64c2011-01-12 05:08:36 +00001125 for (uint64_t i = 0; i != depth; ++i) {
Venkatraman Govindarajufc3faa72011-01-21 22:00:00 +00001126 SDValue Ptr = DAG.getNode(ISD::ADD,
Venkatraman Govindaraju860b64c2011-01-12 05:08:36 +00001127 dl, MVT::i32,
Venkatraman Govindarajufc3faa72011-01-21 22:00:00 +00001128 RetAddr,
Venkatraman Govindaraju860b64c2011-01-12 05:08:36 +00001129 DAG.getIntPtrConstant((i == depth-1)?60:56));
Venkatraman Govindarajufc3faa72011-01-21 22:00:00 +00001130 RetAddr = DAG.getLoad(MVT::i32, dl,
1131 Chain,
Venkatraman Govindaraju860b64c2011-01-12 05:08:36 +00001132 Ptr,
1133 MachinePointerInfo(), false, false, 0);
1134 }
1135 }
1136 return RetAddr;
1137}
1138
Dan Gohman475871a2008-07-27 21:46:04 +00001139SDValue SparcTargetLowering::
Dan Gohmand858e902010-04-17 15:26:15 +00001140LowerOperation(SDValue Op, SelectionDAG &DAG) const {
Chris Lattnerd23405e2008-03-17 03:21:36 +00001141 switch (Op.getOpcode()) {
Torok Edwinc23197a2009-07-14 16:55:14 +00001142 default: llvm_unreachable("Should not custom lower this!");
Venkatraman Govindaraju860b64c2011-01-12 05:08:36 +00001143 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
1144 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
Chris Lattnerd23405e2008-03-17 03:21:36 +00001145 case ISD::GlobalTLSAddress:
Torok Edwinc23197a2009-07-14 16:55:14 +00001146 llvm_unreachable("TLS not implemented for Sparc.");
Chris Lattnerdb486a62009-09-15 17:46:24 +00001147 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
1148 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
Chris Lattnerd23405e2008-03-17 03:21:36 +00001149 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
1150 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
1151 case ISD::BR_CC: return LowerBR_CC(Op, DAG);
1152 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
1153 case ISD::VASTART: return LowerVASTART(Op, DAG, *this);
1154 case ISD::VAARG: return LowerVAARG(Op, DAG);
1155 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
Chris Lattnerd23405e2008-03-17 03:21:36 +00001156 }
1157}
1158
1159MachineBasicBlock *
1160SparcTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
Dan Gohmanaf1d8ca2010-05-01 00:01:06 +00001161 MachineBasicBlock *BB) const {
Chris Lattnerd23405e2008-03-17 03:21:36 +00001162 const TargetInstrInfo &TII = *getTargetMachine().getInstrInfo();
1163 unsigned BROpcode;
1164 unsigned CC;
Dale Johannesend552eee2009-02-13 02:31:35 +00001165 DebugLoc dl = MI->getDebugLoc();
Chris Lattnerd23405e2008-03-17 03:21:36 +00001166 // Figure out the conditional branch opcode to use for this select_cc.
1167 switch (MI->getOpcode()) {
Torok Edwinc23197a2009-07-14 16:55:14 +00001168 default: llvm_unreachable("Unknown SELECT_CC!");
Chris Lattnerd23405e2008-03-17 03:21:36 +00001169 case SP::SELECT_CC_Int_ICC:
1170 case SP::SELECT_CC_FP_ICC:
1171 case SP::SELECT_CC_DFP_ICC:
1172 BROpcode = SP::BCOND;
1173 break;
1174 case SP::SELECT_CC_Int_FCC:
1175 case SP::SELECT_CC_FP_FCC:
1176 case SP::SELECT_CC_DFP_FCC:
1177 BROpcode = SP::FBCOND;
1178 break;
1179 }
1180
1181 CC = (SPCC::CondCodes)MI->getOperand(3).getImm();
Anton Korobeynikov53835702008-10-10 20:27:31 +00001182
Chris Lattnerd23405e2008-03-17 03:21:36 +00001183 // To "insert" a SELECT_CC instruction, we actually have to insert the diamond
1184 // control-flow pattern. The incoming instruction knows the destination vreg
1185 // to set, the condition code register to branch on, the true/false values to
1186 // select between, and a branch opcode to use.
1187 const BasicBlock *LLVM_BB = BB->getBasicBlock();
Dan Gohman8e5f2c62008-07-07 23:14:23 +00001188 MachineFunction::iterator It = BB;
Chris Lattnerd23405e2008-03-17 03:21:36 +00001189 ++It;
Anton Korobeynikov53835702008-10-10 20:27:31 +00001190
Chris Lattnerd23405e2008-03-17 03:21:36 +00001191 // thisMBB:
1192 // ...
1193 // TrueVal = ...
1194 // [f]bCC copy1MBB
1195 // fallthrough --> copy0MBB
1196 MachineBasicBlock *thisMBB = BB;
Chris Lattnerd23405e2008-03-17 03:21:36 +00001197 MachineFunction *F = BB->getParent();
Dan Gohman8e5f2c62008-07-07 23:14:23 +00001198 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
1199 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
Venkatraman Govindarajuf6612772010-12-28 20:39:17 +00001200 F->insert(It, copy0MBB);
1201 F->insert(It, sinkMBB);
Dan Gohman14152b42010-07-06 20:24:04 +00001202
1203 // Transfer the remainder of BB and its successor edges to sinkMBB.
1204 sinkMBB->splice(sinkMBB->begin(), BB,
1205 llvm::next(MachineBasicBlock::iterator(MI)),
1206 BB->end());
1207 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
1208
1209 // Add the true and fallthrough blocks as its successors.
1210 BB->addSuccessor(copy0MBB);
1211 BB->addSuccessor(sinkMBB);
1212
Dale Johannesend552eee2009-02-13 02:31:35 +00001213 BuildMI(BB, dl, TII.get(BROpcode)).addMBB(sinkMBB).addImm(CC);
Anton Korobeynikov53835702008-10-10 20:27:31 +00001214
Chris Lattnerd23405e2008-03-17 03:21:36 +00001215 // copy0MBB:
1216 // %FalseValue = ...
1217 // # fallthrough to sinkMBB
1218 BB = copy0MBB;
Anton Korobeynikov53835702008-10-10 20:27:31 +00001219
Chris Lattnerd23405e2008-03-17 03:21:36 +00001220 // Update machine-CFG edges
1221 BB->addSuccessor(sinkMBB);
Anton Korobeynikov53835702008-10-10 20:27:31 +00001222
Chris Lattnerd23405e2008-03-17 03:21:36 +00001223 // sinkMBB:
1224 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
1225 // ...
1226 BB = sinkMBB;
Dan Gohman14152b42010-07-06 20:24:04 +00001227 BuildMI(*BB, BB->begin(), dl, TII.get(SP::PHI), MI->getOperand(0).getReg())
Chris Lattnerd23405e2008-03-17 03:21:36 +00001228 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
1229 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB);
Anton Korobeynikov53835702008-10-10 20:27:31 +00001230
Dan Gohman14152b42010-07-06 20:24:04 +00001231 MI->eraseFromParent(); // The pseudo instruction is gone now.
Chris Lattnerd23405e2008-03-17 03:21:36 +00001232 return BB;
1233}
Anton Korobeynikov0eefda12008-10-10 20:28:10 +00001234
1235//===----------------------------------------------------------------------===//
1236// Sparc Inline Assembly Support
1237//===----------------------------------------------------------------------===//
1238
1239/// getConstraintType - Given a constraint letter, return the type of
1240/// constraint it is for this target.
1241SparcTargetLowering::ConstraintType
1242SparcTargetLowering::getConstraintType(const std::string &Constraint) const {
1243 if (Constraint.size() == 1) {
1244 switch (Constraint[0]) {
1245 default: break;
1246 case 'r': return C_RegisterClass;
1247 }
1248 }
1249
1250 return TargetLowering::getConstraintType(Constraint);
1251}
1252
1253std::pair<unsigned, const TargetRegisterClass*>
1254SparcTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
Owen Andersone50ed302009-08-10 22:56:29 +00001255 EVT VT) const {
Anton Korobeynikov0eefda12008-10-10 20:28:10 +00001256 if (Constraint.size() == 1) {
1257 switch (Constraint[0]) {
1258 case 'r':
1259 return std::make_pair(0U, SP::IntRegsRegisterClass);
1260 }
1261 }
1262
1263 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
1264}
1265
1266std::vector<unsigned> SparcTargetLowering::
1267getRegClassForInlineAsmConstraint(const std::string &Constraint,
Owen Andersone50ed302009-08-10 22:56:29 +00001268 EVT VT) const {
Anton Korobeynikov0eefda12008-10-10 20:28:10 +00001269 if (Constraint.size() != 1)
1270 return std::vector<unsigned>();
1271
1272 switch (Constraint[0]) {
1273 default: break;
1274 case 'r':
1275 return make_vector<unsigned>(SP::L0, SP::L1, SP::L2, SP::L3,
1276 SP::L4, SP::L5, SP::L6, SP::L7,
1277 SP::I0, SP::I1, SP::I2, SP::I3,
1278 SP::I4, SP::I5,
1279 SP::O0, SP::O1, SP::O2, SP::O3,
1280 SP::O4, SP::O5, SP::O7, 0);
1281 }
1282
1283 return std::vector<unsigned>();
1284}
Dan Gohman6520e202008-10-18 02:06:02 +00001285
1286bool
1287SparcTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
1288 // The Sparc target isn't yet aware of offsets.
1289 return false;
1290}
Bill Wendling20c568f2009-06-30 22:38:32 +00001291
Bill Wendlingb4202b82009-07-01 18:50:55 +00001292/// getFunctionAlignment - Return the Log2 alignment of this function.
Bill Wendling20c568f2009-06-30 22:38:32 +00001293unsigned SparcTargetLowering::getFunctionAlignment(const Function *) const {
Chris Lattnerdb486a62009-09-15 17:46:24 +00001294 return 2;
Bill Wendling20c568f2009-06-30 22:38:32 +00001295}