| Alkis Evlogimenos | 34d9bc9 | 2004-02-23 23:08:11 +0000 | [diff] [blame] | 1 | //===-- llvm/CodeGen/VirtRegMap.cpp - Virtual Register Map ----------------===// | 
 | 2 | // | 
 | 3 | //                     The LLVM Compiler Infrastructure | 
 | 4 | // | 
 | 5 | // This file was developed by the LLVM research group and is distributed under | 
 | 6 | // the University of Illinois Open Source License. See LICENSE.TXT for details. | 
 | 7 | // | 
 | 8 | //===----------------------------------------------------------------------===// | 
 | 9 | // | 
| Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 10 | // This file implements the VirtRegMap class. | 
 | 11 | // | 
 | 12 | // It also contains implementations of the the Spiller interface, which, given a | 
 | 13 | // virtual register map and a machine function, eliminates all virtual | 
 | 14 | // references by replacing them with physical register references - adding spill | 
| Alkis Evlogimenos | 0d6c5b6 | 2004-02-24 08:58:30 +0000 | [diff] [blame] | 15 | // code as necessary. | 
| Alkis Evlogimenos | 34d9bc9 | 2004-02-23 23:08:11 +0000 | [diff] [blame] | 16 | // | 
 | 17 | //===----------------------------------------------------------------------===// | 
 | 18 |  | 
| Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 19 | #define DEBUG_TYPE "spiller" | 
| Alkis Evlogimenos | 34d9bc9 | 2004-02-23 23:08:11 +0000 | [diff] [blame] | 20 | #include "VirtRegMap.h" | 
| Alkis Evlogimenos | 0d6c5b6 | 2004-02-24 08:58:30 +0000 | [diff] [blame] | 21 | #include "llvm/Function.h" | 
| Alkis Evlogimenos | 34d9bc9 | 2004-02-23 23:08:11 +0000 | [diff] [blame] | 22 | #include "llvm/CodeGen/MachineFrameInfo.h" | 
| Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 23 | #include "llvm/CodeGen/MachineFunction.h" | 
 | 24 | #include "llvm/CodeGen/SSARegMap.h" | 
| Alkis Evlogimenos | 34d9bc9 | 2004-02-23 23:08:11 +0000 | [diff] [blame] | 25 | #include "llvm/Target/TargetMachine.h" | 
| Alkis Evlogimenos | 0d6c5b6 | 2004-02-24 08:58:30 +0000 | [diff] [blame] | 26 | #include "llvm/Target/TargetInstrInfo.h" | 
| Reid Spencer | 551ccae | 2004-09-01 22:55:40 +0000 | [diff] [blame] | 27 | #include "llvm/Support/CommandLine.h" | 
 | 28 | #include "llvm/Support/Debug.h" | 
| Chris Lattner | a4f0b3a | 2006-08-27 12:54:02 +0000 | [diff] [blame] | 29 | #include "llvm/Support/Compiler.h" | 
| Evan Cheng | 957840b | 2007-02-21 02:22:03 +0000 | [diff] [blame] | 30 | #include "llvm/ADT/BitVector.h" | 
| Reid Spencer | 551ccae | 2004-09-01 22:55:40 +0000 | [diff] [blame] | 31 | #include "llvm/ADT/Statistic.h" | 
 | 32 | #include "llvm/ADT/STLExtras.h" | 
| Chris Lattner | 08a4d5a | 2007-01-23 00:59:48 +0000 | [diff] [blame] | 33 | #include "llvm/ADT/SmallSet.h" | 
| Chris Lattner | 27f2916 | 2004-10-26 15:35:58 +0000 | [diff] [blame] | 34 | #include <algorithm> | 
| Alkis Evlogimenos | 34d9bc9 | 2004-02-23 23:08:11 +0000 | [diff] [blame] | 35 | using namespace llvm; | 
 | 36 |  | 
| Chris Lattner | cd3245a | 2006-12-19 22:41:21 +0000 | [diff] [blame] | 37 | STATISTIC(NumSpills, "Number of register spills"); | 
| Evan Cheng | 2638e1a | 2007-03-20 08:13:50 +0000 | [diff] [blame] | 38 | STATISTIC(NumReMats, "Number of re-materialization"); | 
| Chris Lattner | cd3245a | 2006-12-19 22:41:21 +0000 | [diff] [blame] | 39 | STATISTIC(NumStores, "Number of stores added"); | 
 | 40 | STATISTIC(NumLoads , "Number of loads added"); | 
 | 41 | STATISTIC(NumReused, "Number of values reused"); | 
 | 42 | STATISTIC(NumDSE   , "Number of dead stores elided"); | 
 | 43 | STATISTIC(NumDCE   , "Number of copies elided"); | 
| Alkis Evlogimenos | 0d6c5b6 | 2004-02-24 08:58:30 +0000 | [diff] [blame] | 44 |  | 
| Chris Lattner | cd3245a | 2006-12-19 22:41:21 +0000 | [diff] [blame] | 45 | namespace { | 
| Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 46 |   enum SpillerName { simple, local }; | 
| Alkis Evlogimenos | dd420e0 | 2004-03-01 23:18:15 +0000 | [diff] [blame] | 47 |  | 
| Andrew Lenharth | ed41f1b | 2006-07-20 17:28:38 +0000 | [diff] [blame] | 48 |   static cl::opt<SpillerName> | 
| Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 49 |   SpillerOpt("spiller", | 
| Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 50 |              cl::desc("Spiller to use: (default: local)"), | 
| Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 51 |              cl::Prefix, | 
 | 52 |              cl::values(clEnumVal(simple, "  simple spiller"), | 
 | 53 |                         clEnumVal(local,  "  local spiller"), | 
 | 54 |                         clEnumValEnd), | 
| Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 55 |              cl::init(local)); | 
| Alkis Evlogimenos | 34d9bc9 | 2004-02-23 23:08:11 +0000 | [diff] [blame] | 56 | } | 
 | 57 |  | 
| Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 58 | //===----------------------------------------------------------------------===// | 
 | 59 | //  VirtRegMap implementation | 
 | 60 | //===----------------------------------------------------------------------===// | 
 | 61 |  | 
| Chris Lattner | 2926869 | 2006-09-05 02:12:02 +0000 | [diff] [blame] | 62 | VirtRegMap::VirtRegMap(MachineFunction &mf) | 
 | 63 |   : TII(*mf.getTarget().getInstrInfo()), MF(mf),  | 
| Evan Cheng | 2638e1a | 2007-03-20 08:13:50 +0000 | [diff] [blame] | 64 |     Virt2PhysMap(NO_PHYS_REG), Virt2StackSlotMap(NO_STACK_SLOT), | 
| Evan Cheng | 549f27d3 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 65 |     Virt2ReMatIdMap(NO_STACK_SLOT), ReMatMap(NULL), | 
| Evan Cheng | 2638e1a | 2007-03-20 08:13:50 +0000 | [diff] [blame] | 66 |     ReMatId(MAX_STACK_SLOT+1) { | 
| Chris Lattner | 2926869 | 2006-09-05 02:12:02 +0000 | [diff] [blame] | 67 |   grow(); | 
 | 68 | } | 
 | 69 |  | 
| Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 70 | void VirtRegMap::grow() { | 
| Evan Cheng | 549f27d3 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 71 |   unsigned LastVirtReg = MF.getSSARegMap()->getLastVirtReg(); | 
 | 72 |   Virt2PhysMap.grow(LastVirtReg); | 
 | 73 |   Virt2StackSlotMap.grow(LastVirtReg); | 
 | 74 |   Virt2ReMatIdMap.grow(LastVirtReg); | 
 | 75 |   ReMatMap.grow(LastVirtReg); | 
| Alkis Evlogimenos | 34d9bc9 | 2004-02-23 23:08:11 +0000 | [diff] [blame] | 76 | } | 
 | 77 |  | 
| Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 78 | int VirtRegMap::assignVirt2StackSlot(unsigned virtReg) { | 
 | 79 |   assert(MRegisterInfo::isVirtualRegister(virtReg)); | 
| Chris Lattner | 7f690e6 | 2004-09-30 02:15:18 +0000 | [diff] [blame] | 80 |   assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT && | 
| Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 81 |          "attempt to assign stack slot to already spilled register"); | 
| Chris Lattner | 7f690e6 | 2004-09-30 02:15:18 +0000 | [diff] [blame] | 82 |   const TargetRegisterClass* RC = MF.getSSARegMap()->getRegClass(virtReg); | 
 | 83 |   int frameIndex = MF.getFrameInfo()->CreateStackObject(RC->getSize(), | 
 | 84 |                                                         RC->getAlignment()); | 
 | 85 |   Virt2StackSlotMap[virtReg] = frameIndex; | 
| Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 86 |   ++NumSpills; | 
 | 87 |   return frameIndex; | 
 | 88 | } | 
 | 89 |  | 
 | 90 | void VirtRegMap::assignVirt2StackSlot(unsigned virtReg, int frameIndex) { | 
 | 91 |   assert(MRegisterInfo::isVirtualRegister(virtReg)); | 
| Chris Lattner | 7f690e6 | 2004-09-30 02:15:18 +0000 | [diff] [blame] | 92 |   assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT && | 
| Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 93 |          "attempt to assign stack slot to already spilled register"); | 
| Evan Cheng | 9193514 | 2007-04-04 07:40:01 +0000 | [diff] [blame] | 94 |   assert((frameIndex >= 0 || | 
 | 95 |           (frameIndex >= MF.getFrameInfo()->getObjectIndexBegin())) && | 
 | 96 |          "illegal fixed frame index"); | 
| Chris Lattner | 7f690e6 | 2004-09-30 02:15:18 +0000 | [diff] [blame] | 97 |   Virt2StackSlotMap[virtReg] = frameIndex; | 
| Alkis Evlogimenos | 38af59a | 2004-05-29 20:38:05 +0000 | [diff] [blame] | 98 | } | 
 | 99 |  | 
| Evan Cheng | 2638e1a | 2007-03-20 08:13:50 +0000 | [diff] [blame] | 100 | int VirtRegMap::assignVirtReMatId(unsigned virtReg) { | 
 | 101 |   assert(MRegisterInfo::isVirtualRegister(virtReg)); | 
| Evan Cheng | 549f27d3 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 102 |   assert(Virt2ReMatIdMap[virtReg] == NO_STACK_SLOT && | 
| Evan Cheng | 2638e1a | 2007-03-20 08:13:50 +0000 | [diff] [blame] | 103 |          "attempt to assign re-mat id to already spilled register"); | 
| Evan Cheng | 549f27d3 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 104 |   Virt2ReMatIdMap[virtReg] = ReMatId; | 
| Evan Cheng | 2638e1a | 2007-03-20 08:13:50 +0000 | [diff] [blame] | 105 |   return ReMatId++; | 
 | 106 | } | 
 | 107 |  | 
| Evan Cheng | 549f27d3 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 108 | void VirtRegMap::assignVirtReMatId(unsigned virtReg, int id) { | 
 | 109 |   assert(MRegisterInfo::isVirtualRegister(virtReg)); | 
 | 110 |   assert(Virt2ReMatIdMap[virtReg] == NO_STACK_SLOT && | 
 | 111 |          "attempt to assign re-mat id to already spilled register"); | 
 | 112 |   Virt2ReMatIdMap[virtReg] = id; | 
 | 113 | } | 
 | 114 |  | 
| Chris Lattner | bec6a9e | 2004-10-01 23:15:36 +0000 | [diff] [blame] | 115 | void VirtRegMap::virtFolded(unsigned VirtReg, MachineInstr *OldMI, | 
| Chris Lattner | 35f2705 | 2006-05-01 21:16:03 +0000 | [diff] [blame] | 116 |                             unsigned OpNo, MachineInstr *NewMI) { | 
| Chris Lattner | bec6a9e | 2004-10-01 23:15:36 +0000 | [diff] [blame] | 117 |   // Move previous memory references folded to new instruction. | 
 | 118 |   MI2VirtMapTy::iterator IP = MI2VirtMap.lower_bound(NewMI); | 
| Misha Brukman | edf128a | 2005-04-21 22:36:52 +0000 | [diff] [blame] | 119 |   for (MI2VirtMapTy::iterator I = MI2VirtMap.lower_bound(OldMI), | 
| Chris Lattner | bec6a9e | 2004-10-01 23:15:36 +0000 | [diff] [blame] | 120 |          E = MI2VirtMap.end(); I != E && I->first == OldMI; ) { | 
 | 121 |     MI2VirtMap.insert(IP, std::make_pair(NewMI, I->second)); | 
| Chris Lattner | dbea973 | 2004-09-30 16:35:08 +0000 | [diff] [blame] | 122 |     MI2VirtMap.erase(I++); | 
| Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 123 |   } | 
| Chris Lattner | dbea973 | 2004-09-30 16:35:08 +0000 | [diff] [blame] | 124 |  | 
| Chris Lattner | bec6a9e | 2004-10-01 23:15:36 +0000 | [diff] [blame] | 125 |   ModRef MRInfo; | 
| Evan Cheng | 5c2a460 | 2006-12-08 08:02:34 +0000 | [diff] [blame] | 126 |   const TargetInstrDescriptor *TID = OldMI->getInstrDescriptor(); | 
 | 127 |   if (TID->getOperandConstraint(OpNo, TOI::TIED_TO) != -1 || | 
| Evan Cheng | cc22a7a | 2006-12-08 18:45:48 +0000 | [diff] [blame] | 128 |       TID->findTiedToSrcOperand(OpNo) != -1) { | 
| Chris Lattner | 2926869 | 2006-09-05 02:12:02 +0000 | [diff] [blame] | 129 |     // Folded a two-address operand. | 
 | 130 |     MRInfo = isModRef; | 
 | 131 |   } else if (OldMI->getOperand(OpNo).isDef()) { | 
 | 132 |     MRInfo = isMod; | 
| Chris Lattner | bec6a9e | 2004-10-01 23:15:36 +0000 | [diff] [blame] | 133 |   } else { | 
| Chris Lattner | 2926869 | 2006-09-05 02:12:02 +0000 | [diff] [blame] | 134 |     MRInfo = isRef; | 
| Chris Lattner | bec6a9e | 2004-10-01 23:15:36 +0000 | [diff] [blame] | 135 |   } | 
| Alkis Evlogimenos | 5f37502 | 2004-03-01 20:05:10 +0000 | [diff] [blame] | 136 |  | 
| Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 137 |   // add new memory reference | 
| Chris Lattner | bec6a9e | 2004-10-01 23:15:36 +0000 | [diff] [blame] | 138 |   MI2VirtMap.insert(IP, std::make_pair(NewMI, std::make_pair(VirtReg, MRInfo))); | 
| Alkis Evlogimenos | 5f37502 | 2004-03-01 20:05:10 +0000 | [diff] [blame] | 139 | } | 
 | 140 |  | 
| Chris Lattner | 7f690e6 | 2004-09-30 02:15:18 +0000 | [diff] [blame] | 141 | void VirtRegMap::print(std::ostream &OS) const { | 
 | 142 |   const MRegisterInfo* MRI = MF.getTarget().getRegisterInfo(); | 
| Alkis Evlogimenos | 34d9bc9 | 2004-02-23 23:08:11 +0000 | [diff] [blame] | 143 |  | 
| Chris Lattner | 7f690e6 | 2004-09-30 02:15:18 +0000 | [diff] [blame] | 144 |   OS << "********** REGISTER MAP **********\n"; | 
| Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 145 |   for (unsigned i = MRegisterInfo::FirstVirtualRegister, | 
| Chris Lattner | 7f690e6 | 2004-09-30 02:15:18 +0000 | [diff] [blame] | 146 |          e = MF.getSSARegMap()->getLastVirtReg(); i <= e; ++i) { | 
 | 147 |     if (Virt2PhysMap[i] != (unsigned)VirtRegMap::NO_PHYS_REG) | 
 | 148 |       OS << "[reg" << i << " -> " << MRI->getName(Virt2PhysMap[i]) << "]\n"; | 
| Misha Brukman | edf128a | 2005-04-21 22:36:52 +0000 | [diff] [blame] | 149 |  | 
| Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 150 |   } | 
 | 151 |  | 
 | 152 |   for (unsigned i = MRegisterInfo::FirstVirtualRegister, | 
| Chris Lattner | 7f690e6 | 2004-09-30 02:15:18 +0000 | [diff] [blame] | 153 |          e = MF.getSSARegMap()->getLastVirtReg(); i <= e; ++i) | 
 | 154 |     if (Virt2StackSlotMap[i] != VirtRegMap::NO_STACK_SLOT) | 
 | 155 |       OS << "[reg" << i << " -> fi#" << Virt2StackSlotMap[i] << "]\n"; | 
 | 156 |   OS << '\n'; | 
| Alkis Evlogimenos | 34d9bc9 | 2004-02-23 23:08:11 +0000 | [diff] [blame] | 157 | } | 
| Alkis Evlogimenos | 0d6c5b6 | 2004-02-24 08:58:30 +0000 | [diff] [blame] | 158 |  | 
| Bill Wendling | b2b9c20 | 2006-11-17 02:09:07 +0000 | [diff] [blame] | 159 | void VirtRegMap::dump() const { | 
| Bill Wendling | 5c7e326 | 2006-12-17 05:15:13 +0000 | [diff] [blame] | 160 |   print(DOUT); | 
| Bill Wendling | b2b9c20 | 2006-11-17 02:09:07 +0000 | [diff] [blame] | 161 | } | 
| Alkis Evlogimenos | dd420e0 | 2004-03-01 23:18:15 +0000 | [diff] [blame] | 162 |  | 
| Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 163 |  | 
 | 164 | //===----------------------------------------------------------------------===// | 
 | 165 | // Simple Spiller Implementation | 
 | 166 | //===----------------------------------------------------------------------===// | 
 | 167 |  | 
 | 168 | Spiller::~Spiller() {} | 
| Alkis Evlogimenos | dd420e0 | 2004-03-01 23:18:15 +0000 | [diff] [blame] | 169 |  | 
| Alkis Evlogimenos | 0d6c5b6 | 2004-02-24 08:58:30 +0000 | [diff] [blame] | 170 | namespace { | 
| Chris Lattner | f8c68f6 | 2006-06-28 22:17:39 +0000 | [diff] [blame] | 171 |   struct VISIBILITY_HIDDEN SimpleSpiller : public Spiller { | 
| Chris Lattner | 35f2705 | 2006-05-01 21:16:03 +0000 | [diff] [blame] | 172 |     bool runOnMachineFunction(MachineFunction& mf, VirtRegMap &VRM); | 
| Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 173 |   }; | 
| Alkis Evlogimenos | 0d6c5b6 | 2004-02-24 08:58:30 +0000 | [diff] [blame] | 174 | } | 
 | 175 |  | 
| Chris Lattner | 35f2705 | 2006-05-01 21:16:03 +0000 | [diff] [blame] | 176 | bool SimpleSpiller::runOnMachineFunction(MachineFunction &MF, VirtRegMap &VRM) { | 
| Bill Wendling | b2b9c20 | 2006-11-17 02:09:07 +0000 | [diff] [blame] | 177 |   DOUT << "********** REWRITE MACHINE CODE **********\n"; | 
 | 178 |   DOUT << "********** Function: " << MF.getFunction()->getName() << '\n'; | 
| Chris Lattner | b0f31bf | 2005-01-23 22:45:13 +0000 | [diff] [blame] | 179 |   const TargetMachine &TM = MF.getTarget(); | 
 | 180 |   const MRegisterInfo &MRI = *TM.getRegisterInfo(); | 
| Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 181 |  | 
| Chris Lattner | 4ea1b82 | 2004-09-30 02:33:48 +0000 | [diff] [blame] | 182 |   // LoadedRegs - Keep track of which vregs are loaded, so that we only load | 
 | 183 |   // each vreg once (in the case where a spilled vreg is used by multiple | 
 | 184 |   // operands).  This is always smaller than the number of operands to the | 
 | 185 |   // current machine instr, so it should be small. | 
 | 186 |   std::vector<unsigned> LoadedRegs; | 
| Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 187 |  | 
| Chris Lattner | 0fc27cc | 2004-09-30 02:59:33 +0000 | [diff] [blame] | 188 |   for (MachineFunction::iterator MBBI = MF.begin(), E = MF.end(); | 
 | 189 |        MBBI != E; ++MBBI) { | 
| Bill Wendling | b2b9c20 | 2006-11-17 02:09:07 +0000 | [diff] [blame] | 190 |     DOUT << MBBI->getBasicBlock()->getName() << ":\n"; | 
| Chris Lattner | 0fc27cc | 2004-09-30 02:59:33 +0000 | [diff] [blame] | 191 |     MachineBasicBlock &MBB = *MBBI; | 
 | 192 |     for (MachineBasicBlock::iterator MII = MBB.begin(), | 
 | 193 |            E = MBB.end(); MII != E; ++MII) { | 
 | 194 |       MachineInstr &MI = *MII; | 
 | 195 |       for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) { | 
| Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 196 |         MachineOperand &MO = MI.getOperand(i); | 
| Chris Lattner | 886dd91 | 2005-04-04 21:35:34 +0000 | [diff] [blame] | 197 |         if (MO.isRegister() && MO.getReg()) | 
 | 198 |           if (MRegisterInfo::isVirtualRegister(MO.getReg())) { | 
 | 199 |             unsigned VirtReg = MO.getReg(); | 
 | 200 |             unsigned PhysReg = VRM.getPhys(VirtReg); | 
| Evan Cheng | 549f27d3 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 201 |             if (!VRM.isAssignedReg(VirtReg)) { | 
| Chris Lattner | 886dd91 | 2005-04-04 21:35:34 +0000 | [diff] [blame] | 202 |               int StackSlot = VRM.getStackSlot(VirtReg); | 
| Chris Lattner | bf9716b | 2005-09-30 01:29:00 +0000 | [diff] [blame] | 203 |               const TargetRegisterClass* RC = | 
 | 204 |                 MF.getSSARegMap()->getRegClass(VirtReg); | 
| Misha Brukman | edf128a | 2005-04-21 22:36:52 +0000 | [diff] [blame] | 205 |  | 
| Chris Lattner | 886dd91 | 2005-04-04 21:35:34 +0000 | [diff] [blame] | 206 |               if (MO.isUse() && | 
 | 207 |                   std::find(LoadedRegs.begin(), LoadedRegs.end(), VirtReg) | 
 | 208 |                   == LoadedRegs.end()) { | 
| Chris Lattner | bf9716b | 2005-09-30 01:29:00 +0000 | [diff] [blame] | 209 |                 MRI.loadRegFromStackSlot(MBB, &MI, PhysReg, StackSlot, RC); | 
| Chris Lattner | 886dd91 | 2005-04-04 21:35:34 +0000 | [diff] [blame] | 210 |                 LoadedRegs.push_back(VirtReg); | 
 | 211 |                 ++NumLoads; | 
| Bill Wendling | b2b9c20 | 2006-11-17 02:09:07 +0000 | [diff] [blame] | 212 |                 DOUT << '\t' << *prior(MII); | 
| Chris Lattner | 886dd91 | 2005-04-04 21:35:34 +0000 | [diff] [blame] | 213 |               } | 
| Misha Brukman | edf128a | 2005-04-21 22:36:52 +0000 | [diff] [blame] | 214 |  | 
| Chris Lattner | 886dd91 | 2005-04-04 21:35:34 +0000 | [diff] [blame] | 215 |               if (MO.isDef()) { | 
| Chris Lattner | bf9716b | 2005-09-30 01:29:00 +0000 | [diff] [blame] | 216 |                 MRI.storeRegToStackSlot(MBB, next(MII), PhysReg, StackSlot, RC); | 
| Chris Lattner | 886dd91 | 2005-04-04 21:35:34 +0000 | [diff] [blame] | 217 |                 ++NumStores; | 
 | 218 |               } | 
| Chris Lattner | 0fc27cc | 2004-09-30 02:59:33 +0000 | [diff] [blame] | 219 |             } | 
| Evan Cheng | 6c087e5 | 2007-04-25 22:13:27 +0000 | [diff] [blame] | 220 |             MF.setPhysRegUsed(PhysReg); | 
| Chris Lattner | e53f4a0 | 2006-05-04 17:52:23 +0000 | [diff] [blame] | 221 |             MI.getOperand(i).setReg(PhysReg); | 
| Chris Lattner | 886dd91 | 2005-04-04 21:35:34 +0000 | [diff] [blame] | 222 |           } else { | 
| Evan Cheng | 6c087e5 | 2007-04-25 22:13:27 +0000 | [diff] [blame] | 223 |             MF.setPhysRegUsed(MO.getReg()); | 
| Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 224 |           } | 
| Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 225 |       } | 
| Chris Lattner | 886dd91 | 2005-04-04 21:35:34 +0000 | [diff] [blame] | 226 |  | 
| Bill Wendling | b2b9c20 | 2006-11-17 02:09:07 +0000 | [diff] [blame] | 227 |       DOUT << '\t' << MI; | 
| Chris Lattner | 4ea1b82 | 2004-09-30 02:33:48 +0000 | [diff] [blame] | 228 |       LoadedRegs.clear(); | 
| Alkis Evlogimenos | dd420e0 | 2004-03-01 23:18:15 +0000 | [diff] [blame] | 229 |     } | 
| Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 230 |   } | 
 | 231 |   return true; | 
 | 232 | } | 
 | 233 |  | 
 | 234 | //===----------------------------------------------------------------------===// | 
 | 235 | //  Local Spiller Implementation | 
 | 236 | //===----------------------------------------------------------------------===// | 
 | 237 |  | 
 | 238 | namespace { | 
| Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 239 |   /// LocalSpiller - This spiller does a simple pass over the machine basic | 
 | 240 |   /// block to attempt to keep spills in registers as much as possible for | 
 | 241 |   /// blocks that have low register pressure (the vreg may be spilled due to | 
 | 242 |   /// register pressure in other blocks). | 
| Chris Lattner | f8c68f6 | 2006-06-28 22:17:39 +0000 | [diff] [blame] | 243 |   class VISIBILITY_HIDDEN LocalSpiller : public Spiller { | 
| Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 244 |     const MRegisterInfo *MRI; | 
| Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 245 |     const TargetInstrInfo *TII; | 
| Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 246 |   public: | 
| Chris Lattner | 35f2705 | 2006-05-01 21:16:03 +0000 | [diff] [blame] | 247 |     bool runOnMachineFunction(MachineFunction &MF, VirtRegMap &VRM) { | 
| Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 248 |       MRI = MF.getTarget().getRegisterInfo(); | 
 | 249 |       TII = MF.getTarget().getInstrInfo(); | 
| Bill Wendling | b2b9c20 | 2006-11-17 02:09:07 +0000 | [diff] [blame] | 250 |       DOUT << "\n**** Local spiller rewriting function '" | 
 | 251 |            << MF.getFunction()->getName() << "':\n"; | 
| Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 252 |  | 
| Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 253 |       for (MachineFunction::iterator MBB = MF.begin(), E = MF.end(); | 
 | 254 |            MBB != E; ++MBB) | 
| Evan Cheng | 549f27d3 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 255 |         RewriteMBB(*MBB, VRM); | 
| Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 256 |       return true; | 
 | 257 |     } | 
| Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 258 |   private: | 
| Evan Cheng | 549f27d3 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 259 |     void RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM); | 
| Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 260 |   }; | 
 | 261 | } | 
 | 262 |  | 
| Chris Lattner | 66cf80f | 2006-02-03 23:13:58 +0000 | [diff] [blame] | 263 | /// AvailableSpills - As the local spiller is scanning and rewriting an MBB from | 
| Evan Cheng | 549f27d3 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 264 | /// top down, keep track of which spills slots or remat are available in each | 
 | 265 | /// register. | 
| Chris Lattner | 593c958 | 2006-02-03 23:28:46 +0000 | [diff] [blame] | 266 | /// | 
 | 267 | /// Note that not all physregs are created equal here.  In particular, some | 
 | 268 | /// physregs are reloads that we are allowed to clobber or ignore at any time. | 
 | 269 | /// Other physregs are values that the register allocated program is using that | 
 | 270 | /// we cannot CHANGE, but we can read if we like.  We keep track of this on a  | 
| Evan Cheng | 549f27d3 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 271 | /// per-stack-slot / remat id basis as the low bit in the value of the | 
 | 272 | /// SpillSlotsAvailable entries.  The predicate 'canClobberPhysReg()' checks | 
 | 273 | /// this bit and addAvailable sets it if. | 
| Chris Lattner | f8c68f6 | 2006-06-28 22:17:39 +0000 | [diff] [blame] | 274 | namespace { | 
 | 275 | class VISIBILITY_HIDDEN AvailableSpills { | 
| Chris Lattner | 66cf80f | 2006-02-03 23:13:58 +0000 | [diff] [blame] | 276 |   const MRegisterInfo *MRI; | 
 | 277 |   const TargetInstrInfo *TII; | 
 | 278 |  | 
| Evan Cheng | 549f27d3 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 279 |   // SpillSlotsOrReMatsAvailable - This map keeps track of all of the spilled | 
 | 280 |   // or remat'ed virtual register values that are still available, due to being | 
 | 281 |   // loaded or stored to, but not invalidated yet. | 
 | 282 |   std::map<int, unsigned> SpillSlotsOrReMatsAvailable; | 
| Chris Lattner | 66cf80f | 2006-02-03 23:13:58 +0000 | [diff] [blame] | 283 |      | 
| Evan Cheng | 549f27d3 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 284 |   // PhysRegsAvailable - This is the inverse of SpillSlotsOrReMatsAvailable, | 
 | 285 |   // indicating which stack slot values are currently held by a physreg.  This | 
 | 286 |   // is used to invalidate entries in SpillSlotsOrReMatsAvailable when a | 
 | 287 |   // physreg is modified. | 
| Chris Lattner | 66cf80f | 2006-02-03 23:13:58 +0000 | [diff] [blame] | 288 |   std::multimap<unsigned, int> PhysRegsAvailable; | 
 | 289 |    | 
| Evan Cheng | 7a0d51c | 2006-12-14 07:54:05 +0000 | [diff] [blame] | 290 |   void disallowClobberPhysRegOnly(unsigned PhysReg); | 
 | 291 |  | 
| Chris Lattner | 66cf80f | 2006-02-03 23:13:58 +0000 | [diff] [blame] | 292 |   void ClobberPhysRegOnly(unsigned PhysReg); | 
 | 293 | public: | 
 | 294 |   AvailableSpills(const MRegisterInfo *mri, const TargetInstrInfo *tii) | 
 | 295 |     : MRI(mri), TII(tii) { | 
 | 296 |   } | 
 | 297 |    | 
| Evan Cheng | 91e2390 | 2007-02-23 01:13:26 +0000 | [diff] [blame] | 298 |   const MRegisterInfo *getRegInfo() const { return MRI; } | 
 | 299 |  | 
| Evan Cheng | 549f27d3 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 300 |   /// getSpillSlotOrReMatPhysReg - If the specified stack slot or remat is | 
 | 301 |   /// available in a  physical register, return that PhysReg, otherwise | 
 | 302 |   /// return 0. | 
 | 303 |   unsigned getSpillSlotOrReMatPhysReg(int Slot) const { | 
 | 304 |     std::map<int, unsigned>::const_iterator I = | 
 | 305 |       SpillSlotsOrReMatsAvailable.find(Slot); | 
 | 306 |     if (I != SpillSlotsOrReMatsAvailable.end()) { | 
| Evan Cheng | b9591c6 | 2007-07-11 08:47:44 +0000 | [diff] [blame] | 307 |       return I->second >> 1;  // Remove the CanClobber bit. | 
| Evan Cheng | 91e2390 | 2007-02-23 01:13:26 +0000 | [diff] [blame] | 308 |     } | 
| Chris Lattner | 66cf80f | 2006-02-03 23:13:58 +0000 | [diff] [blame] | 309 |     return 0; | 
 | 310 |   } | 
| Evan Cheng | de4e942 | 2007-02-25 09:51:27 +0000 | [diff] [blame] | 311 |  | 
| Evan Cheng | 549f27d3 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 312 |   /// addAvailable - Mark that the specified stack slot / remat is available in | 
 | 313 |   /// the specified physreg.  If CanClobber is true, the physreg can be modified | 
 | 314 |   /// at any time without changing the semantics of the program. | 
 | 315 |   void addAvailable(int SlotOrReMat, MachineInstr *MI, unsigned Reg, | 
| Evan Cheng | 91e2390 | 2007-02-23 01:13:26 +0000 | [diff] [blame] | 316 |                     bool CanClobber = true) { | 
| Chris Lattner | 8666249 | 2006-02-03 23:50:46 +0000 | [diff] [blame] | 317 |     // If this stack slot is thought to be available in some other physreg,  | 
 | 318 |     // remove its record. | 
| Evan Cheng | 549f27d3 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 319 |     ModifyStackSlotOrReMat(SlotOrReMat); | 
| Chris Lattner | 8666249 | 2006-02-03 23:50:46 +0000 | [diff] [blame] | 320 |      | 
| Evan Cheng | 549f27d3 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 321 |     PhysRegsAvailable.insert(std::make_pair(Reg, SlotOrReMat)); | 
 | 322 |     SpillSlotsOrReMatsAvailable[SlotOrReMat] = (Reg << 1) | (unsigned)CanClobber; | 
| Chris Lattner | 66cf80f | 2006-02-03 23:13:58 +0000 | [diff] [blame] | 323 |    | 
| Evan Cheng | 549f27d3 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 324 |     if (SlotOrReMat > VirtRegMap::MAX_STACK_SLOT) | 
 | 325 |       DOUT << "Remembering RM#" << SlotOrReMat-VirtRegMap::MAX_STACK_SLOT-1; | 
| Evan Cheng | 2638e1a | 2007-03-20 08:13:50 +0000 | [diff] [blame] | 326 |     else | 
| Evan Cheng | 549f27d3 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 327 |       DOUT << "Remembering SS#" << SlotOrReMat; | 
| Evan Cheng | 2638e1a | 2007-03-20 08:13:50 +0000 | [diff] [blame] | 328 |     DOUT << " in physreg " << MRI->getName(Reg) << "\n"; | 
| Chris Lattner | 66cf80f | 2006-02-03 23:13:58 +0000 | [diff] [blame] | 329 |   } | 
| Evan Cheng | 7a0d51c | 2006-12-14 07:54:05 +0000 | [diff] [blame] | 330 |  | 
| Chris Lattner | 593c958 | 2006-02-03 23:28:46 +0000 | [diff] [blame] | 331 |   /// canClobberPhysReg - Return true if the spiller is allowed to change the  | 
 | 332 |   /// value of the specified stackslot register if it desires.  The specified | 
 | 333 |   /// stack slot must be available in a physreg for this query to make sense. | 
| Evan Cheng | 549f27d3 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 334 |   bool canClobberPhysReg(int SlotOrReMat) const { | 
 | 335 |     assert(SpillSlotsOrReMatsAvailable.count(SlotOrReMat) && "Value not available!"); | 
 | 336 |     return SpillSlotsOrReMatsAvailable.find(SlotOrReMat)->second & 1; | 
| Chris Lattner | 593c958 | 2006-02-03 23:28:46 +0000 | [diff] [blame] | 337 |   } | 
| Chris Lattner | 66cf80f | 2006-02-03 23:13:58 +0000 | [diff] [blame] | 338 |    | 
| Evan Cheng | 7a0d51c | 2006-12-14 07:54:05 +0000 | [diff] [blame] | 339 |   /// disallowClobberPhysReg - Unset the CanClobber bit of the specified | 
 | 340 |   /// stackslot register. The register is still available but is no longer | 
 | 341 |   /// allowed to be modifed. | 
 | 342 |   void disallowClobberPhysReg(unsigned PhysReg); | 
 | 343 |    | 
| Chris Lattner | 66cf80f | 2006-02-03 23:13:58 +0000 | [diff] [blame] | 344 |   /// ClobberPhysReg - This is called when the specified physreg changes | 
 | 345 |   /// value.  We use this to invalidate any info about stuff we thing lives in | 
 | 346 |   /// it and any of its aliases. | 
 | 347 |   void ClobberPhysReg(unsigned PhysReg); | 
 | 348 |  | 
| Evan Cheng | 549f27d3 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 349 |   /// ModifyStackSlotOrReMat - This method is called when the value in a stack slot | 
| Chris Lattner | 66cf80f | 2006-02-03 23:13:58 +0000 | [diff] [blame] | 350 |   /// changes.  This removes information about which register the previous value | 
 | 351 |   /// for this slot lives in (as the previous value is dead now). | 
| Evan Cheng | 549f27d3 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 352 |   void ModifyStackSlotOrReMat(int SlotOrReMat); | 
| Chris Lattner | 66cf80f | 2006-02-03 23:13:58 +0000 | [diff] [blame] | 353 | }; | 
| Chris Lattner | f8c68f6 | 2006-06-28 22:17:39 +0000 | [diff] [blame] | 354 | } | 
| Chris Lattner | 66cf80f | 2006-02-03 23:13:58 +0000 | [diff] [blame] | 355 |  | 
| Evan Cheng | 7a0d51c | 2006-12-14 07:54:05 +0000 | [diff] [blame] | 356 | /// disallowClobberPhysRegOnly - Unset the CanClobber bit of the specified | 
 | 357 | /// stackslot register. The register is still available but is no longer | 
 | 358 | /// allowed to be modifed. | 
 | 359 | void AvailableSpills::disallowClobberPhysRegOnly(unsigned PhysReg) { | 
 | 360 |   std::multimap<unsigned, int>::iterator I = | 
 | 361 |     PhysRegsAvailable.lower_bound(PhysReg); | 
 | 362 |   while (I != PhysRegsAvailable.end() && I->first == PhysReg) { | 
| Evan Cheng | 549f27d3 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 363 |     int SlotOrReMat = I->second; | 
| Evan Cheng | 7a0d51c | 2006-12-14 07:54:05 +0000 | [diff] [blame] | 364 |     I++; | 
| Evan Cheng | 549f27d3 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 365 |     assert((SpillSlotsOrReMatsAvailable[SlotOrReMat] >> 1) == PhysReg && | 
| Evan Cheng | 7a0d51c | 2006-12-14 07:54:05 +0000 | [diff] [blame] | 366 |            "Bidirectional map mismatch!"); | 
| Evan Cheng | 549f27d3 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 367 |     SpillSlotsOrReMatsAvailable[SlotOrReMat] &= ~1; | 
| Evan Cheng | 7a0d51c | 2006-12-14 07:54:05 +0000 | [diff] [blame] | 368 |     DOUT << "PhysReg " << MRI->getName(PhysReg) | 
 | 369 |          << " copied, it is available for use but can no longer be modified\n"; | 
 | 370 |   } | 
 | 371 | } | 
 | 372 |  | 
 | 373 | /// disallowClobberPhysReg - Unset the CanClobber bit of the specified | 
 | 374 | /// stackslot register and its aliases. The register and its aliases may | 
 | 375 | /// still available but is no longer allowed to be modifed. | 
 | 376 | void AvailableSpills::disallowClobberPhysReg(unsigned PhysReg) { | 
 | 377 |   for (const unsigned *AS = MRI->getAliasSet(PhysReg); *AS; ++AS) | 
 | 378 |     disallowClobberPhysRegOnly(*AS); | 
 | 379 |   disallowClobberPhysRegOnly(PhysReg); | 
 | 380 | } | 
 | 381 |  | 
| Chris Lattner | 66cf80f | 2006-02-03 23:13:58 +0000 | [diff] [blame] | 382 | /// ClobberPhysRegOnly - This is called when the specified physreg changes | 
 | 383 | /// value.  We use this to invalidate any info about stuff we thing lives in it. | 
 | 384 | void AvailableSpills::ClobberPhysRegOnly(unsigned PhysReg) { | 
 | 385 |   std::multimap<unsigned, int>::iterator I = | 
 | 386 |     PhysRegsAvailable.lower_bound(PhysReg); | 
| Chris Lattner | 07cf141 | 2006-02-03 00:36:31 +0000 | [diff] [blame] | 387 |   while (I != PhysRegsAvailable.end() && I->first == PhysReg) { | 
| Evan Cheng | 549f27d3 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 388 |     int SlotOrReMat = I->second; | 
| Chris Lattner | 07cf141 | 2006-02-03 00:36:31 +0000 | [diff] [blame] | 389 |     PhysRegsAvailable.erase(I++); | 
| Evan Cheng | 549f27d3 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 390 |     assert((SpillSlotsOrReMatsAvailable[SlotOrReMat] >> 1) == PhysReg && | 
| Chris Lattner | 66cf80f | 2006-02-03 23:13:58 +0000 | [diff] [blame] | 391 |            "Bidirectional map mismatch!"); | 
| Evan Cheng | 549f27d3 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 392 |     SpillSlotsOrReMatsAvailable.erase(SlotOrReMat); | 
| Bill Wendling | b2b9c20 | 2006-11-17 02:09:07 +0000 | [diff] [blame] | 393 |     DOUT << "PhysReg " << MRI->getName(PhysReg) | 
| Evan Cheng | 2638e1a | 2007-03-20 08:13:50 +0000 | [diff] [blame] | 394 |          << " clobbered, invalidating "; | 
| Evan Cheng | 549f27d3 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 395 |     if (SlotOrReMat > VirtRegMap::MAX_STACK_SLOT) | 
 | 396 |       DOUT << "RM#" << SlotOrReMat-VirtRegMap::MAX_STACK_SLOT-1 << "\n"; | 
| Evan Cheng | 2638e1a | 2007-03-20 08:13:50 +0000 | [diff] [blame] | 397 |     else | 
| Evan Cheng | 549f27d3 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 398 |       DOUT << "SS#" << SlotOrReMat << "\n"; | 
| Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 399 |   } | 
| Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 400 | } | 
 | 401 |  | 
| Chris Lattner | 66cf80f | 2006-02-03 23:13:58 +0000 | [diff] [blame] | 402 | /// ClobberPhysReg - This is called when the specified physreg changes | 
 | 403 | /// value.  We use this to invalidate any info about stuff we thing lives in | 
 | 404 | /// it and any of its aliases. | 
 | 405 | void AvailableSpills::ClobberPhysReg(unsigned PhysReg) { | 
| Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 406 |   for (const unsigned *AS = MRI->getAliasSet(PhysReg); *AS; ++AS) | 
| Chris Lattner | 66cf80f | 2006-02-03 23:13:58 +0000 | [diff] [blame] | 407 |     ClobberPhysRegOnly(*AS); | 
 | 408 |   ClobberPhysRegOnly(PhysReg); | 
| Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 409 | } | 
 | 410 |  | 
| Evan Cheng | 549f27d3 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 411 | /// ModifyStackSlotOrReMat - This method is called when the value in a stack slot | 
| Chris Lattner | 07cf141 | 2006-02-03 00:36:31 +0000 | [diff] [blame] | 412 | /// changes.  This removes information about which register the previous value | 
 | 413 | /// for this slot lives in (as the previous value is dead now). | 
| Evan Cheng | 549f27d3 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 414 | void AvailableSpills::ModifyStackSlotOrReMat(int SlotOrReMat) { | 
 | 415 |   std::map<int, unsigned>::iterator It = SpillSlotsOrReMatsAvailable.find(SlotOrReMat); | 
 | 416 |   if (It == SpillSlotsOrReMatsAvailable.end()) return; | 
| Evan Cheng | b9591c6 | 2007-07-11 08:47:44 +0000 | [diff] [blame] | 417 |   unsigned Reg = It->second >> 1; | 
| Evan Cheng | 549f27d3 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 418 |   SpillSlotsOrReMatsAvailable.erase(It); | 
| Chris Lattner | 07cf141 | 2006-02-03 00:36:31 +0000 | [diff] [blame] | 419 |    | 
 | 420 |   // This register may hold the value of multiple stack slots, only remove this | 
 | 421 |   // stack slot from the set of values the register contains. | 
 | 422 |   std::multimap<unsigned, int>::iterator I = PhysRegsAvailable.lower_bound(Reg); | 
 | 423 |   for (; ; ++I) { | 
 | 424 |     assert(I != PhysRegsAvailable.end() && I->first == Reg && | 
 | 425 |            "Map inverse broken!"); | 
| Evan Cheng | 549f27d3 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 426 |     if (I->second == SlotOrReMat) break; | 
| Chris Lattner | 07cf141 | 2006-02-03 00:36:31 +0000 | [diff] [blame] | 427 |   } | 
 | 428 |   PhysRegsAvailable.erase(I); | 
 | 429 | } | 
 | 430 |  | 
 | 431 |  | 
| Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 432 |  | 
| Evan Cheng | 28bb462 | 2007-07-11 19:17:18 +0000 | [diff] [blame] | 433 | /// InvalidateKills - MI is going to be deleted. If any of its operands are | 
 | 434 | /// marked kill, then invalidate the information. | 
 | 435 | static void InvalidateKills(MachineInstr &MI, BitVector &RegKills, | 
 | 436 |                            std::vector<MachineOperand*> &KillOps) { | 
 | 437 |   for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) { | 
 | 438 |     MachineOperand &MO = MI.getOperand(i); | 
 | 439 |     if (!MO.isReg() || !MO.isUse() || !MO.isKill()) | 
 | 440 |       continue; | 
 | 441 |     unsigned Reg = MO.getReg(); | 
 | 442 |     if (KillOps[Reg] == &MO) { | 
 | 443 |       RegKills.reset(Reg); | 
 | 444 |       KillOps[Reg] = NULL; | 
 | 445 |     } | 
 | 446 |   } | 
 | 447 | } | 
 | 448 |  | 
 | 449 | /// UpdateKills - Track and update kill info. If a MI reads a register that is | 
 | 450 | /// marked kill, then it must be due to register reuse. Transfer the kill info | 
 | 451 | /// over. | 
 | 452 | static void UpdateKills(MachineInstr &MI, BitVector &RegKills, | 
 | 453 |                         std::vector<MachineOperand*> &KillOps) { | 
 | 454 |   const TargetInstrDescriptor *TID = MI.getInstrDescriptor(); | 
 | 455 |   for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) { | 
 | 456 |     MachineOperand &MO = MI.getOperand(i); | 
 | 457 |     if (!MO.isReg() || !MO.isUse()) | 
 | 458 |       continue; | 
 | 459 |     unsigned Reg = MO.getReg(); | 
 | 460 |     if (Reg == 0) | 
 | 461 |       continue; | 
 | 462 |      | 
 | 463 |     if (RegKills[Reg]) { | 
 | 464 |       // That can't be right. Register is killed but not re-defined and it's | 
 | 465 |       // being reused. Let's fix that. | 
 | 466 |       KillOps[Reg]->unsetIsKill(); | 
 | 467 |       if (i < TID->numOperands && | 
 | 468 |           TID->getOperandConstraint(i, TOI::TIED_TO) == -1) | 
 | 469 |         // Unless it's a two-address operand, this is the new kill. | 
 | 470 |         MO.setIsKill(); | 
 | 471 |     } | 
 | 472 |  | 
 | 473 |     if (MO.isKill()) { | 
 | 474 |       RegKills.set(Reg); | 
 | 475 |       KillOps[Reg] = &MO; | 
 | 476 |     } | 
 | 477 |   } | 
 | 478 |  | 
 | 479 |   for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) { | 
 | 480 |     const MachineOperand &MO = MI.getOperand(i); | 
 | 481 |     if (!MO.isReg() || !MO.isDef()) | 
 | 482 |       continue; | 
 | 483 |     unsigned Reg = MO.getReg(); | 
 | 484 |     RegKills.reset(Reg); | 
 | 485 |     KillOps[Reg] = NULL; | 
 | 486 |   } | 
 | 487 | } | 
 | 488 |  | 
 | 489 |  | 
| Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 490 | // ReusedOp - For each reused operand, we keep track of a bit of information, in | 
 | 491 | // case we need to rollback upon processing a new operand.  See comments below. | 
 | 492 | namespace { | 
 | 493 |   struct ReusedOp { | 
 | 494 |     // The MachineInstr operand that reused an available value. | 
 | 495 |     unsigned Operand; | 
| Misha Brukman | edf128a | 2005-04-21 22:36:52 +0000 | [diff] [blame] | 496 |  | 
| Evan Cheng | 549f27d3 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 497 |     // StackSlotOrReMat - The spill slot or remat id of the value being reused. | 
 | 498 |     unsigned StackSlotOrReMat; | 
| Misha Brukman | edf128a | 2005-04-21 22:36:52 +0000 | [diff] [blame] | 499 |  | 
| Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 500 |     // PhysRegReused - The physical register the value was available in. | 
 | 501 |     unsigned PhysRegReused; | 
| Misha Brukman | edf128a | 2005-04-21 22:36:52 +0000 | [diff] [blame] | 502 |  | 
| Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 503 |     // AssignedPhysReg - The physreg that was assigned for use by the reload. | 
 | 504 |     unsigned AssignedPhysReg; | 
| Chris Lattner | 8a61a75 | 2005-10-06 17:19:06 +0000 | [diff] [blame] | 505 |      | 
 | 506 |     // VirtReg - The virtual register itself. | 
 | 507 |     unsigned VirtReg; | 
| Misha Brukman | edf128a | 2005-04-21 22:36:52 +0000 | [diff] [blame] | 508 |  | 
| Chris Lattner | 8a61a75 | 2005-10-06 17:19:06 +0000 | [diff] [blame] | 509 |     ReusedOp(unsigned o, unsigned ss, unsigned prr, unsigned apr, | 
 | 510 |              unsigned vreg) | 
| Evan Cheng | 549f27d3 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 511 |       : Operand(o), StackSlotOrReMat(ss), PhysRegReused(prr), AssignedPhysReg(apr), | 
| Chris Lattner | 8a61a75 | 2005-10-06 17:19:06 +0000 | [diff] [blame] | 512 |       VirtReg(vreg) {} | 
| Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 513 |   }; | 
| Chris Lattner | 540fec6 | 2006-02-25 01:51:33 +0000 | [diff] [blame] | 514 |    | 
 | 515 |   /// ReuseInfo - This maintains a collection of ReuseOp's for each operand that | 
 | 516 |   /// is reused instead of reloaded. | 
| Chris Lattner | f8c68f6 | 2006-06-28 22:17:39 +0000 | [diff] [blame] | 517 |   class VISIBILITY_HIDDEN ReuseInfo { | 
| Chris Lattner | 540fec6 | 2006-02-25 01:51:33 +0000 | [diff] [blame] | 518 |     MachineInstr &MI; | 
 | 519 |     std::vector<ReusedOp> Reuses; | 
| Evan Cheng | 957840b | 2007-02-21 02:22:03 +0000 | [diff] [blame] | 520 |     BitVector PhysRegsClobbered; | 
| Chris Lattner | 540fec6 | 2006-02-25 01:51:33 +0000 | [diff] [blame] | 521 |   public: | 
| Evan Cheng | e077ef6 | 2006-11-04 00:21:55 +0000 | [diff] [blame] | 522 |     ReuseInfo(MachineInstr &mi, const MRegisterInfo *mri) : MI(mi) { | 
| Evan Cheng | 957840b | 2007-02-21 02:22:03 +0000 | [diff] [blame] | 523 |       PhysRegsClobbered.resize(mri->getNumRegs()); | 
| Evan Cheng | e077ef6 | 2006-11-04 00:21:55 +0000 | [diff] [blame] | 524 |     } | 
| Chris Lattner | 540fec6 | 2006-02-25 01:51:33 +0000 | [diff] [blame] | 525 |      | 
 | 526 |     bool hasReuses() const { | 
 | 527 |       return !Reuses.empty(); | 
 | 528 |     } | 
 | 529 |      | 
 | 530 |     /// addReuse - If we choose to reuse a virtual register that is already | 
 | 531 |     /// available instead of reloading it, remember that we did so. | 
| Evan Cheng | 549f27d3 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 532 |     void addReuse(unsigned OpNo, unsigned StackSlotOrReMat, | 
| Chris Lattner | 540fec6 | 2006-02-25 01:51:33 +0000 | [diff] [blame] | 533 |                   unsigned PhysRegReused, unsigned AssignedPhysReg, | 
 | 534 |                   unsigned VirtReg) { | 
 | 535 |       // If the reload is to the assigned register anyway, no undo will be | 
 | 536 |       // required. | 
 | 537 |       if (PhysRegReused == AssignedPhysReg) return; | 
 | 538 |        | 
 | 539 |       // Otherwise, remember this. | 
| Evan Cheng | 549f27d3 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 540 |       Reuses.push_back(ReusedOp(OpNo, StackSlotOrReMat, PhysRegReused,  | 
| Chris Lattner | 540fec6 | 2006-02-25 01:51:33 +0000 | [diff] [blame] | 541 |                                 AssignedPhysReg, VirtReg)); | 
 | 542 |     } | 
| Evan Cheng | e077ef6 | 2006-11-04 00:21:55 +0000 | [diff] [blame] | 543 |  | 
 | 544 |     void markClobbered(unsigned PhysReg) { | 
| Evan Cheng | 957840b | 2007-02-21 02:22:03 +0000 | [diff] [blame] | 545 |       PhysRegsClobbered.set(PhysReg); | 
| Evan Cheng | e077ef6 | 2006-11-04 00:21:55 +0000 | [diff] [blame] | 546 |     } | 
 | 547 |  | 
 | 548 |     bool isClobbered(unsigned PhysReg) const { | 
| Evan Cheng | 957840b | 2007-02-21 02:22:03 +0000 | [diff] [blame] | 549 |       return PhysRegsClobbered.test(PhysReg); | 
| Evan Cheng | e077ef6 | 2006-11-04 00:21:55 +0000 | [diff] [blame] | 550 |     } | 
| Chris Lattner | 540fec6 | 2006-02-25 01:51:33 +0000 | [diff] [blame] | 551 |      | 
 | 552 |     /// GetRegForReload - We are about to emit a reload into PhysReg.  If there | 
 | 553 |     /// is some other operand that is using the specified register, either pick | 
 | 554 |     /// a new register to use, or evict the previous reload and use this reg.  | 
 | 555 |     unsigned GetRegForReload(unsigned PhysReg, MachineInstr *MI, | 
 | 556 |                              AvailableSpills &Spills, | 
| Evan Cheng | 3c82cab | 2007-01-19 22:40:14 +0000 | [diff] [blame] | 557 |                              std::map<int, MachineInstr*> &MaybeDeadStores, | 
| Evan Cheng | 28bb462 | 2007-07-11 19:17:18 +0000 | [diff] [blame] | 558 |                              SmallSet<unsigned, 8> &Rejected, | 
 | 559 |                              BitVector &RegKills, | 
| Evan Cheng | 549f27d3 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 560 |                              std::vector<MachineOperand*> &KillOps, | 
 | 561 |                              VirtRegMap &VRM) { | 
| Chris Lattner | 540fec6 | 2006-02-25 01:51:33 +0000 | [diff] [blame] | 562 |       if (Reuses.empty()) return PhysReg;  // This is most often empty. | 
 | 563 |  | 
 | 564 |       for (unsigned ro = 0, e = Reuses.size(); ro != e; ++ro) { | 
 | 565 |         ReusedOp &Op = Reuses[ro]; | 
 | 566 |         // If we find some other reuse that was supposed to use this register | 
 | 567 |         // exactly for its reload, we can change this reload to use ITS reload | 
| Evan Cheng | 3c82cab | 2007-01-19 22:40:14 +0000 | [diff] [blame] | 568 |         // register. That is, unless its reload register has already been | 
 | 569 |         // considered and subsequently rejected because it has also been reused | 
 | 570 |         // by another operand. | 
 | 571 |         if (Op.PhysRegReused == PhysReg && | 
 | 572 |             Rejected.count(Op.AssignedPhysReg) == 0) { | 
| Chris Lattner | 540fec6 | 2006-02-25 01:51:33 +0000 | [diff] [blame] | 573 |           // Yup, use the reload register that we didn't use before. | 
| Evan Cheng | 3c82cab | 2007-01-19 22:40:14 +0000 | [diff] [blame] | 574 |           unsigned NewReg = Op.AssignedPhysReg; | 
 | 575 |           Rejected.insert(PhysReg); | 
| Evan Cheng | 28bb462 | 2007-07-11 19:17:18 +0000 | [diff] [blame] | 576 |           return GetRegForReload(NewReg, MI, Spills, MaybeDeadStores, Rejected, | 
| Evan Cheng | 549f27d3 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 577 |                                  RegKills, KillOps, VRM); | 
| Chris Lattner | 540fec6 | 2006-02-25 01:51:33 +0000 | [diff] [blame] | 578 |         } else { | 
 | 579 |           // Otherwise, we might also have a problem if a previously reused | 
 | 580 |           // value aliases the new register.  If so, codegen the previous reload | 
 | 581 |           // and use this one.           | 
 | 582 |           unsigned PRRU = Op.PhysRegReused; | 
 | 583 |           const MRegisterInfo *MRI = Spills.getRegInfo(); | 
 | 584 |           if (MRI->areAliases(PRRU, PhysReg)) { | 
 | 585 |             // Okay, we found out that an alias of a reused register | 
 | 586 |             // was used.  This isn't good because it means we have | 
 | 587 |             // to undo a previous reuse. | 
 | 588 |             MachineBasicBlock *MBB = MI->getParent(); | 
 | 589 |             const TargetRegisterClass *AliasRC = | 
| Chris Lattner | 28bad08 | 2006-02-25 02:17:31 +0000 | [diff] [blame] | 590 |               MBB->getParent()->getSSARegMap()->getRegClass(Op.VirtReg); | 
 | 591 |  | 
 | 592 |             // Copy Op out of the vector and remove it, we're going to insert an | 
 | 593 |             // explicit load for it. | 
 | 594 |             ReusedOp NewOp = Op; | 
 | 595 |             Reuses.erase(Reuses.begin()+ro); | 
 | 596 |  | 
 | 597 |             // Ok, we're going to try to reload the assigned physreg into the | 
 | 598 |             // slot that we were supposed to in the first place.  However, that | 
 | 599 |             // register could hold a reuse.  Check to see if it conflicts or | 
 | 600 |             // would prefer us to use a different register. | 
 | 601 |             unsigned NewPhysReg = GetRegForReload(NewOp.AssignedPhysReg, | 
| Evan Cheng | 28bb462 | 2007-07-11 19:17:18 +0000 | [diff] [blame] | 602 |                                                   MI, Spills, MaybeDeadStores, | 
| Evan Cheng | 549f27d3 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 603 |                                               Rejected, RegKills, KillOps, VRM); | 
| Chris Lattner | 28bad08 | 2006-02-25 02:17:31 +0000 | [diff] [blame] | 604 |              | 
| Evan Cheng | 549f27d3 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 605 |             if (NewOp.StackSlotOrReMat > VirtRegMap::MAX_STACK_SLOT) { | 
 | 606 |               MRI->reMaterialize(*MBB, MI, NewPhysReg, | 
 | 607 |                                  VRM.getReMaterializedMI(NewOp.VirtReg)); | 
 | 608 |               ++NumReMats; | 
 | 609 |             } else { | 
 | 610 |               MRI->loadRegFromStackSlot(*MBB, MI, NewPhysReg, | 
 | 611 |                                         NewOp.StackSlotOrReMat, AliasRC); | 
 | 612 |               ++NumLoads; | 
 | 613 |             } | 
| Chris Lattner | 28bad08 | 2006-02-25 02:17:31 +0000 | [diff] [blame] | 614 |             Spills.ClobberPhysReg(NewPhysReg); | 
 | 615 |             Spills.ClobberPhysReg(NewOp.PhysRegReused); | 
| Chris Lattner | 540fec6 | 2006-02-25 01:51:33 +0000 | [diff] [blame] | 616 |              | 
 | 617 |             // Any stores to this stack slot are not dead anymore. | 
| Evan Cheng | 549f27d3 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 618 |             MaybeDeadStores.erase(NewOp.StackSlotOrReMat); | 
| Chris Lattner | 540fec6 | 2006-02-25 01:51:33 +0000 | [diff] [blame] | 619 |              | 
| Chris Lattner | e53f4a0 | 2006-05-04 17:52:23 +0000 | [diff] [blame] | 620 |             MI->getOperand(NewOp.Operand).setReg(NewPhysReg); | 
| Chris Lattner | 540fec6 | 2006-02-25 01:51:33 +0000 | [diff] [blame] | 621 |              | 
| Evan Cheng | 549f27d3 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 622 |             Spills.addAvailable(NewOp.StackSlotOrReMat, MI, NewPhysReg); | 
| Evan Cheng | 28bb462 | 2007-07-11 19:17:18 +0000 | [diff] [blame] | 623 |             MachineBasicBlock::iterator MII = MI; | 
 | 624 |             --MII; | 
 | 625 |             UpdateKills(*MII, RegKills, KillOps); | 
 | 626 |             DOUT << '\t' << *MII; | 
| Chris Lattner | 540fec6 | 2006-02-25 01:51:33 +0000 | [diff] [blame] | 627 |              | 
| Bill Wendling | b2b9c20 | 2006-11-17 02:09:07 +0000 | [diff] [blame] | 628 |             DOUT << "Reuse undone!\n"; | 
| Chris Lattner | 540fec6 | 2006-02-25 01:51:33 +0000 | [diff] [blame] | 629 |             --NumReused; | 
| Chris Lattner | 28bad08 | 2006-02-25 02:17:31 +0000 | [diff] [blame] | 630 |              | 
 | 631 |             // Finally, PhysReg is now available, go ahead and use it. | 
| Chris Lattner | 540fec6 | 2006-02-25 01:51:33 +0000 | [diff] [blame] | 632 |             return PhysReg; | 
 | 633 |           } | 
 | 634 |         } | 
 | 635 |       } | 
 | 636 |       return PhysReg; | 
 | 637 |     } | 
| Evan Cheng | 3c82cab | 2007-01-19 22:40:14 +0000 | [diff] [blame] | 638 |  | 
 | 639 |     /// GetRegForReload - Helper for the above GetRegForReload(). Add a | 
 | 640 |     /// 'Rejected' set to remember which registers have been considered and | 
 | 641 |     /// rejected for the reload. This avoids infinite looping in case like | 
 | 642 |     /// this: | 
 | 643 |     /// t1 := op t2, t3 | 
 | 644 |     /// t2 <- assigned r0 for use by the reload but ended up reuse r1 | 
 | 645 |     /// t3 <- assigned r1 for use by the reload but ended up reuse r0 | 
 | 646 |     /// t1 <- desires r1 | 
 | 647 |     ///       sees r1 is taken by t2, tries t2's reload register r0 | 
 | 648 |     ///       sees r0 is taken by t3, tries t3's reload register r1 | 
 | 649 |     ///       sees r1 is taken by t2, tries t2's reload register r0 ... | 
 | 650 |     unsigned GetRegForReload(unsigned PhysReg, MachineInstr *MI, | 
 | 651 |                              AvailableSpills &Spills, | 
| Evan Cheng | 28bb462 | 2007-07-11 19:17:18 +0000 | [diff] [blame] | 652 |                              std::map<int, MachineInstr*> &MaybeDeadStores, | 
 | 653 |                              BitVector &RegKills, | 
| Evan Cheng | 549f27d3 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 654 |                              std::vector<MachineOperand*> &KillOps, | 
 | 655 |                              VirtRegMap &VRM) { | 
| Chris Lattner | 08a4d5a | 2007-01-23 00:59:48 +0000 | [diff] [blame] | 656 |       SmallSet<unsigned, 8> Rejected; | 
| Evan Cheng | 28bb462 | 2007-07-11 19:17:18 +0000 | [diff] [blame] | 657 |       return GetRegForReload(PhysReg, MI, Spills, MaybeDeadStores, Rejected, | 
| Evan Cheng | 549f27d3 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 658 |                              RegKills, KillOps, VRM); | 
| Evan Cheng | 3c82cab | 2007-01-19 22:40:14 +0000 | [diff] [blame] | 659 |     } | 
| Chris Lattner | 540fec6 | 2006-02-25 01:51:33 +0000 | [diff] [blame] | 660 |   }; | 
| Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 661 | } | 
| Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 662 |  | 
| Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 663 |  | 
 | 664 | /// rewriteMBB - Keep track of which spills are available even after the | 
 | 665 | /// register allocator is done with them.  If possible, avoid reloading vregs. | 
| Evan Cheng | 549f27d3 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 666 | void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) { | 
| Bill Wendling | b2b9c20 | 2006-11-17 02:09:07 +0000 | [diff] [blame] | 667 |   DOUT << MBB.getBasicBlock()->getName() << ":\n"; | 
| Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 668 |  | 
| Chris Lattner | 66cf80f | 2006-02-03 23:13:58 +0000 | [diff] [blame] | 669 |   // Spills - Keep track of which spilled values are available in physregs so | 
 | 670 |   // that we can choose to reuse the physregs instead of emitting reloads. | 
 | 671 |   AvailableSpills Spills(MRI, TII); | 
 | 672 |    | 
| Chris Lattner | 52b25db | 2004-10-01 19:47:12 +0000 | [diff] [blame] | 673 |   // MaybeDeadStores - When we need to write a value back into a stack slot, | 
 | 674 |   // keep track of the inserted store.  If the stack slot value is never read | 
 | 675 |   // (because the value was used from some available register, for example), and | 
 | 676 |   // subsequently stored to, the original store is dead.  This map keeps track | 
 | 677 |   // of inserted stores that are not used.  If we see a subsequent store to the | 
 | 678 |   // same stack slot, the original store is deleted. | 
 | 679 |   std::map<int, MachineInstr*> MaybeDeadStores; | 
 | 680 |  | 
| Evan Cheng | 0c40d72 | 2007-07-11 05:28:39 +0000 | [diff] [blame] | 681 |   // Keep track of kill information. | 
 | 682 |   BitVector RegKills(MRI->getNumRegs()); | 
 | 683 |   std::vector<MachineOperand*>  KillOps; | 
 | 684 |   KillOps.resize(MRI->getNumRegs(), NULL); | 
 | 685 |  | 
| Evan Cheng | 6c087e5 | 2007-04-25 22:13:27 +0000 | [diff] [blame] | 686 |   MachineFunction &MF = *MBB.getParent(); | 
| Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 687 |   for (MachineBasicBlock::iterator MII = MBB.begin(), E = MBB.end(); | 
 | 688 |        MII != E; ) { | 
 | 689 |     MachineInstr &MI = *MII; | 
 | 690 |     MachineBasicBlock::iterator NextMII = MII; ++NextMII; | 
| Evan Cheng | 0c40d72 | 2007-07-11 05:28:39 +0000 | [diff] [blame] | 691 |     VirtRegMap::MI2VirtMapTy::const_iterator I, End; | 
 | 692 |  | 
 | 693 |     bool Erased = false; | 
 | 694 |     bool BackTracked = false; | 
| Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 695 |  | 
| Chris Lattner | 540fec6 | 2006-02-25 01:51:33 +0000 | [diff] [blame] | 696 |     /// ReusedOperands - Keep track of operand reuse in case we need to undo | 
 | 697 |     /// reuse. | 
| Evan Cheng | e077ef6 | 2006-11-04 00:21:55 +0000 | [diff] [blame] | 698 |     ReuseInfo ReusedOperands(MI, MRI); | 
 | 699 |  | 
 | 700 |     // Loop over all of the implicit defs, clearing them from our available | 
 | 701 |     // sets. | 
| Evan Cheng | 86facc2 | 2006-12-15 06:41:01 +0000 | [diff] [blame] | 702 |     const TargetInstrDescriptor *TID = MI.getInstrDescriptor(); | 
| Evan Cheng | 0c40d72 | 2007-07-11 05:28:39 +0000 | [diff] [blame] | 703 |     if (TID->ImplicitDefs) { | 
 | 704 |       const unsigned *ImpDef = TID->ImplicitDefs; | 
| Evan Cheng | e077ef6 | 2006-11-04 00:21:55 +0000 | [diff] [blame] | 705 |       for ( ; *ImpDef; ++ImpDef) { | 
| Evan Cheng | 6c087e5 | 2007-04-25 22:13:27 +0000 | [diff] [blame] | 706 |         MF.setPhysRegUsed(*ImpDef); | 
| Evan Cheng | e077ef6 | 2006-11-04 00:21:55 +0000 | [diff] [blame] | 707 |         ReusedOperands.markClobbered(*ImpDef); | 
 | 708 |         Spills.ClobberPhysReg(*ImpDef); | 
 | 709 |       } | 
 | 710 |     } | 
 | 711 |  | 
| Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 712 |     // Process all of the spilled uses and all non spilled reg references. | 
 | 713 |     for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) { | 
 | 714 |       MachineOperand &MO = MI.getOperand(i); | 
| Chris Lattner | 50ea01e | 2005-09-09 20:29:51 +0000 | [diff] [blame] | 715 |       if (!MO.isRegister() || MO.getReg() == 0) | 
 | 716 |         continue;   // Ignore non-register operands. | 
 | 717 |        | 
 | 718 |       if (MRegisterInfo::isPhysicalRegister(MO.getReg())) { | 
 | 719 |         // Ignore physregs for spilling, but remember that it is used by this | 
 | 720 |         // function. | 
| Evan Cheng | 6c087e5 | 2007-04-25 22:13:27 +0000 | [diff] [blame] | 721 |         MF.setPhysRegUsed(MO.getReg()); | 
| Evan Cheng | e077ef6 | 2006-11-04 00:21:55 +0000 | [diff] [blame] | 722 |         ReusedOperands.markClobbered(MO.getReg()); | 
| Chris Lattner | 50ea01e | 2005-09-09 20:29:51 +0000 | [diff] [blame] | 723 |         continue; | 
 | 724 |       } | 
 | 725 |        | 
 | 726 |       assert(MRegisterInfo::isVirtualRegister(MO.getReg()) && | 
 | 727 |              "Not a virtual or a physical register?"); | 
 | 728 |        | 
 | 729 |       unsigned VirtReg = MO.getReg(); | 
| Evan Cheng | 549f27d3 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 730 |       if (VRM.isAssignedReg(VirtReg)) { | 
| Chris Lattner | 50ea01e | 2005-09-09 20:29:51 +0000 | [diff] [blame] | 731 |         // This virtual register was assigned a physreg! | 
 | 732 |         unsigned Phys = VRM.getPhys(VirtReg); | 
| Evan Cheng | 6c087e5 | 2007-04-25 22:13:27 +0000 | [diff] [blame] | 733 |         MF.setPhysRegUsed(Phys); | 
| Evan Cheng | e077ef6 | 2006-11-04 00:21:55 +0000 | [diff] [blame] | 734 |         if (MO.isDef()) | 
 | 735 |           ReusedOperands.markClobbered(Phys); | 
| Chris Lattner | e53f4a0 | 2006-05-04 17:52:23 +0000 | [diff] [blame] | 736 |         MI.getOperand(i).setReg(Phys); | 
| Chris Lattner | 50ea01e | 2005-09-09 20:29:51 +0000 | [diff] [blame] | 737 |         continue; | 
 | 738 |       } | 
 | 739 |        | 
 | 740 |       // This virtual register is now known to be a spilled value. | 
 | 741 |       if (!MO.isUse()) | 
 | 742 |         continue;  // Handle defs in the loop below (handle use&def here though) | 
| Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 743 |  | 
| Evan Cheng | 549f27d3 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 744 |       bool DoReMat = VRM.isReMaterialized(VirtReg); | 
 | 745 |       int SSorRMId = DoReMat | 
 | 746 |         ? VRM.getReMatId(VirtReg) : VRM.getStackSlot(VirtReg); | 
| Evan Cheng | dc6be19 | 2007-08-14 05:42:54 +0000 | [diff] [blame] | 747 |       int ReuseSlot = SSorRMId; | 
| Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 748 |  | 
| Chris Lattner | 50ea01e | 2005-09-09 20:29:51 +0000 | [diff] [blame] | 749 |       // Check to see if this stack slot is available. | 
| Evan Cheng | dc6be19 | 2007-08-14 05:42:54 +0000 | [diff] [blame] | 750 |       unsigned PhysReg = Spills.getSpillSlotOrReMatPhysReg(SSorRMId); | 
 | 751 |       if (!PhysReg && DoReMat) { | 
 | 752 |         // This use is rematerializable. But perhaps the value is available in | 
 | 753 |         // stack if the definition is not deleted. If so, check if we can | 
 | 754 |         // reuse the value. | 
 | 755 |         ReuseSlot = VRM.getStackSlot(VirtReg); | 
 | 756 |         if (ReuseSlot != VirtRegMap::NO_STACK_SLOT) | 
 | 757 |           PhysReg = Spills.getSpillSlotOrReMatPhysReg(ReuseSlot); | 
 | 758 |       } | 
 | 759 |       if (PhysReg) { | 
| Chris Lattner | 2926869 | 2006-09-05 02:12:02 +0000 | [diff] [blame] | 760 |         // This spilled operand might be part of a two-address operand.  If this | 
 | 761 |         // is the case, then changing it will necessarily require changing the  | 
 | 762 |         // def part of the instruction as well.  However, in some cases, we | 
 | 763 |         // aren't allowed to modify the reused register.  If none of these cases | 
 | 764 |         // apply, reuse it. | 
 | 765 |         bool CanReuse = true; | 
| Evan Cheng | 86facc2 | 2006-12-15 06:41:01 +0000 | [diff] [blame] | 766 |         int ti = TID->getOperandConstraint(i, TOI::TIED_TO); | 
| Evan Cheng | 360c2dd | 2006-11-01 23:06:55 +0000 | [diff] [blame] | 767 |         if (ti != -1 && | 
 | 768 |             MI.getOperand(ti).isReg() &&  | 
 | 769 |             MI.getOperand(ti).getReg() == VirtReg) { | 
| Chris Lattner | 2926869 | 2006-09-05 02:12:02 +0000 | [diff] [blame] | 770 |           // Okay, we have a two address operand.  We can reuse this physreg as | 
| Evan Cheng | 3c82cab | 2007-01-19 22:40:14 +0000 | [diff] [blame] | 771 |           // long as we are allowed to clobber the value and there isn't an | 
 | 772 |           // earlier def that has already clobbered the physreg. | 
| Evan Cheng | dc6be19 | 2007-08-14 05:42:54 +0000 | [diff] [blame] | 773 |           CanReuse = Spills.canClobberPhysReg(ReuseSlot) && | 
| Evan Cheng | e077ef6 | 2006-11-04 00:21:55 +0000 | [diff] [blame] | 774 |             !ReusedOperands.isClobbered(PhysReg); | 
| Chris Lattner | 2926869 | 2006-09-05 02:12:02 +0000 | [diff] [blame] | 775 |         } | 
 | 776 |          | 
 | 777 |         if (CanReuse) { | 
| Chris Lattner | addc55a | 2006-04-28 01:46:50 +0000 | [diff] [blame] | 778 |           // If this stack slot value is already available, reuse it! | 
| Evan Cheng | dc6be19 | 2007-08-14 05:42:54 +0000 | [diff] [blame] | 779 |           if (ReuseSlot > VirtRegMap::MAX_STACK_SLOT) | 
 | 780 |             DOUT << "Reusing RM#" << ReuseSlot-VirtRegMap::MAX_STACK_SLOT-1; | 
| Evan Cheng | 2638e1a | 2007-03-20 08:13:50 +0000 | [diff] [blame] | 781 |           else | 
| Evan Cheng | dc6be19 | 2007-08-14 05:42:54 +0000 | [diff] [blame] | 782 |             DOUT << "Reusing SS#" << ReuseSlot; | 
| Evan Cheng | 2638e1a | 2007-03-20 08:13:50 +0000 | [diff] [blame] | 783 |           DOUT << " from physreg " | 
| Bill Wendling | b2b9c20 | 2006-11-17 02:09:07 +0000 | [diff] [blame] | 784 |                << MRI->getName(PhysReg) << " for vreg" | 
 | 785 |                << VirtReg <<" instead of reloading into physreg " | 
 | 786 |                << MRI->getName(VRM.getPhys(VirtReg)) << "\n"; | 
| Chris Lattner | e53f4a0 | 2006-05-04 17:52:23 +0000 | [diff] [blame] | 787 |           MI.getOperand(i).setReg(PhysReg); | 
| Chris Lattner | addc55a | 2006-04-28 01:46:50 +0000 | [diff] [blame] | 788 |  | 
 | 789 |           // The only technical detail we have is that we don't know that | 
 | 790 |           // PhysReg won't be clobbered by a reloaded stack slot that occurs | 
 | 791 |           // later in the instruction.  In particular, consider 'op V1, V2'. | 
 | 792 |           // If V1 is available in physreg R0, we would choose to reuse it | 
 | 793 |           // here, instead of reloading it into the register the allocator | 
 | 794 |           // indicated (say R1).  However, V2 might have to be reloaded | 
 | 795 |           // later, and it might indicate that it needs to live in R0.  When | 
 | 796 |           // this occurs, we need to have information available that | 
 | 797 |           // indicates it is safe to use R1 for the reload instead of R0. | 
 | 798 |           // | 
 | 799 |           // To further complicate matters, we might conflict with an alias, | 
 | 800 |           // or R0 and R1 might not be compatible with each other.  In this | 
 | 801 |           // case, we actually insert a reload for V1 in R1, ensuring that | 
 | 802 |           // we can get at R0 or its alias. | 
| Evan Cheng | dc6be19 | 2007-08-14 05:42:54 +0000 | [diff] [blame] | 803 |           ReusedOperands.addReuse(i, ReuseSlot, PhysReg, | 
| Chris Lattner | addc55a | 2006-04-28 01:46:50 +0000 | [diff] [blame] | 804 |                                   VRM.getPhys(VirtReg), VirtReg); | 
| Evan Cheng | e077ef6 | 2006-11-04 00:21:55 +0000 | [diff] [blame] | 805 |           if (ti != -1) | 
 | 806 |             // Only mark it clobbered if this is a use&def operand. | 
 | 807 |             ReusedOperands.markClobbered(PhysReg); | 
| Chris Lattner | addc55a | 2006-04-28 01:46:50 +0000 | [diff] [blame] | 808 |           ++NumReused; | 
 | 809 |           continue; | 
 | 810 |         } | 
 | 811 |          | 
 | 812 |         // Otherwise we have a situation where we have a two-address instruction | 
 | 813 |         // whose mod/ref operand needs to be reloaded.  This reload is already | 
 | 814 |         // available in some register "PhysReg", but if we used PhysReg as the | 
 | 815 |         // operand to our 2-addr instruction, the instruction would modify | 
 | 816 |         // PhysReg.  This isn't cool if something later uses PhysReg and expects | 
 | 817 |         // to get its initial value. | 
| Chris Lattner | 50ea01e | 2005-09-09 20:29:51 +0000 | [diff] [blame] | 818 |         // | 
| Chris Lattner | addc55a | 2006-04-28 01:46:50 +0000 | [diff] [blame] | 819 |         // To avoid this problem, and to avoid doing a load right after a store, | 
 | 820 |         // we emit a copy from PhysReg into the designated register for this | 
 | 821 |         // operand. | 
 | 822 |         unsigned DesignatedReg = VRM.getPhys(VirtReg); | 
 | 823 |         assert(DesignatedReg && "Must map virtreg to physreg!"); | 
 | 824 |  | 
 | 825 |         // Note that, if we reused a register for a previous operand, the | 
 | 826 |         // register we want to reload into might not actually be | 
 | 827 |         // available.  If this occurs, use the register indicated by the | 
 | 828 |         // reuser. | 
 | 829 |         if (ReusedOperands.hasReuses()) | 
 | 830 |           DesignatedReg = ReusedOperands.GetRegForReload(DesignatedReg, &MI,  | 
| Evan Cheng | 549f27d3 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 831 |                                Spills, MaybeDeadStores, RegKills, KillOps, VRM); | 
| Chris Lattner | addc55a | 2006-04-28 01:46:50 +0000 | [diff] [blame] | 832 |          | 
| Chris Lattner | ba1fc3d | 2006-04-28 04:43:18 +0000 | [diff] [blame] | 833 |         // If the mapped designated register is actually the physreg we have | 
 | 834 |         // incoming, we don't need to inserted a dead copy. | 
 | 835 |         if (DesignatedReg == PhysReg) { | 
 | 836 |           // If this stack slot value is already available, reuse it! | 
| Evan Cheng | dc6be19 | 2007-08-14 05:42:54 +0000 | [diff] [blame] | 837 |           if (ReuseSlot > VirtRegMap::MAX_STACK_SLOT) | 
 | 838 |             DOUT << "Reusing RM#" << ReuseSlot-VirtRegMap::MAX_STACK_SLOT-1; | 
| Evan Cheng | 2638e1a | 2007-03-20 08:13:50 +0000 | [diff] [blame] | 839 |           else | 
| Evan Cheng | dc6be19 | 2007-08-14 05:42:54 +0000 | [diff] [blame] | 840 |             DOUT << "Reusing SS#" << ReuseSlot; | 
| Evan Cheng | 2638e1a | 2007-03-20 08:13:50 +0000 | [diff] [blame] | 841 |           DOUT << " from physreg " << MRI->getName(PhysReg) << " for vreg" | 
| Bill Wendling | b2b9c20 | 2006-11-17 02:09:07 +0000 | [diff] [blame] | 842 |                << VirtReg | 
 | 843 |                << " instead of reloading into same physreg.\n"; | 
| Chris Lattner | e53f4a0 | 2006-05-04 17:52:23 +0000 | [diff] [blame] | 844 |           MI.getOperand(i).setReg(PhysReg); | 
| Evan Cheng | e077ef6 | 2006-11-04 00:21:55 +0000 | [diff] [blame] | 845 |           ReusedOperands.markClobbered(PhysReg); | 
| Chris Lattner | ba1fc3d | 2006-04-28 04:43:18 +0000 | [diff] [blame] | 846 |           ++NumReused; | 
 | 847 |           continue; | 
 | 848 |         } | 
 | 849 |          | 
| Evan Cheng | 6c087e5 | 2007-04-25 22:13:27 +0000 | [diff] [blame] | 850 |         const TargetRegisterClass* RC = MF.getSSARegMap()->getRegClass(VirtReg); | 
 | 851 |         MF.setPhysRegUsed(DesignatedReg); | 
| Evan Cheng | e077ef6 | 2006-11-04 00:21:55 +0000 | [diff] [blame] | 852 |         ReusedOperands.markClobbered(DesignatedReg); | 
| Chris Lattner | addc55a | 2006-04-28 01:46:50 +0000 | [diff] [blame] | 853 |         MRI->copyRegToReg(MBB, &MI, DesignatedReg, PhysReg, RC); | 
| Evan Cheng | de4e942 | 2007-02-25 09:51:27 +0000 | [diff] [blame] | 854 |  | 
| Evan Cheng | 6b44809 | 2007-03-02 08:52:00 +0000 | [diff] [blame] | 855 |         MachineInstr *CopyMI = prior(MII); | 
| Evan Cheng | 0c40d72 | 2007-07-11 05:28:39 +0000 | [diff] [blame] | 856 |         UpdateKills(*CopyMI, RegKills, KillOps); | 
| Evan Cheng | de4e942 | 2007-02-25 09:51:27 +0000 | [diff] [blame] | 857 |  | 
| Chris Lattner | addc55a | 2006-04-28 01:46:50 +0000 | [diff] [blame] | 858 |         // This invalidates DesignatedReg. | 
 | 859 |         Spills.ClobberPhysReg(DesignatedReg); | 
 | 860 |          | 
| Evan Cheng | dc6be19 | 2007-08-14 05:42:54 +0000 | [diff] [blame] | 861 |         Spills.addAvailable(ReuseSlot, &MI, DesignatedReg); | 
| Chris Lattner | e53f4a0 | 2006-05-04 17:52:23 +0000 | [diff] [blame] | 862 |         MI.getOperand(i).setReg(DesignatedReg); | 
| Bill Wendling | b2b9c20 | 2006-11-17 02:09:07 +0000 | [diff] [blame] | 863 |         DOUT << '\t' << *prior(MII); | 
| Chris Lattner | 50ea01e | 2005-09-09 20:29:51 +0000 | [diff] [blame] | 864 |         ++NumReused; | 
 | 865 |         continue; | 
 | 866 |       } | 
 | 867 |        | 
 | 868 |       // Otherwise, reload it and remember that we have it. | 
 | 869 |       PhysReg = VRM.getPhys(VirtReg); | 
| Chris Lattner | 172c362 | 2006-01-04 06:47:48 +0000 | [diff] [blame] | 870 |       assert(PhysReg && "Must map virtreg to physreg!"); | 
| Evan Cheng | 6c087e5 | 2007-04-25 22:13:27 +0000 | [diff] [blame] | 871 |       const TargetRegisterClass* RC = MF.getSSARegMap()->getRegClass(VirtReg); | 
| Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 872 |  | 
| Chris Lattner | 50ea01e | 2005-09-09 20:29:51 +0000 | [diff] [blame] | 873 |       // Note that, if we reused a register for a previous operand, the | 
 | 874 |       // register we want to reload into might not actually be | 
 | 875 |       // available.  If this occurs, use the register indicated by the | 
 | 876 |       // reuser. | 
| Chris Lattner | 540fec6 | 2006-02-25 01:51:33 +0000 | [diff] [blame] | 877 |       if (ReusedOperands.hasReuses()) | 
 | 878 |         PhysReg = ReusedOperands.GetRegForReload(PhysReg, &MI,  | 
| Evan Cheng | 549f27d3 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 879 |                                Spills, MaybeDeadStores, RegKills, KillOps, VRM); | 
| Chris Lattner | 540fec6 | 2006-02-25 01:51:33 +0000 | [diff] [blame] | 880 |        | 
| Evan Cheng | 6c087e5 | 2007-04-25 22:13:27 +0000 | [diff] [blame] | 881 |       MF.setPhysRegUsed(PhysReg); | 
| Evan Cheng | e077ef6 | 2006-11-04 00:21:55 +0000 | [diff] [blame] | 882 |       ReusedOperands.markClobbered(PhysReg); | 
| Evan Cheng | 549f27d3 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 883 |       if (DoReMat) { | 
| Evan Cheng | 2638e1a | 2007-03-20 08:13:50 +0000 | [diff] [blame] | 884 |         MRI->reMaterialize(MBB, &MI, PhysReg, VRM.getReMaterializedMI(VirtReg)); | 
| Evan Cheng | 9193514 | 2007-04-04 07:40:01 +0000 | [diff] [blame] | 885 |         ++NumReMats; | 
 | 886 |       } else { | 
| Evan Cheng | 549f27d3 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 887 |         MRI->loadRegFromStackSlot(MBB, &MI, PhysReg, SSorRMId, RC); | 
| Evan Cheng | 9193514 | 2007-04-04 07:40:01 +0000 | [diff] [blame] | 888 |         ++NumLoads; | 
 | 889 |       } | 
| Chris Lattner | 50ea01e | 2005-09-09 20:29:51 +0000 | [diff] [blame] | 890 |       // This invalidates PhysReg. | 
| Chris Lattner | 66cf80f | 2006-02-03 23:13:58 +0000 | [diff] [blame] | 891 |       Spills.ClobberPhysReg(PhysReg); | 
| Chris Lattner | 50ea01e | 2005-09-09 20:29:51 +0000 | [diff] [blame] | 892 |  | 
 | 893 |       // Any stores to this stack slot are not dead anymore. | 
| Evan Cheng | 549f27d3 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 894 |       if (!DoReMat) | 
 | 895 |         MaybeDeadStores.erase(SSorRMId); | 
 | 896 |       Spills.addAvailable(SSorRMId, &MI, PhysReg); | 
| Evan Cheng | de4e942 | 2007-02-25 09:51:27 +0000 | [diff] [blame] | 897 |       // Assumes this is the last use. IsKill will be unset if reg is reused | 
 | 898 |       // unless it's a two-address operand. | 
 | 899 |       if (TID->getOperandConstraint(i, TOI::TIED_TO) == -1) | 
 | 900 |         MI.getOperand(i).setIsKill(); | 
| Chris Lattner | e53f4a0 | 2006-05-04 17:52:23 +0000 | [diff] [blame] | 901 |       MI.getOperand(i).setReg(PhysReg); | 
| Evan Cheng | 0c40d72 | 2007-07-11 05:28:39 +0000 | [diff] [blame] | 902 |       UpdateKills(*prior(MII), RegKills, KillOps); | 
| Bill Wendling | b2b9c20 | 2006-11-17 02:09:07 +0000 | [diff] [blame] | 903 |       DOUT << '\t' << *prior(MII); | 
| Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 904 |     } | 
 | 905 |  | 
| Bill Wendling | b2b9c20 | 2006-11-17 02:09:07 +0000 | [diff] [blame] | 906 |     DOUT << '\t' << MI; | 
| Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 907 |  | 
| Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 908 |     // If we have folded references to memory operands, make sure we clear all | 
 | 909 |     // physical registers that may contain the value of the spilled virtual | 
 | 910 |     // register | 
| Chris Lattner | 8f1d640 | 2005-01-14 15:54:24 +0000 | [diff] [blame] | 911 |     for (tie(I, End) = VRM.getFoldedVirts(&MI); I != End; ++I) { | 
| Bill Wendling | b2b9c20 | 2006-11-17 02:09:07 +0000 | [diff] [blame] | 912 |       DOUT << "Folded vreg: " << I->second.first << "  MR: " | 
 | 913 |            << I->second.second; | 
| Chris Lattner | bec6a9e | 2004-10-01 23:15:36 +0000 | [diff] [blame] | 914 |       unsigned VirtReg = I->second.first; | 
 | 915 |       VirtRegMap::ModRef MR = I->second.second; | 
| Evan Cheng | 549f27d3 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 916 |       if (VRM.isAssignedReg(VirtReg)) { | 
| Bill Wendling | b2b9c20 | 2006-11-17 02:09:07 +0000 | [diff] [blame] | 917 |         DOUT << ": No stack slot!\n"; | 
| Chris Lattner | cea8688 | 2005-09-19 06:56:21 +0000 | [diff] [blame] | 918 |         continue; | 
 | 919 |       } | 
 | 920 |       int SS = VRM.getStackSlot(VirtReg); | 
| Bill Wendling | b2b9c20 | 2006-11-17 02:09:07 +0000 | [diff] [blame] | 921 |       DOUT << " - StackSlot: " << SS << "\n"; | 
| Chris Lattner | cea8688 | 2005-09-19 06:56:21 +0000 | [diff] [blame] | 922 |        | 
 | 923 |       // If this folded instruction is just a use, check to see if it's a | 
 | 924 |       // straight load from the virt reg slot. | 
 | 925 |       if ((MR & VirtRegMap::isRef) && !(MR & VirtRegMap::isMod)) { | 
 | 926 |         int FrameIdx; | 
| Chris Lattner | 4083960 | 2006-02-02 20:12:32 +0000 | [diff] [blame] | 927 |         if (unsigned DestReg = TII->isLoadFromStackSlot(&MI, FrameIdx)) { | 
| Chris Lattner | 6ec3626 | 2006-10-12 17:45:38 +0000 | [diff] [blame] | 928 |           if (FrameIdx == SS) { | 
 | 929 |             // If this spill slot is available, turn it into a copy (or nothing) | 
 | 930 |             // instead of leaving it as a load! | 
| Evan Cheng | 549f27d3 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 931 |             if (unsigned InReg = Spills.getSpillSlotOrReMatPhysReg(SS)) { | 
| Bill Wendling | b2b9c20 | 2006-11-17 02:09:07 +0000 | [diff] [blame] | 932 |               DOUT << "Promoted Load To Copy: " << MI; | 
| Chris Lattner | 6ec3626 | 2006-10-12 17:45:38 +0000 | [diff] [blame] | 933 |               if (DestReg != InReg) { | 
 | 934 |                 MRI->copyRegToReg(MBB, &MI, DestReg, InReg, | 
 | 935 |                                   MF.getSSARegMap()->getRegClass(VirtReg)); | 
 | 936 |                 // Revisit the copy so we make sure to notice the effects of the | 
 | 937 |                 // operation on the destreg (either needing to RA it if it's  | 
 | 938 |                 // virtual or needing to clobber any values if it's physical). | 
 | 939 |                 NextMII = &MI; | 
 | 940 |                 --NextMII;  // backtrack to the copy. | 
| Evan Cheng | 0c40d72 | 2007-07-11 05:28:39 +0000 | [diff] [blame] | 941 |                 BackTracked = true; | 
| Evan Cheng | de4e942 | 2007-02-25 09:51:27 +0000 | [diff] [blame] | 942 |               } else | 
 | 943 |                 DOUT << "Removing now-noop copy: " << MI; | 
 | 944 |  | 
| Chris Lattner | 6ec3626 | 2006-10-12 17:45:38 +0000 | [diff] [blame] | 945 |               VRM.RemoveFromFoldedVirtMap(&MI); | 
 | 946 |               MBB.erase(&MI); | 
| Evan Cheng | 0c40d72 | 2007-07-11 05:28:39 +0000 | [diff] [blame] | 947 |               Erased = true; | 
| Chris Lattner | 6ec3626 | 2006-10-12 17:45:38 +0000 | [diff] [blame] | 948 |               goto ProcessNextInst; | 
| Chris Lattner | cea8688 | 2005-09-19 06:56:21 +0000 | [diff] [blame] | 949 |             } | 
| Chris Lattner | cea8688 | 2005-09-19 06:56:21 +0000 | [diff] [blame] | 950 |           } | 
 | 951 |         } | 
 | 952 |       } | 
 | 953 |  | 
 | 954 |       // If this reference is not a use, any previous store is now dead. | 
 | 955 |       // Otherwise, the store to this stack slot is not dead anymore. | 
 | 956 |       std::map<int, MachineInstr*>::iterator MDSI = MaybeDeadStores.find(SS); | 
 | 957 |       if (MDSI != MaybeDeadStores.end()) { | 
 | 958 |         if (MR & VirtRegMap::isRef)   // Previous store is not dead. | 
 | 959 |           MaybeDeadStores.erase(MDSI); | 
 | 960 |         else { | 
 | 961 |           // If we get here, the store is dead, nuke it now. | 
| Chris Lattner | 35f2705 | 2006-05-01 21:16:03 +0000 | [diff] [blame] | 962 |           assert(VirtRegMap::isMod && "Can't be modref!"); | 
| Bill Wendling | b2b9c20 | 2006-11-17 02:09:07 +0000 | [diff] [blame] | 963 |           DOUT << "Removed dead store:\t" << *MDSI->second; | 
| Evan Cheng | 0c40d72 | 2007-07-11 05:28:39 +0000 | [diff] [blame] | 964 |           InvalidateKills(*MDSI->second, RegKills, KillOps); | 
| Chris Lattner | 35f2705 | 2006-05-01 21:16:03 +0000 | [diff] [blame] | 965 |           MBB.erase(MDSI->second); | 
| Chris Lattner | 229924a | 2006-05-01 22:03:24 +0000 | [diff] [blame] | 966 |           VRM.RemoveFromFoldedVirtMap(MDSI->second); | 
| Chris Lattner | 35f2705 | 2006-05-01 21:16:03 +0000 | [diff] [blame] | 967 |           MaybeDeadStores.erase(MDSI); | 
 | 968 |           ++NumDSE; | 
| Chris Lattner | cea8688 | 2005-09-19 06:56:21 +0000 | [diff] [blame] | 969 |         } | 
 | 970 |       } | 
 | 971 |  | 
 | 972 |       // If the spill slot value is available, and this is a new definition of | 
 | 973 |       // the value, the value is not available anymore. | 
 | 974 |       if (MR & VirtRegMap::isMod) { | 
| Chris Lattner | 07cf141 | 2006-02-03 00:36:31 +0000 | [diff] [blame] | 975 |         // Notice that the value in this stack slot has been modified. | 
| Evan Cheng | 549f27d3 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 976 |         Spills.ModifyStackSlotOrReMat(SS); | 
| Chris Lattner | cd81639 | 2006-02-02 23:29:36 +0000 | [diff] [blame] | 977 |          | 
 | 978 |         // If this is *just* a mod of the value, check to see if this is just a | 
 | 979 |         // store to the spill slot (i.e. the spill got merged into the copy). If | 
 | 980 |         // so, realize that the vreg is available now, and add the store to the | 
 | 981 |         // MaybeDeadStore info. | 
 | 982 |         int StackSlot; | 
 | 983 |         if (!(MR & VirtRegMap::isRef)) { | 
 | 984 |           if (unsigned SrcReg = TII->isStoreToStackSlot(&MI, StackSlot)) { | 
 | 985 |             assert(MRegisterInfo::isPhysicalRegister(SrcReg) && | 
 | 986 |                    "Src hasn't been allocated yet?"); | 
| Chris Lattner | 07cf141 | 2006-02-03 00:36:31 +0000 | [diff] [blame] | 987 |             // Okay, this is certainly a store of SrcReg to [StackSlot].  Mark | 
| Chris Lattner | cd81639 | 2006-02-02 23:29:36 +0000 | [diff] [blame] | 988 |             // this as a potentially dead store in case there is a subsequent | 
 | 989 |             // store into the stack slot without a read from it. | 
 | 990 |             MaybeDeadStores[StackSlot] = &MI; | 
 | 991 |  | 
| Chris Lattner | cd81639 | 2006-02-02 23:29:36 +0000 | [diff] [blame] | 992 |             // If the stack slot value was previously available in some other | 
 | 993 |             // register, change it now.  Otherwise, make the register available, | 
 | 994 |             // in PhysReg. | 
| Evan Cheng | 91e2390 | 2007-02-23 01:13:26 +0000 | [diff] [blame] | 995 |             Spills.addAvailable(StackSlot, &MI, SrcReg, false/*don't clobber*/); | 
| Chris Lattner | cd81639 | 2006-02-02 23:29:36 +0000 | [diff] [blame] | 996 |           } | 
 | 997 |         } | 
| Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 998 |       } | 
| Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 999 |     } | 
 | 1000 |  | 
| Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 1001 |     // Process all of the spilled defs. | 
 | 1002 |     for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) { | 
 | 1003 |       MachineOperand &MO = MI.getOperand(i); | 
 | 1004 |       if (MO.isRegister() && MO.getReg() && MO.isDef()) { | 
 | 1005 |         unsigned VirtReg = MO.getReg(); | 
| Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 1006 |  | 
| Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 1007 |         if (!MRegisterInfo::isVirtualRegister(VirtReg)) { | 
| Chris Lattner | 2926869 | 2006-09-05 02:12:02 +0000 | [diff] [blame] | 1008 |           // Check to see if this is a noop copy.  If so, eliminate the | 
 | 1009 |           // instruction before considering the dest reg to be changed. | 
 | 1010 |           unsigned Src, Dst; | 
 | 1011 |           if (TII->isMoveInstr(MI, Src, Dst) && Src == Dst) { | 
 | 1012 |             ++NumDCE; | 
| Bill Wendling | b2b9c20 | 2006-11-17 02:09:07 +0000 | [diff] [blame] | 1013 |             DOUT << "Removing now-noop copy: " << MI; | 
| Chris Lattner | 2926869 | 2006-09-05 02:12:02 +0000 | [diff] [blame] | 1014 |             MBB.erase(&MI); | 
| Evan Cheng | 0c40d72 | 2007-07-11 05:28:39 +0000 | [diff] [blame] | 1015 |             Erased = true; | 
| Chris Lattner | 2926869 | 2006-09-05 02:12:02 +0000 | [diff] [blame] | 1016 |             VRM.RemoveFromFoldedVirtMap(&MI); | 
| Evan Cheng | 7a0d51c | 2006-12-14 07:54:05 +0000 | [diff] [blame] | 1017 |             Spills.disallowClobberPhysReg(VirtReg); | 
| Chris Lattner | 2926869 | 2006-09-05 02:12:02 +0000 | [diff] [blame] | 1018 |             goto ProcessNextInst; | 
| Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 1019 |           } | 
| Chris Lattner | 6ec3626 | 2006-10-12 17:45:38 +0000 | [diff] [blame] | 1020 |            | 
 | 1021 |           // If it's not a no-op copy, it clobbers the value in the destreg. | 
| Chris Lattner | 2926869 | 2006-09-05 02:12:02 +0000 | [diff] [blame] | 1022 |           Spills.ClobberPhysReg(VirtReg); | 
| Evan Cheng | e077ef6 | 2006-11-04 00:21:55 +0000 | [diff] [blame] | 1023 |           ReusedOperands.markClobbered(VirtReg); | 
| Chris Lattner | 6ec3626 | 2006-10-12 17:45:38 +0000 | [diff] [blame] | 1024 |   | 
 | 1025 |           // Check to see if this instruction is a load from a stack slot into | 
 | 1026 |           // a register.  If so, this provides the stack slot value in the reg. | 
 | 1027 |           int FrameIdx; | 
 | 1028 |           if (unsigned DestReg = TII->isLoadFromStackSlot(&MI, FrameIdx)) { | 
 | 1029 |             assert(DestReg == VirtReg && "Unknown load situation!"); | 
 | 1030 |              | 
 | 1031 |             // Otherwise, if it wasn't available, remember that it is now! | 
| Evan Cheng | 91e2390 | 2007-02-23 01:13:26 +0000 | [diff] [blame] | 1032 |             Spills.addAvailable(FrameIdx, &MI, DestReg); | 
| Chris Lattner | 6ec3626 | 2006-10-12 17:45:38 +0000 | [diff] [blame] | 1033 |             goto ProcessNextInst; | 
 | 1034 |           } | 
 | 1035 |              | 
| Chris Lattner | 2926869 | 2006-09-05 02:12:02 +0000 | [diff] [blame] | 1036 |           continue; | 
| Misha Brukman | edf128a | 2005-04-21 22:36:52 +0000 | [diff] [blame] | 1037 |         } | 
| Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 1038 |  | 
| Chris Lattner | 84e752a | 2006-02-03 03:06:49 +0000 | [diff] [blame] | 1039 |         // The only vregs left are stack slot definitions. | 
 | 1040 |         int StackSlot = VRM.getStackSlot(VirtReg); | 
| Evan Cheng | 6c087e5 | 2007-04-25 22:13:27 +0000 | [diff] [blame] | 1041 |         const TargetRegisterClass *RC = MF.getSSARegMap()->getRegClass(VirtReg); | 
| Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 1042 |  | 
| Chris Lattner | 2926869 | 2006-09-05 02:12:02 +0000 | [diff] [blame] | 1043 |         // If this def is part of a two-address operand, make sure to execute | 
 | 1044 |         // the store from the correct physical register. | 
 | 1045 |         unsigned PhysReg; | 
| Evan Cheng | cc22a7a | 2006-12-08 18:45:48 +0000 | [diff] [blame] | 1046 |         int TiedOp = MI.getInstrDescriptor()->findTiedToSrcOperand(i); | 
| Evan Cheng | 360c2dd | 2006-11-01 23:06:55 +0000 | [diff] [blame] | 1047 |         if (TiedOp != -1) | 
 | 1048 |           PhysReg = MI.getOperand(TiedOp).getReg(); | 
| Evan Cheng | e077ef6 | 2006-11-04 00:21:55 +0000 | [diff] [blame] | 1049 |         else { | 
| Chris Lattner | 2926869 | 2006-09-05 02:12:02 +0000 | [diff] [blame] | 1050 |           PhysReg = VRM.getPhys(VirtReg); | 
| Evan Cheng | e077ef6 | 2006-11-04 00:21:55 +0000 | [diff] [blame] | 1051 |           if (ReusedOperands.isClobbered(PhysReg)) { | 
 | 1052 |             // Another def has taken the assigned physreg. It must have been a | 
 | 1053 |             // use&def which got it due to reuse. Undo the reuse! | 
 | 1054 |             PhysReg = ReusedOperands.GetRegForReload(PhysReg, &MI,  | 
| Evan Cheng | 549f27d3 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 1055 |                                Spills, MaybeDeadStores, RegKills, KillOps, VRM); | 
| Evan Cheng | e077ef6 | 2006-11-04 00:21:55 +0000 | [diff] [blame] | 1056 |           } | 
 | 1057 |         } | 
| Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 1058 |  | 
| Evan Cheng | 6c087e5 | 2007-04-25 22:13:27 +0000 | [diff] [blame] | 1059 |         MF.setPhysRegUsed(PhysReg); | 
| Evan Cheng | e077ef6 | 2006-11-04 00:21:55 +0000 | [diff] [blame] | 1060 |         ReusedOperands.markClobbered(PhysReg); | 
| Chris Lattner | 84e752a | 2006-02-03 03:06:49 +0000 | [diff] [blame] | 1061 |         MRI->storeRegToStackSlot(MBB, next(MII), PhysReg, StackSlot, RC); | 
| Bill Wendling | b2b9c20 | 2006-11-17 02:09:07 +0000 | [diff] [blame] | 1062 |         DOUT << "Store:\t" << *next(MII); | 
| Chris Lattner | e53f4a0 | 2006-05-04 17:52:23 +0000 | [diff] [blame] | 1063 |         MI.getOperand(i).setReg(PhysReg); | 
| Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 1064 |  | 
| Chris Lattner | 84e752a | 2006-02-03 03:06:49 +0000 | [diff] [blame] | 1065 |         // If there is a dead store to this stack slot, nuke it now. | 
 | 1066 |         MachineInstr *&LastStore = MaybeDeadStores[StackSlot]; | 
 | 1067 |         if (LastStore) { | 
| Bill Wendling | b2b9c20 | 2006-11-17 02:09:07 +0000 | [diff] [blame] | 1068 |           DOUT << "Removed dead store:\t" << *LastStore; | 
| Chris Lattner | 84e752a | 2006-02-03 03:06:49 +0000 | [diff] [blame] | 1069 |           ++NumDSE; | 
| Evan Cheng | 0c40d72 | 2007-07-11 05:28:39 +0000 | [diff] [blame] | 1070 |           InvalidateKills(*LastStore, RegKills, KillOps); | 
| Chris Lattner | 84e752a | 2006-02-03 03:06:49 +0000 | [diff] [blame] | 1071 |           MBB.erase(LastStore); | 
| Chris Lattner | 229924a | 2006-05-01 22:03:24 +0000 | [diff] [blame] | 1072 |           VRM.RemoveFromFoldedVirtMap(LastStore); | 
| Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 1073 |         } | 
| Chris Lattner | 84e752a | 2006-02-03 03:06:49 +0000 | [diff] [blame] | 1074 |         LastStore = next(MII); | 
 | 1075 |  | 
 | 1076 |         // If the stack slot value was previously available in some other | 
 | 1077 |         // register, change it now.  Otherwise, make the register available, | 
 | 1078 |         // in PhysReg. | 
| Evan Cheng | 549f27d3 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 1079 |         Spills.ModifyStackSlotOrReMat(StackSlot); | 
| Chris Lattner | 66cf80f | 2006-02-03 23:13:58 +0000 | [diff] [blame] | 1080 |         Spills.ClobberPhysReg(PhysReg); | 
| Evan Cheng | 91e2390 | 2007-02-23 01:13:26 +0000 | [diff] [blame] | 1081 |         Spills.addAvailable(StackSlot, LastStore, PhysReg); | 
| Chris Lattner | 84e752a | 2006-02-03 03:06:49 +0000 | [diff] [blame] | 1082 |         ++NumStores; | 
| Evan Cheng | f50d09a | 2007-02-08 06:04:54 +0000 | [diff] [blame] | 1083 |  | 
 | 1084 |         // Check to see if this is a noop copy.  If so, eliminate the | 
 | 1085 |         // instruction before considering the dest reg to be changed. | 
 | 1086 |         { | 
 | 1087 |           unsigned Src, Dst; | 
 | 1088 |           if (TII->isMoveInstr(MI, Src, Dst) && Src == Dst) { | 
 | 1089 |             ++NumDCE; | 
 | 1090 |             DOUT << "Removing now-noop copy: " << MI; | 
 | 1091 |             MBB.erase(&MI); | 
| Evan Cheng | 0c40d72 | 2007-07-11 05:28:39 +0000 | [diff] [blame] | 1092 |             Erased = true; | 
| Evan Cheng | f50d09a | 2007-02-08 06:04:54 +0000 | [diff] [blame] | 1093 |             VRM.RemoveFromFoldedVirtMap(&MI); | 
| Evan Cheng | 28bb462 | 2007-07-11 19:17:18 +0000 | [diff] [blame] | 1094 |             UpdateKills(*LastStore, RegKills, KillOps); | 
| Evan Cheng | f50d09a | 2007-02-08 06:04:54 +0000 | [diff] [blame] | 1095 |             goto ProcessNextInst; | 
 | 1096 |           } | 
 | 1097 |         }         | 
| Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 1098 |       } | 
 | 1099 |     } | 
| Chris Lattner | cea8688 | 2005-09-19 06:56:21 +0000 | [diff] [blame] | 1100 |   ProcessNextInst: | 
| Evan Cheng | 0c40d72 | 2007-07-11 05:28:39 +0000 | [diff] [blame] | 1101 |     if (!Erased && !BackTracked) | 
 | 1102 |       for (MachineBasicBlock::iterator II = MI; II != NextMII; ++II) | 
 | 1103 |         UpdateKills(*II, RegKills, KillOps); | 
| Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 1104 |     MII = NextMII; | 
 | 1105 |   } | 
| Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 1106 | } | 
 | 1107 |  | 
| Chris Lattner | f7da2c7 | 2006-08-24 22:43:55 +0000 | [diff] [blame] | 1108 |  | 
| Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 1109 | llvm::Spiller* llvm::createSpiller() { | 
 | 1110 |   switch (SpillerOpt) { | 
 | 1111 |   default: assert(0 && "Unreachable!"); | 
 | 1112 |   case local: | 
 | 1113 |     return new LocalSpiller(); | 
 | 1114 |   case simple: | 
 | 1115 |     return new SimpleSpiller(); | 
 | 1116 |   } | 
| Alkis Evlogimenos | 0d6c5b6 | 2004-02-24 08:58:30 +0000 | [diff] [blame] | 1117 | } |