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gerrit-public.fairphone.software / fp2-dev / platform / external / llvm / 05fc9664018f867b2184589e8a04cc8f056cfa16 / lib / Target / ARM / ARMInstrInfo.h
  1. 05fc966 Revert 56176. All those instruction formats are still needed. by Evan Cheng · 17 years ago
  2. a964b7d Eliminate unnecessary instruction formats. by Evan Cheng · 17 years ago
  3. 5f1db7b Rewrite address mode 1 code emission routines. by Evan Cheng · 17 years ago
  4. 940f83e Make TargetInstrInfo::copyRegToReg return a bool indicating whether the copy requested by Owen Anderson · 17 years ago
  5. 44eb65c Convert uses of std::vector in TargetInstrInfo to SmallVector. This change had to be propoagated down into all the targets and up into all clients of this API. by Owen Anderson · 17 years ago
  6. f660c17 Make LiveVariables even more optional, by making it optional in the call to TargetInstrInfo::convertToThreeAddressInstruction by Owen Anderson · 17 years ago
  7. c9f5f3f Change target-specific classes to use more precise static types. by Dan Gohman · 17 years ago
  8. 52e724a Infrastructure for getting the machine code size of a function and an instruction. X86, PowerPC and ARM are implemented by Nicolas Geoffray · 17 years ago
  9. ca1267c Move reMaterialize() from TargetRegisterInfo to TargetInstrInfo. by Evan Cheng · 17 years ago
  10. 950a4c4 Add explicit keywords. by Dan Gohman · 17 years ago
  11. 6f0d024 Rename MRegisterInfo to TargetRegisterInfo. by Dan Gohman · 18 years ago
  12. 5fd79d0 It's not always safe to fold movsd into xorpd, etc. Check the alignment of the load address first to make sure it's 16 byte aligned. by Evan Cheng · 18 years ago
  13. 43dbe05 Move even more functionality from MRegisterInfo into TargetInstrInfo. by Owen Anderson · 18 years ago
  14. d94b6a1 Move some more functionality from MRegisterInfo to TargetInstrInfo. by Owen Anderson · 18 years ago
  15. f6372aa Move some more instruction creation methods from RegisterInfo into InstrInfo. by Owen Anderson · 18 years ago
  16. 6410552 Fix a problem where lib/Target/TargetInstrInfo.h would include and use by Chris Lattner · 18 years ago
  17. d10fd97 Move copyRegToReg from MRegisterInfo to TargetInstrInfo. This is part of the by Owen Anderson · 18 years ago
  18. 4ee451d Remove attribution from file headers, per discussion on llvmdev. by Chris Lattner · 18 years ago
  19. a4c7910 Fix a misnamed parameter. by Christopher Lamb · 18 years ago
  20. 8c13263 Instruction formats added used to generate multiply instructions of V5TE. by Raul Herbster · 18 years ago
  21. 0ff94f7 Initial JIT support for ARM by Raul Fernandes Herbster. by Evan Cheng · 18 years ago
  22. 13ab020 Remove clobbersPred. Add an OptionalDefOperand to instructions which have the 's' bit. by Evan Cheng · 18 years ago
  23. d45eddd Revert the earlier change that removed the M_REMATERIALIZABLE machine by Dan Gohman · 18 years ago
  24. 82a87a0 Replace M_REMATERIALIZIBLE and the newly-added isOtherReMaterializableLoad by Dan Gohman · 18 years ago
  25. eaa91b0 Replace TargetInstrInfo::CanBeDuplicated() with a M_NOT_DUPLICABLE bit. by Evan Cheng · 18 years ago
  26. d42e56e Instructions with unique labels or embedded jumptables cannot be duplicated during ifcvt. by Evan Cheng · 18 years ago
  27. 62ccdbf Add missing const qualifiers. by Evan Cheng · 18 years ago
  28. 69d5556 Hooks for predication support. by Evan Cheng · 18 years ago
  29. 6ae3626 RemoveBranch() and InsertBranch() now returns number of instructions deleted / inserted. by Evan Cheng · 18 years ago
  30. 02c602b PredicateInstruction returns true if the operation was successful. by Evan Cheng · 18 years ago
  31. b5f8eff Removed isPredicable(). by Evan Cheng · 18 years ago
  32. 9307292 Hooks for predication support. by Evan Cheng · 18 years ago
  33. 29836c3 Factor GetInstSize() out of constpool island pass. by Evan Cheng · 19 years ago
  34. 1ee2925 Make LABEL a builtin opcode. by Jim Laskey · 19 years ago
  35. a8e2989 ARM backend contribution from Apple. by Evan Cheng · 19 years ago
  36. 578e64a implement uncond branch insertion, mark branches with isBranch. by Chris Lattner · 19 years ago
  37. 46adf81 change the addressing mode of the str instruction to reg+imm by Rafael Espindola · 19 years ago
  38. aefe142 create the raddr addressing mode that matches any register and the frame index by Rafael Espindola · 19 years ago
  39. 7bc59bc added a skeleton of the ARM backend by Rafael Espindola · 19 years ago