1. 0c439eb Eliminate target hook IsEligibleForTailCallOptimization. by Evan Cheng · 16 years ago
  2. cb9a6aa Wrap some comments to 80 columns. by Bob Wilson · 16 years ago
  3. 3482c80 Patch by David Conrad: by Jim Grosbach · 16 years ago
  4. 867bbbf Name change for consistency. No functional change. by Jim Grosbach · 16 years ago
  5. 5efaed3 EmitAtomicCmpSwap() custome inserter needs to delete the MI passed in. EmitAtomicBinary() already does this. by Jim Grosbach · 16 years ago
  6. 09bf003 ARM "l" constraint for inline asm means R0-R7, also for Thumb2. by Jakob Stoklund Olesen · 16 years ago
  7. 15913c9 Fix pasto by Jakob Stoklund Olesen · 16 years ago
  8. 3ea3c24 Add more plumbing. This time in the LowerArguments and "get" functions which by Bill Wendling · 16 years ago
  9. 102ebf1 Delete the instruction just before the function terminates for consistency sake. by Evan Cheng · 16 years ago
  10. fda60d3 Fix libstdc++ build on ARM linux and part of PR5770. by Rafael Espindola · 16 years ago
  11. 5afffae Handle ARM inline asm "w" constraints with 64-bit ("d") registers. by Bob Wilson · 16 years ago
  12. c67b556 nand atomic requires opposite operand ordering by Jim Grosbach · 16 years ago
  13. 7c03dbd Add ARMv6 memory and sync barrier instructions by Jim Grosbach · 16 years ago
  14. a36c8f2 Thumb2 atomic operations by Jim Grosbach · 16 years ago
  15. c3c2354 atomic binary operations up to 32-bits wide. by Jim Grosbach · 16 years ago
  16. e801dc4 Framework for atomic binary operations. The emitter for the pseudo instructions by Jim Grosbach · 16 years ago
  17. 5278eb8 Rough first pass at compare_and_swap atomic builtins for ARM mode. Work in progress. by Jim Grosbach · 16 years ago
  18. 3728e96 Add memory barrier intrinsic support for ARM. Moving towards adding the atomic operations intrinsics. by Jim Grosbach · 16 years ago
  19. d831cda - Support inline asm 'w' constraint for 128-bit vector types. by Evan Cheng · 16 years ago
  20. 324f4f1 Recognize canonical forms of vector shuffles where the same vector is used for by Bob Wilson · 16 years ago
  21. 5cdc3a9 Materialize global addresses via movt/movw pair, this is always better by Anton Korobeynikov · 16 years ago
  22. 735afe1 Remove ISD::DEBUG_LOC and ISD::DBG_LABEL, which are no longer used. by Dan Gohman · 16 years ago
  23. bef8888 We are not using DBG_STOPPOINT anymore. by Devang Patel · 16 years ago
  24. 3f2bf85 by David Greene · 16 years ago
  25. 06b53c0 isLegalICmpImmediate should take a signed integer; code clean up. by Evan Cheng · 16 years ago
  26. 77e4751 Add TargetLowering::isLegalICmpImmediate. It tells LSR what immediate can be folded into target icmp instructions. by Evan Cheng · 16 years ago
  27. e516549 Use Unified Assembly Syntax for the ARM backend. by Jim Grosbach · 16 years ago
  28. e7e0d62 Remove ARMPCLabelIndex from ARMISelLowering. Use ARMFunctionInfo::createConstPoolEntryUId() instead. by Evan Cheng · 16 years ago
  29. b62d257 Revert previous change to a comment. The BlockAddresses go in the by Bob Wilson · 16 years ago
  30. 907eebd Put BlockAddresses into ARM constant pools. by Bob Wilson · 16 years ago
  31. 2ae0eec Handle splats of undefs properly. This includes the testcase for PR5364 as well. by Anton Korobeynikov · 16 years ago
  32. bcf2f2c Expand 64-bit logical shift right inline by Jim Grosbach · 16 years ago
  33. b4a976c Expand 64-bit arithmetic shift right inline by Jim Grosbach · 16 years ago
  34. c2b879f Expand 64 bit left shift inline rather than using the libcall. For now, this by Jim Grosbach · 16 years ago
  35. 9eda689 It's safe to remat t2LDRpci; Add PseudoSourceValue to load / store's to enable more machine licm. More changes coming. by Evan Cheng · 16 years ago
  36. 929ffa2 Fix a comment. by Bob Wilson · 16 years ago
  37. c1382b7 This fixes functions like by Rafael Espindola · 16 years ago
  38. ddb16df Add ARM codegen for indirect branches. by Bob Wilson · 16 years ago
  39. c594208 Give ARMISD::EH_SJLJ_LONGJMP and EH_SJLJ_SETJMP names. by Evan Cheng · 16 years ago
  40. 3938242 Use fconsts and fconstd to materialize small fp constants. by Evan Cheng · 16 years ago
  41. 20d1081 Most of the NEON shuffle instructions do not support 64-bit element types. by Bob Wilson · 16 years ago
  42. 2095659 Match more patterns to movt. by Evan Cheng · 16 years ago
  43. 174101e Random #include pruning. by Benjamin Kramer · 16 years ago
  44. 934f98b Revert svn r80498 and replace it with a different solution. The only problem by Bob Wilson · 16 years ago
  45. e72142a More Neon clean-up: avoid the need for custom-lowering vld/st-lane intrinsics by Bob Wilson · 16 years ago
  46. 73d64a6 NEON VLD/VST are now fully implemented. For operations that expand to by Bob Wilson · 16 years ago
  47. 249fb33 Add PseudoSourceValues for constpool stuff on ELF (Darwin should use something similar) by Anton Korobeynikov · 16 years ago
  48. 048e36f getFunctionAlignment should return log2 alignment. by Evan Cheng · 16 years ago
  49. 48e1935 ARM does not support offset folding (yet). Disable it for now. by Anton Korobeynikov · 16 years ago
  50. ce31910 Fix PR4926. When target hook EmitInstrWithCustomInserter() insert new basic blocks and update CFG, it should also inform sdisel of the changes so the phi source operands will come from the right basic blocks. by Evan Cheng · 16 years ago
  51. fb2e752 Enhance EmitInstrWithCustomInserter() so target can specify CFG changes that sdisel will use to properly complete phi nodes. by Evan Cheng · 16 years ago
  52. 0696fdf Expand vector floating-point conversions not supported by NEON. by Bob Wilson · 16 years ago
  53. 642b329 Expand some more vector operations not supported by Neon. by Bob Wilson · 16 years ago
  54. 1633076 Neon does not support vector divide or remainder. Expand them. by Bob Wilson · 16 years ago
  55. 74dc72e Expand all v2f64 arithmetic operations for Neon. by Bob Wilson · 16 years ago
  56. cd3b9a4 Fix pr4939: Change FPCCToARMCC to translate SETOLE to ARMCC::LS. by Bob Wilson · 16 years ago
  57. 2ba62ef Unbreak getOnesVector() / getZeroVector() to use valid ARM extended imm's. by Anton Korobeynikov · 16 years ago
  58. 63476a8 Reference to hidden symbols do not have to go through non-lazy pointer in non-pic mode. rdar://7187172. by Evan Cheng · 16 years ago
  59. 65c3c8f Retype from unsigned to CallingConv::ID accordingly. Approved by Bob Wilson. by Sandeep Patel · 16 years ago
  60. 8a3198b Add support for generating code for vst{234}lane intrinsics. by Bob Wilson · 16 years ago
  61. 243fcc5 Generate code for vld{234}_lane intrinsics. by Bob Wilson · 16 years ago
  62. 3fb2b1e Clean up LSDA name generation and use for SJLJ exception handling. This by Jim Grosbach · 16 years ago
  63. b00c03b EXTRACT_VECTOR_ELEMENT can have result type different from element type. by Anton Korobeynikov · 16 years ago
  64. 71624cc Do not assert on too wide splats we don't support. by Anton Korobeynikov · 16 years ago
  65. e4e4ed3 Let Darwin linker auto-synthesize stubs and lazy-pointers. This deletes a bunch of nasty code in ARM asm printer. by Evan Cheng · 16 years ago
  66. b5fb428 Hopefully the final missing part :( scalar_to_vector is fully legal now by Anton Korobeynikov · 16 years ago
  67. fdf189a Transform float scalar_to_vector into subreg accesses. by Anton Korobeynikov · 16 years ago
  68. 31fb12f Remove unneeded ARM-specific DAG nodes for VLD* and VST* Neon operations. by Bob Wilson · 16 years ago
  69. 1cb852b Expand scalar_to_vector - we don't have any isel logic for it now by Anton Korobeynikov · 16 years ago
  70. ce392eb Make x86 test actually test x86 code generation. Fix the by Eli Friedman · 16 years ago
  71. c692cb7 Match VTRN, VZIP, and VUZP shuffles. Restore the tests for these operations, by Bob Wilson · 16 years ago
  72. 051cfd6 Fix some typos and use type-based isel for VZIP/VUZP/VTRN by Anton Korobeynikov · 16 years ago
  73. 1c8e581 Add lowering of ARM 4-element shuffles to multiple instructios via perfectshuffle-generated table. by Anton Korobeynikov · 16 years ago
  74. 62e84f1 Add nodes & dummy matchers for some v{zip,uzp,trn} instructions by Anton Korobeynikov · 16 years ago
  75. 8e6c2b9 Expand EXTRACT_SUBVECTOR by Anton Korobeynikov · 16 years ago
  76. 5da894f Provide vext.{16,32} by Anton Korobeynikov · 16 years ago
  77. d0ac234 Use masks not nodes for vector shuffle predicates. Provide set of 'legal' masks, so legalizer won't infinite cycle by Anton Korobeynikov · 16 years ago
  78. de95c1b8 Add support for Neon VEXT (vector extract) shuffles. by Bob Wilson · 16 years ago
  79. af56634 Reapply r79127. It was fixed by d0k. by Bill Wendling · 16 years ago
  80. f865ea8 Revert r79127. It was causing compilation errors. by Bill Wendling · 16 years ago
  81. 088880c Change allowsUnalignedMemoryAccesses to take type argument since some targets by Evan Cheng · 16 years ago
  82. bc9b754 Turn on if-conversion for thumb2. by Evan Cheng · 16 years ago
  83. 72977a4 Allow targets to specify their choice of calling conventions per by Anton Korobeynikov · 16 years ago
  84. e6c835f Add Thumb2 lsr hooks. by Evan Cheng · 16 years ago
  85. 59bc060 80 col violation. by Evan Cheng · 16 years ago
  86. 22cac0d Now that all the legal Neon shuffles (or at least the ones that have been by Bob Wilson · 16 years ago
  87. c1d287b Create a new ARM-specific DAG node, VDUP, to represent a splat from a by Bob Wilson · 16 years ago
  88. 0ce3710 During legalization, change Neon vdup_lane operations from shuffles to by Bob Wilson · 16 years ago
  89. 1d0be15 Push LLVMContexts through the IntegerType APIs. by Owen Anderson · 16 years ago
  90. bfcbb50 Add a fixme message about canonicalizing floating-point vector types. by Bob Wilson · 16 years ago
  91. bab812b Revert r78852 for now. I want to do this differently, but I don't have time by Bob Wilson · 16 years ago
  92. 2886506 Add a comment to describe why vector shuffles are legalized to custom DAG nodes. by Bob Wilson · 16 years ago
  93. d06791f Use cast<> instead of dyn_cast<> in places where the type is known. by Bob Wilson · 16 years ago
  94. af385ba Recognize Neon VDUP shuffles during legalization instead of selection. by Bob Wilson · 16 years ago
  95. d8e1757 Recognize Neon VREV shuffles during legalization instead of selection. by Bob Wilson · 16 years ago
  96. bff3923 Add catch block handling to SjLj exception handling. by Jim Grosbach · 16 years ago
  97. 007ea27 Shrink Thumb2 movcc instructions. by Evan Cheng · 16 years ago
  98. 825b72b Split EVT into MVT and EVT, the former representing _just_ a primitive type, while by Owen Anderson · 16 years ago
  99. 764ab52 Whitespace cleanup. Remove trailing whitespace. by Jim Grosbach · 16 years ago
  100. b0abb4d Use vAny type to get rid of Neon intrinsics that differed only in whether by Bob Wilson · 16 years ago