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gerrit-public.fairphone.software / fp2-dev / platform / external / llvm / 10a433238fe4679c8da17f3eb19611466332e312
  1. 10a4332 Spill multiple registers at once. by Jakob Stoklund Olesen · 14 years ago
  2. 7a387e4 Fixed the comparison operator for the enhanced disassembler's disassembler map. by Sean Callanan · 14 years ago
  3. 55768d7 That's it, I am declaring this a failure of the C++03 STL. by Jakob Stoklund Olesen · 14 years ago
  4. 8b3000b Saving files before committing is overrated. by Eric Christopher · 14 years ago
  5. af3dce5 Sometimes isPredicable lies to us and tells us we don't need the operands. by Eric Christopher · 14 years ago
  6. 7d3a16a Remove no-longer-correct special case for disasm of ARM BL instructions. by Jim Grosbach · 14 years ago
  7. 34e98e9 Add FIXME. by Jim Grosbach · 14 years ago
  8. f859a54 Pseudo-ize the ARM Darwin *r9 call instruction definitions. They're the same by Jim Grosbach · 14 years ago
  9. cea5afc Add a FIXME. by Jim Grosbach · 14 years ago
  10. 72422d3 Pseudo-ize the ARM 'B' instruction. by Jim Grosbach · 14 years ago
  11. 3c5edaa Remove dead code. These ARM instruction definitions no longer exist. by Jim Grosbach · 14 years ago
  12. 5380bbf Remove dead code. These ARM instruction definitions no longer exist. by Jim Grosbach · 14 years ago
  13. f219f31 Pseudo-ize VMOVDcc and VMOVScc. by Jim Grosbach · 14 years ago
  14. b181ad3 80 columns by Jim Grosbach · 14 years ago
  15. dd11988 Properly pseudo-ize the ARM LDMIA_RET instruction. This has the nice side- by Jim Grosbach · 14 years ago
  16. 899eaa3 Roll r127459 back in: by Cameron Zwarich · 14 years ago
  17. 53aac15 Fix the GCC test suite issue exposed by r127477, which was caused by stack by Cameron Zwarich · 14 years ago
  18. 2ce5bf1 Teach FastISel to support register-immediate-immediate instructions. by Owen Anderson · 14 years ago
  19. 2a09f87 80 columns. by Jim Grosbach · 14 years ago
  20. 108e4db Trailing whitespace. by Jim Grosbach · 14 years ago
  21. b9cf5f8 Remove dead code. These ARM instruction definitions don't exist. by Jim Grosbach · 14 years ago
  22. 958108a ARM VDUPfd and VDUPfq can just be patterns. The instruction is the same by Jim Grosbach · 14 years ago
  23. 81bb655 Remove dead code. These ARM instruction definitions don't exist. by Jim Grosbach · 14 years ago
  24. 8b8515c ARM VDUPLNfq and VDUPLNfd definitions can just be Pat<>s for VDUPLN32q by Jim Grosbach · 14 years ago
  25. 1558df7 ARM VREV64df and VREV64qf can just be patterns. The instruction is the same by Jim Grosbach · 14 years ago
  26. f0112a2 This FIXME has been fixed. by Jim Grosbach · 14 years ago
  27. e672ff8 Properly pseudo-ize ARM MVNCCi. by Jim Grosbach · 14 years ago
  28. 6a44ada Add missing 'return on failure'. Previously we'd crash after emitting by Jim Grosbach · 14 years ago
  29. e4f6d74 Remove optimization emitting a reference insted of label difference, since it can create more relocations. Removed isBaseAddressKnownZero method, because it is no longer used. by Jan Sjödin · 14 years ago
  30. 950d3db Revert r127459, "Optimize trivial branches in CodeGenPrepare, which often get by Daniel Dunbar · 14 years ago
  31. 4839ded Force re-linking of LLVMgold.so when its exports file changes. by Oscar Fuentes · 14 years ago
  32. aa1fbb4 Fix processing of gold.exports. by Oscar Fuentes · 14 years ago
  33. 027f099 While printing annotations, print line number and variable name if debug info is present. by Devang Patel · 14 years ago
  34. eb582d7 Fix MOVCCi32imm to be have ARM-mode Requires and a proper size (8 bytes, was 4). by Jim Grosbach · 14 years ago
  35. 778583a Replace -dag-chain-limit flag with constant. It has survived a release cycle without being touched, so no longer needs to pollute the hidden-help text. by Andrew Trick · 14 years ago
  36. 1dc550b Add LTO and gold plugin to the CMake build. Linux-only, support for by Oscar Fuentes · 14 years ago
  37. 2715a58 ComputeMaskedBits: sub falls through to add, and sub doesn't have the same overflow semantics as add. by Benjamin Kramer · 14 years ago
  38. 6b49725 InstCombine: Fix a thinko where transform an icmp under the assumption that it's a zero comparison when it's not. by Benjamin Kramer · 14 years ago
  39. b69050a Teach ComputeMaskedBits about nsw on add. I don't think there's anything we can by Nick Lewycky · 14 years ago
  40. 6fd2472 Fix use of CompEnd predicate to be standards conforming by John Wiegley · 14 years ago
  41. 592ca3f Optimize trivial branches in CodeGenPrepare, which often get created from the by Cameron Zwarich · 14 years ago
  42. 4a6d735 Teach TableGen to pre-calculate register enum values when creating the by Jim Grosbach · 14 years ago
  43. 109d6db silence a conditional assignment -Wuninitialized warning. by Chris Lattner · 14 years ago
  44. 17fad04 Make the register enum value part of the CodeGenRegister struct. by Jim Grosbach · 14 years ago
  45. 510207c Trailing whitespace. by Jim Grosbach · 14 years ago
  46. 5d4314e Trailing whitespace. by Jim Grosbach · 14 years ago
  47. 7e0e82d Tidy up since ARM MOVCCi and MOVCCi16 are now pseudos. by Jim Grosbach · 14 years ago
  48. 3906276 Properly pseudo-ize ARM MOVCCi and MOVCCi16. by Jim Grosbach · 14 years ago
  49. de5e101 Change the x86 32-bit scheduler to register pressure and fix up the by Eric Christopher · 14 years ago
  50. 9ef82ce Avoid replacing the value of a directly stored load with the stored value if the load is indexed. rdar://9117613. by Evan Cheng · 14 years ago
  51. d4a16ad Properly pseudo-ize MOVCCr and MOVCCs. by Jim Grosbach · 14 years ago
  52. c9f2f61 RecursivelyDeleteTriviallyDeadInstructions only needs a by Dan Gohman · 14 years ago
  53. 9d2234d Don't compute the file size if we don't need to. by Rafael Espindola · 14 years ago
  54. fa0e6fa Fix reassociate to postpone certain instruction deletions until by Dan Gohman · 14 years ago
  55. a4f809d DMB can just be a pat referencing MCR. by Jim Grosbach · 14 years ago
  56. bc908cf Reorganize a bit. No functional change, just moving patterns up. by Jim Grosbach · 14 years ago
  57. a768c3d Pseudo-instructions are codegenonly by definition. by Jim Grosbach · 14 years ago
  58. 5e97338 Memory barrier instructions don't need special handling in tblgen anymore. by Jim Grosbach · 14 years ago
  59. 6b96fe7 InstCombine: Turn umul_with_overflow into mul nuw if we can prove that it cannot overflow. by Benjamin Kramer · 14 years ago
  60. f7fdad1 Add r127409 back now that the windows file was updated. by Rafael Espindola · 14 years ago
  61. b78e2ae Try to fix the windows build. by Rafael Espindola · 14 years ago
  62. 4b0e1f1 Revert r127409 which broke all the Windows bots. by Jakob Stoklund Olesen · 14 years ago
  63. fca9efc PTX: Add preliminary support for floating-point divide and multiply-and-add by Justin Holewinski · 14 years ago
  64. 7deb187 Add support for MemoryBuffers that are not null terminated and add by Rafael Espindola · 14 years ago
  65. be2e1b5 rip out llvm 2.8 release notes to make room for llvm 2.9 notes. by Chris Lattner · 14 years ago
  66. 6a951ac Add an option to disable critical edge splitting in PHIElimination. by Cameron Zwarich · 14 years ago
  67. 2f5565d ptx: add the rest of special registers of ISA version 2.0 by Che-Liang Chiou · 14 years ago
  68. 47dbf6c Change the Spiller interface to take a LiveRangeEdit reference. by Jakob Stoklund Olesen · 14 years ago
  69. 38f6bd0 Make SpillIs an optional pointer. Avoid creating a bunch of temporary SmallVectors. by Jakob Stoklund Olesen · 14 years ago
  70. 581d535 Unbreak the CMake build. by Francois Pichet · 14 years ago
  71. 03d5826 Revert 127359; it broke lencod. by Stuart Hastings · 14 years ago
  72. 6af531f Introduce DebugInfoProbe. This is used to monitor how llvm optimizer is treating debugging information. by Devang Patel · 14 years ago
  73. b0519e1 Re-commit 127368 and 127371. They are exonerated. by Evan Cheng · 14 years ago
  74. 02d7c92 Revert 127368 and 127371 for now. by Evan Cheng · 14 years ago
  75. 0f24d49 Restore the default implementation of getCrossCopyRegClass: no need for cross-regclass copies. by Evan Cheng · 14 years ago
  76. edfab0c Revert "Re-enable test and hope to silence the buildbots", still broken. by Daniel Dunbar · 14 years ago
  77. 17adafc Change the definition of TargetRegisterInfo::getCrossCopyRegClass to be more by Evan Cheng · 14 years ago
  78. 7bff3e7 Fix mistyped CHECK lines. by Benjamin Kramer · 14 years ago
  79. b64b497 Fix a pasto that broke all x86_64-elf targets. by Benjamin Kramer · 14 years ago
  80. 167831d Tweak test to work on Linux. by Stuart Hastings · 14 years ago
  81. 2f5443b Disable this test temporarily to reduce BuildBot complaints. by Stuart Hastings · 14 years ago
  82. a2ab399 Preserve line number information while simplifying libcalls. by Devang Patel · 14 years ago
  83. 2f26fa4 X86 byval copies no longer always_inline. <rdar://problem/8706628> by Stuart Hastings · 14 years ago
  84. 842db07 Add a testcase for the addc improvements introduced some commits ago. Patch by Akira Hatanaka by Bruno Cardoso Lopes · 14 years ago
  85. 2c19ed9 Re-enable test and hope to silence the buildbots by Bruno Cardoso Lopes · 14 years ago
  86. 557ce71 try to make o32 cc tests less specific to silence some buildbots. The test isn't enabled yet, this is will be done in a subsequent commit. Patch by Akira Hatanaka. by Bruno Cardoso Lopes · 14 years ago
  87. 18b475f LLVM combines the offset mode of A8.6.199 A1 & A2 into STRBT. by Johnny Chen · 14 years ago
  88. f607abd Make these options hidden to reduce the amount of text -help puts on the by Eric Christopher · 14 years ago
  89. 0ef1560 These llvm.dbg.* constants are not used anymore. by Devang Patel · 14 years ago
  90. 5d96e5a Make physreg coalescing independent on the number of uses of the virtual register. by Jakob Stoklund Olesen · 14 years ago
  91. dda386c Delete a test case that is very sensitive to coalescer behavior. by Jakob Stoklund Olesen · 14 years ago
  92. 954dac0 Improve varags handling, with testcases. Patch by Sasa Stankovic by Bruno Cardoso Lopes · 14 years ago
  93. 5d332e0 This test case should work with list-ilp or list-burr. by Andrew Trick · 14 years ago
  94. 4bbf467 Improve pre-RA-sched register pressure tracking for duplicate operands. by Andrew Trick · 14 years ago
  95. d1cba87 Add createELFObjectTargetWriter method to TargetAsmBackend, which enables construction of non-standard ELFObjectWriters that can be used in MCJIT. by Jan Sjödin · 14 years ago
  96. 7263d71 Missing file from previous commmit (127341) for InitializeTargetAsmParser function. by Jan Sjödin · 14 years ago
  97. 01dff96 Add constructors to MCElfStreamer and MCObjectStreamer to take an extra MCAssembler * argument. by Jan Sjödin · 14 years ago
  98. e62289b When SCEV can determine the loop test is X < X, set ExactBECount=0. by Andrew Trick · 14 years ago
  99. dd54ffd Add InitializeNativeAsmParser function. by Jan Sjödin · 14 years ago
  100. 635f718 whitespace by Andrew Trick · 14 years ago