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gerrit-public.fairphone.software / fp2-dev / platform / external / llvm / 17a1e8775119db75ece41e041eeb6480793696ff / lib / Target
  1. 17a1e87 Make $fp and $ra callee-saved registers and let PrologEpilogInserter handle by Akira Hatanaka · 14 years ago
  2. 0b65599 Revert accidental commit. by Evan Cheng · 14 years ago
  3. eb274e6 Rename the "sandybridge" subtarget to "corei7-avx", for GCC compatibility. by Benjamin Kramer · 14 years ago
  4. 6e35e4c Remove noisy semicolons. by Benjamin Kramer · 14 years ago
  5. cd0f90f Fix bug in which nodes that write to argument registers do not get glued with the JALR node. Patch by Sasa Stankovic by Akira Hatanaka · 14 years ago
  6. d992f6c Remove code that creates unnecessary frame objects. by Akira Hatanaka · 14 years ago
  7. da0a357 Define variables and functions in MipsFunctionInfo. by Akira Hatanaka · 14 years ago
  8. a166089 Don't attempt to tail call optimize for Win64. by Chad Rosier · 14 years ago
  9. 2e64960 Revert r131664 and fix it in instcombine instead. rdar://9467055 by Evan Cheng · 14 years ago
  10. dc51575 Add fast-isel support for zeroext and signext ret instructions on x86. by Eli Friedman · 14 years ago
  11. 2bbecd8 Oddly people want to use the 'r' constraint for fp constants on x86. by Eric Christopher · 14 years ago
  12. 861b9c6 This fixes one divergence between LLVM and binutils for ARM in the text section. by Jason W Kim · 14 years ago
  13. a3bff99 ADD64ri32 sign extends its argument, so we need to use a R_X86_64_32S. by Rafael Espindola · 14 years ago
  14. a1a7ba8 Align i64 arguments to 64 bit boundaries. by Akira Hatanaka · 14 years ago
  15. 0efaa5e crc32 with 64-bit output zeros upper 32-bits. rdar://9467055 by Evan Cheng · 14 years ago
  16. 59d2660 Increase number of available registers when target is MIPS32. by Akira Hatanaka · 14 years ago
  17. 95b8ae1 Simplify CC_MipsO32 and merge it with CC_MipsO32_VarArgs. Patch by Sasa Stankovic. by Akira Hatanaka · 14 years ago
  18. d22f036 Reverting 131641 to investigate 'bot complaint. by Stuart Hastings · 14 years ago
  19. 6635b04 80 columns. by Jim Grosbach · 14 years ago
  20. d48cfae Fix data layout string. i64 is aligned to 64 bit boundaries. by Akira Hatanaka · 14 years ago
  21. b6dcf3c Revise MOVSX16rr8/MOVZX16rr8 (and rm variants) to no longer be by Stuart Hastings · 14 years ago
  22. 055cdfc Use the correct register class for Cell varargs spilling. This fixes all of the by Cameron Zwarich · 14 years ago
  23. 28e2b1d Fixed sdiv and udiv for <4 x i16>. The test from r125402 still applies for this change. by Mon P Wang · 14 years ago
  24. d76773a Make CodeGen/PowerPC/2007-09-11-RegCoalescerAssert.ll pass with the verifier. by Cameron Zwarich · 14 years ago
  25. 0113e4e Fix PR8828 by removing the explicit def in MovePCToLR as well as the pointless by Cameron Zwarich · 14 years ago
  26. 462b6dc Reuse the TargetInstrDesc. by Cameron Zwarich · 14 years ago
  27. 2180372 Correctly constrain a register class when computing frame offsets, as the Thumb2 by Cameron Zwarich · 14 years ago
  28. 22486c9 Revert unintentional commit. by Eli Friedman · 14 years ago
  29. 107ffd5 More instcombine simplifications towards better debug locations. by Eli Friedman · 14 years ago
  30. 631fcbf Add missing mayLoad / mayStore flags to instruction definitions without patterns, by Cameron Zwarich · 14 years ago
  31. e4c6445 Reserve the segment registers on x86 to fix verifier failures in any code that by Cameron Zwarich · 14 years ago
  32. 20a41cb Reserve r29 on Alpha. This fixes all verifier failures in CodeGen/Alpha. by Cameron Zwarich · 14 years ago
  33. db28247 Handle perfect shuffle case that generates a vrev for vectors of floats. by Tanya Lattner · 14 years ago
  34. 955db42 Fix more of PR8825. Now all of CodeGen/ARM passes with VerifyCoalescing turned on. by Cameron Zwarich · 14 years ago
  35. a96581f Disassembly of tBcc was wrongly adding 4 to the SignExtend'ed imm8:'0' immediate operand. by Johnny Chen · 14 years ago
  36. 871f664 Enables vararg functions that pass all arguments via registers to be optimized into tail-calls when possible. by Chad Rosier · 14 years ago
  37. b936e30 Revise r131553. Just use the type of the input node and forgo the bitcast. rdar://9449159. by Evan Cheng · 14 years ago
  38. d48fda4 Fix an ARMTargetLowering::LowerSELECT bug: legalized result must have same type as input. Sorry test cases only trigger when dag combine is disabled. rdar://9449178 by Evan Cheng · 14 years ago
  39. 657d1be PTX: add flag to disable mad/fma selection by Justin Holewinski · 14 years ago
  40. 2a8eb72 In r131488 I misunderstood how VREV works. It splits the vector in half and splits each half. Therefore, the real problem was that we were using a VREV64 for a 4xi16, when we should have been using a VREV32. by Tanya Lattner · 14 years ago
  41. 141ec63 Fix typo. by Cameron Zwarich · 14 years ago
  42. 7d336c0 Fix more of PR8825 by correctly using rGPR registers when lowering atomic by Cameron Zwarich · 14 years ago
  43. d6ffcd8 Actually, the address operand of the Thumb2 LDREX / STREX instructions *can* by Cameron Zwarich · 14 years ago
  44. 3c60ff4 Correct a minor problem with the Thumb2 LDREX and STREX instruction encodings. They by Cameron Zwarich · 14 years ago
  45. c81c970 vrev is incorrectly defined in the perfect shuffle table. The ordering is backwards (should be 0x3210 versus 0x1032) which exposed a bug when doing a shuffle on a 4xi16. I've attached a test case. by Tanya Lattner · 14 years ago
  46. fee2286 Enable autodetect of popcnt by Mon P Wang · 14 years ago
  47. 19515b4 Add x86 fast-isel for calls returning first-class aggregates. rdar://9435872. by Eli Friedman · 14 years ago
  48. b8e0d34 Clean up the mess created by r131467+r131469. by Eli Friedman · 14 years ago
  49. 6db2c2f Revert 131467 due to buildbot complaint. by Stuart Hastings · 14 years ago
  50. 504421e Fix an obscure issue in X86_64 parameter passing: if a tiny byval is by Stuart Hastings · 14 years ago
  51. 8669429 by Nadav Rotem · 14 years ago
  52. 6abb7ba Update comment. by Eric Christopher · 14 years ago
  53. c324f72 Support XOR and AND optimization with no return value. by Eric Christopher · 14 years ago
  54. 811c2b7 Couple less magic numbers. by Eric Christopher · 14 years ago
  55. 8102bf0 Make this code a little less magic number laden. by Eric Christopher · 14 years ago
  56. 5d4718b add a note by Chris Lattner · 14 years ago
  57. c93943b Back out r131444 and r131438; they're breaking nightly tests. I'll look into by Eli Friedman · 14 years ago
  58. cdc9a20 Add x86 fast-isel for calls returning first-class aggregates. rdar://9435872. by Eli Friedman · 14 years ago
  59. 0c72076 Kill some dead code. by Jim Grosbach · 14 years ago
  60. 57f4b03 Remove dead code. Fix associated test to use FileCheck. by Eli Friedman · 14 years ago
  61. 482feb3 Make fast-isel work correctly s/uadd.with.overflow intrinsics. by Eli Friedman · 14 years ago
  62. 6469540 sets bit 0 of the function address of thumb function in .symtab by Rafael Espindola · 14 years ago
  63. d0118a2 Fix a FIXME by moving the fast-isel implementation of the objectsize intrinsic from the x86 code to the generic code. by Eli Friedman · 14 years ago
  64. a3f8814 Don't produce a vmovntdq if we don't have AVX support. by Rafael Espindola · 14 years ago
  65. d25d16c Zap useless code; this hasn't done anything useful since fast-isel switched to being bottom-up (a very long time ago). by Eli Friedman · 14 years ago
  66. eea6c95 Fix a source of non determinism in FindUsedTypes, use a SetVector instead of a by Julien Lerouge · 14 years ago
  67. 01765eb Fix setting of isCommutable flag. by Akira Hatanaka · 14 years ago
  68. c493a1f Turn this into a table, this will make more sense shortly. by Eric Christopher · 14 years ago
  69. 18901d6 Fix encoding of Thumb BLX register instructions. Patch by Koan-Sin Tan. by Owen Anderson · 14 years ago
  70. 4301222 by Nadav Rotem · 14 years ago
  71. 61512ba Give the 'eh.sjlj.dispatchsetup' intrinsic call the value coming from the setjmp by Bill Wendling · 14 years ago
  72. b38fe4b Optimize atomic lock or that doesn't use the result value. by Eric Christopher · 14 years ago
  73. 988397d Refactor lock versions of binary operators to be a little less cut and paste. by Eric Christopher · 14 years ago
  74. f4351ce First cut at getting debugging support for ARM/MC/ELF/.o by Jason W Kim · 14 years ago
  75. 0d10970 PTX: add PTX 2.3 setting in PTX sub-target. by Justin Holewinski · 14 years ago
  76. 49ac3d7 Fix td file comments for Mips. by Eric Christopher · 14 years ago
  77. 183c627 Fixed MC encoding for index_align for VLD1/VST1 (single element from one lane) for size 32 by Mon P Wang · 14 years ago
  78. f51190b X86: Add a bunch of peeps for add and sub of SETB. by Benjamin Kramer · 14 years ago
  79. ca66226 Eliminate the ARM sub-register indexes that are not needed by the sources. by Jakob Stoklund Olesen · 14 years ago
  80. 33c110e Fix the non-MC encoding of pkhbt and pkhtb. by Eric Christopher · 14 years ago
  81. 325e66d 1. Keep lines in 80 columns. 2. Remove unused function. 3. Correct indentation. by Akira Hatanaka · 14 years ago
  82. fc5d305 Make the logic for determining function alignment more explicit. No functionality change. by Eli Friedman · 14 years ago
  83. f2b0423 Dead code elimination. by Rafael Espindola · 14 years ago
  84. ab0145d PTX: add PTX 2.3 language target by Justin Holewinski · 14 years ago
  85. 108709d Move PPC Linux to CFI. by Rafael Espindola · 14 years ago
  86. 2970159 PR9848: pandn is not commutative. by Eli Friedman · 14 years ago
  87. 087aad4 Remove a flag that would set the ".eh" symbol as .globl. MachO was the only one by Bill Wendling · 14 years ago
  88. 4f5de9b Fix X86RegisterInfo::getMatchingSuperRegClass for sub_8bit_hi. by Jakob Stoklund Olesen · 14 years ago
  89. 21f7902 Implement SystemZRegisterInfo::getMatchingSuperRegClass to enable cross-class joins. by Jakob Stoklund Olesen · 14 years ago
  90. 64915de Do not emit location expression size twice. by Devang Patel · 14 years ago
  91. 6af0b76 Fix cmake build. by Rafael Espindola · 14 years ago
  92. 6b7588e Prevent instructions using $gp from being placed between a jalr and the instruction that restores the clobbered $gp. by Akira Hatanaka · 14 years ago
  93. b89383a Implement MSP430RegisterInfo::getMatchingSuperRegClass to enable cross-class by Jakob Stoklund Olesen · 14 years ago
  94. 2944b4f Mark ultra-super-registers QQQQ as call-clobbered instead of the D sub-registers. by Jakob Stoklund Olesen · 14 years ago
  95. 9493a28 Replace the "movnt" intrinsics with a native store + nontemporal metadata bit. by Bill Wendling · 14 years ago
  96. 9ff1b9b Fix function MipsRegisterInfo::getRegisterNumbering. by Akira Hatanaka · 14 years ago
  97. e1a56ae Temporarily disable use of divmod compiler-rt functions for iOS. by Bob Wilson · 14 years ago
  98. 0a69ba3 Fold ARM coprocessor intrinsics patterns into the instructions defs whenever by Bruno Cardoso Lopes · 14 years ago
  99. 54ad87a Add a few ARM coprocessor intrinsics. Testcases included by Bruno Cardoso Lopes · 14 years ago
  100. d2189bf Remove unused variables caught by GCC's -Wunused-but-set-variable. by Benjamin Kramer · 14 years ago