- eb274e6 Rename the "sandybridge" subtarget to "corei7-avx", for GCC compatibility. by Benjamin Kramer · 13 years ago
- 34868ee Add pentium{3,4}m cpus. Patch by Alexander Best! by Michael J. Spencer · 14 years ago
- 7a2bdde Fix a ton of comment typos found by codespell. Patch by by Chris Lattner · 14 years ago
- 4babeee Add 3DNow! intrinsics. by Michael J. Spencer · 14 years ago
- 9a0bac4 Fix whitespace and tabs. by Michael J. Spencer · 14 years ago
- de7f920 Disable auto-detection of AVX support since AVX codegen support is not ready. by Evan Cheng · 14 years ago
- 2ea8ee7 Formalize the notion that AVX and SSE are non-overlapping extensions from the compiler's point of view. Per email discussion, we either want to always use VEX-prefixed instructions or never use them, and are taking "HasAVX" to mean "Always use VEX". Passing -mattr=-avx,+sse42 should serve to restore legacy SSE support when desirable. by Nate Begeman · 14 years ago
- 1292c22 Add patterns for the x86 popcnt instruction. by Benjamin Kramer · 14 years ago
- 604cdf6 Clean up comments. by Jim Grosbach · 14 years ago
- ddcf859 Clean up asm writer usage for x86 and msp430 to flag that the writer should by Jim Grosbach · 14 years ago
- 4f98f83 tblgen/AsmMatcher: Always emit the match function as 'MatchInstructionImpl', by Daniel Dunbar · 14 years ago
- 26a9142 Declare CLMUL as a subtarget feature by Bruno Cardoso Lopes · 14 years ago
- 90b374c MC/X86: We now match instructions like "incl %eax" correctly for the arch we are by Daniel Dunbar · 14 years ago
- c918d60 MC/X86: Add "support" for matching ATT style mnemonic prefixes. by Daniel Dunbar · 15 years ago
- fddb766 Replace TSFlagsFields and TSFlagsShifts with a simpler TSFlags field. by Jakob Stoklund Olesen · 15 years ago
- 6d1cd1c Separate out the AES-NI instructions from the SSE4.2 instructions. Add by Eric Christopher · 15 years ago
- 48c58bb Nehalem unaligned memory access is fast. by Evan Cheng · 15 years ago
- 70feca4 Teach TableGen to understand X.Y notation in the TSFlagsFields strings. by Jakob Stoklund Olesen · 15 years ago
- 352aa50 Add a late SSEDomainFix pass that twiddles SSE instructions to avoid domain crossings. by Jakob Stoklund Olesen · 15 years ago
- f98bc63 MC/X86/AsmMatcher: Use the new instruction cleanup routine to implement a by Daniel Dunbar · 15 years ago
- 1f84e32 all 64-bit cpus have cmov, this should fix CodeGen/X86/cmov.ll by Chris Lattner · 15 years ago
- c96f6d6 revert r95949, it turns out that adding new prefixes is not a by Chris Lattner · 15 years ago
- 239a1ed add another bit of space for new kinds of instruction prefixes. by Chris Lattner · 15 years ago
- 95eb2ee by David Greene · 15 years ago
- b1f4981 Remove target attribute break-sse-dep. Instead, do not fold load into sse partial update instructions unless optimizing for size. by Evan Cheng · 15 years ago
- 400073d On recent Intel u-arch's, folding loads into some unary SSE instructions can by Evan Cheng · 15 years ago
- 108934c Instruction fixes, added instructions, and AsmString changes in the by Sean Callanan · 15 years ago
- 7057641 remove a temporary hack. by Chris Lattner · 15 years ago
- cae05cb split MCInst printing out of the X86ATTInstPrinter by Chris Lattner · 15 years ago
- 7008416 Add support for modeling whether or not the processor has support for by Chris Lattner · 15 years ago
- 59fc42d llvm-mc/AsmParser: Allow target to specific a comment delimiter, which will be by Daniel Dunbar · 15 years ago
- 0e2771f Match X86 register names to number. by Daniel Dunbar · 15 years ago
- 3016af5 by David Greene · 15 years ago
- 343dadb by David Greene · 15 years ago
- 874ae25 Revert 72707 and 72709, for the moment. by Dale Johannesen · 15 years ago
- ca46fdd Add missing file. by Dale Johannesen · 15 years ago
- 8cf5ab1 Update CPU capabilities for AMD machines by Stefanus Du Toit · 15 years ago
- f75e5b4 Change Feature64Bit to not imply FeatureSSE2. All x86-64 hardware has by Dan Gohman · 16 years ago
- 0be6d3f Add Intel processors core i7 and atom. by Evan Cheng · 16 years ago
- ccb6976 Do not isel load folding bt instructions for pentium m, core, core2, and AMD processors. These are significantly slower than a load followed by a bt of a register. by Evan Cheng · 16 years ago
- 027fdbe Move target independent td files from lib/Target/ to include/llvm/Target so they can be distributed along with the header files. by Evan Cheng · 16 years ago
- 2194d46 Accept -march=i586, because gcc does (a synonym by Dale Johannesen · 16 years ago
- ef93cec Add ability to override segment (mostly for code emitter purposes). by Anton Korobeynikov · 16 years ago
- ea7da50 Add lock prefix support to x86. Also add the instructions necessary for the atomic ops. They are still marked pseudo, since I cannot figure out what format to use, but they are the correct opcode. by Andrew Lenharth · 17 years ago
- b4c9a68 nocona, core2 and penryn support 64 bit. by Dale Johannesen · 17 years ago
- 63ec90a SSE 4.1 Intrinsics and detection by Nate Begeman · 17 years ago
- 4ee451d Remove attribution from file headers, per discussion on llvmdev. by Chris Lattner · 17 years ago
- 48abc5c Corrected many typing errors. And removed 'nest' parameter handling by Arnold Schwaighofer · 17 years ago
- cd6cea0 We only need to specify the most-implied feature for an architecture. by Bill Wendling · 17 years ago
- 11d8fda 3DNowA implies 3DNow. 64-bit implies SSE1, SSE2, and I assume MMX. by Bill Wendling · 18 years ago
- 4222d80 Add an "implies" field to features. This indicates that, if the current by Bill Wendling · 18 years ago
- 3f3a17d Add SSSE3 as a feature of Core2. Add MMX registers to the list of registers by Bill Wendling · 18 years ago
- bb1ee05 Add support for our first SSSE3 instruction "pmulhrsw". by Bill Wendling · 18 years ago
- 31c8a6d Add a description of the X86-64 calling convention and the return by Chris Lattner · 18 years ago
- a26eb5e Still need to support -mcpu=<> or cross compilation will fail. Doh. by Evan Cheng · 18 years ago
- abc346c Do away with CPU feature list. Just use CPUID to detect MMX, SSE, SSE2, SSE3, and 64-bit support. by Evan Cheng · 18 years ago
- 25ab690 Committing X86-64 support. by Evan Cheng · 18 years ago
- 751458d ImmMask should be 3 for a two-bit field; Compact X86II by Evan Cheng · 18 years ago
- 0f3ac8d getCalleeSaveRegs and getCalleeSaveRegClasses are no long TableGen'd. by Evan Cheng · 18 years ago
- c01d497 Remove PointerType from class Target by Evan Cheng · 18 years ago
- 3c55c54 - Use xor to clear integer registers (set R, 0). by Evan Cheng · 19 years ago
- 259e97c * Fix 80-column violations by Chris Lattner · 19 years ago
- b8643ac Fix typo. by Jeff Cohen · 19 years ago
- 559806f x86 CPU detection and proper subtarget support by Evan Cheng · 19 years ago
- cedc6f4 PHI and INLINEASM are now built-in instructions provided by Target.td by Chris Lattner · 19 years ago
- 97c7fc3 Added preliminary x86 subtarget support. by Evan Cheng · 19 years ago
- 16b04f3 Get closer to fully working scalar FP in SSE regs. This gets singlesource by Nate Begeman · 19 years ago
- f63be7d First round of support for doing scalar FP using the SSE2 ISA extension and by Nate Begeman · 19 years ago
- 9a3e49a Add support for the -x86-asm-syntax flag, which can be used to choose between by Chris Lattner · 20 years ago
- c96bb81 Remove a bunch of ad-hoc target-specific flags that were only used by the by Chris Lattner · 20 years ago
- a35ce87 Eliminate 3 of the X86 printImplicit* flags. by Chris Lattner · 20 years ago
- 2665383 Add support for the printImplicitDefsBefore flag by Chris Lattner · 21 years ago
- 4ffff9e Added the llvm.readport and llvm.writeport intrinsics for x86. These do by John Criswell · 21 years ago
- 1c54a85 Add FP conditional move instructions, which annoyingly have special properties by Chris Lattner · 21 years ago
- 5ab29b5 Each instruction now has both an ImmType and a MemType. This describes by Alkis Evlogimenos · 21 years ago
- 856ba76 Added LLVM copyright header. by John Criswell · 21 years ago
- 2959b6e Completely eliminate the isVoid TSFlag, shifting over all other fields by Chris Lattner · 21 years ago
- e5bb2d9 There is nothing special about noops anymore by Chris Lattner · 21 years ago
- c8f4587 transition to using let instead of set by Chris Lattner · 21 years ago
- 1cca5e3 Add new TableGen instruction definitions by Chris Lattner · 21 years ago
- b77eb78 Add Target class for X86 target by Chris Lattner · 21 years ago
- 762fb5f Initial checkin of X86.td file by Chris Lattner · 21 years ago