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gerrit-public.fairphone.software / fp2-dev / platform / external / llvm / 19f18be449268605ea210e68b02220a0e7bd0c15 / test
  1. 19f18be Expose FMA3 instructions to the disassembler. by Craig Topper · 13 years ago
  2. b48a189 Change CaptureTracking to pass a Use* instead of a Value* when a value is by Nick Lewycky · 13 years ago
  3. da813f4 Fix type-checking for load transformation which is not legal on floating-point types. PR11674. by Eli Friedman · 13 years ago
  4. 6059b83 PR11662. by Nadav Rotem · 13 years ago
  5. 021c0a2 Fixed a bug in LowerVECTOR_SHUFFLE and LowerBUILD_VECTOR. by Elena Demikhovsky · 13 years ago
  6. a6b21ea Turn cos(-x) into cos(x). Patch by Alexander Malyshev! by Nick Lewycky · 13 years ago
  7. 06cc66f Teach simplifycfg to recompute branch weights when merging some branches, and by Nick Lewycky · 13 years ago
  8. d6e2560 Make sure DAGCombiner doesn't introduce multiple loads from the same memory location. PR10747, part 2. by Eli Friedman · 13 years ago
  9. c9a1aed Update the branch weight metadata when reversing the order of a branch. by Nick Lewycky · 13 years ago
  10. d62414c Add an explicit test that we now fold cttz.i32(..., true) >> 5 -> 0. by Chandler Carruth · 13 years ago
  11. 49064ff InstCombine: Add a combine that turns (2^n)-1 ^ x back into (2^n)-1 - x iff x is smaller than 2^n and it fuses with a following add. by Benjamin Kramer · 13 years ago
  12. 009da05 ComputeMaskedBits: Make knownzero computation more aggressive for ctlz with undef zero. by Benjamin Kramer · 13 years ago
  13. 1fdfae0 InstCombine: Canonicalize (2^n)-1 - x into (2^n)-1 ^ x iff x is known to be smaller than 2^n. by Benjamin Kramer · 13 years ago
  14. 7782102 Use standard promotion for i8 CTTZ nodes and i8 CTLZ nodes when the by Chandler Carruth · 13 years ago
  15. 3d636ea Add systematic testing for cttz as well, and fix the bug I spotted by by Chandler Carruth · 13 years ago
  16. 9d2051f Add i8 and i64 testing for ctlz on x86. Also simplify the i16 test. by Chandler Carruth · 13 years ago
  17. e0c643d Tidy up this rather crufty test. Put the declarations at the top to make by Chandler Carruth · 13 years ago
  18. d873a4b Expand more when we have a nice 'tzcnt' instruction, to avoid generating by Chandler Carruth · 13 years ago
  19. 131f7d3 Tidy up some of these tests. by Chandler Carruth · 13 years ago
  20. acc068e Switch the lowering of CTLZ_ZERO_UNDEF from a .td pattern back to the by Chandler Carruth · 13 years ago
  21. c08e57c Cleanup this test a bit, sorting things and grouping them more clearly. by Chandler Carruth · 13 years ago
  22. 5085681 Test case for r147232. by Akira Hatanaka · 13 years ago
  23. d4659ad Move this test from date-name to feature-name, and port it to FileCheck. by Nick Lewycky · 13 years ago
  24. f06f6f5 Experimental support for aligned NEON spills. by Jakob Stoklund Olesen · 13 years ago
  25. 4050bc4 ARM VFP assembly parsing and encoding for VCVT(float <--> fixed point). by Jim Grosbach · 13 years ago
  26. b975c27 Fix incorrect relocation generation. Patch by Kristof Beyls. Fixes PR11214. by Rafael Espindola · 13 years ago
  27. f1eba25 Reinstate r146578; it doesn't appear to be the cause of some recent execution- by Chad Rosier · 13 years ago
  28. 8d9550b ARM assembler should accept shift-by-zero for any shifted-immediate operand. by Jim Grosbach · 13 years ago
  29. b143ea3 Give string constants generated by IRBuilder private linkage. by Benjamin Kramer · 13 years ago
  30. 51f40a7 Make the unreachable probability much much heavier. The previous by Chandler Carruth · 13 years ago
  31. 5ddb7a0 Speculatively revert r146578 to determine if it is the cause of a number of by Chad Rosier · 13 years ago
  32. bc24985 Local dynamic TLS model for direct object output. Create the correct TLS MIPS by Akira Hatanaka · 13 years ago
  33. af33a0c ARM VFP optional data type on VMOV GPR<-->SPR. by Jim Grosbach · 13 years ago
  34. 520dc78 Thumb2 assembly parsing of 'mov rd, rn, rrx'. by Jim Grosbach · 13 years ago
  35. 2cc5cda Thumb2 assembly parsing of 'mov(register shifted register)' aliases. by Jim Grosbach · 13 years ago
  36. e6949b1 ARM NEON assmebly parsing for VLD2 to all lanes instructions. by Jim Grosbach · 13 years ago
  37. 8d0447c Fix a couple of copy-n-paste bugs. Noticed by George Russell! by Chad Rosier · 13 years ago
  38. 8369687 Make some intrinsics safe to speculatively execute. by Nick Lewycky · 13 years ago
  39. 1e33e8b Fix a couple of copy-n-paste bugs. Noticed by George Russell. by Evan Cheng · 13 years ago
  40. 3471d4f ARM NEON VLD2 assembly parsing for structure to all lanes, non-writeback. by Jim Grosbach · 13 years ago
  41. c7541c4 Fix bug in zero-store peephole pattern reported in pr11615. by Akira Hatanaka · 13 years ago
  42. c79507a Expand 64-bit CTLZ nodes if target architecture does not support it. Add test by Akira Hatanaka · 13 years ago
  43. cf966cb Test case for r147017. by Akira Hatanaka · 13 years ago
  44. 06d738c Enable and fix a test. by Jim Grosbach · 13 years ago
  45. 2fd0475 Add function MipsDAGToDAGISel::SelectMULT and factor out code that generates by Akira Hatanaka · 13 years ago
  46. 8dc684d 64-bit data directive. by Akira Hatanaka · 13 years ago
  47. ef43c2d 32-to-64-bit sext_inreg pattern. by Akira Hatanaka · 13 years ago
  48. 990d639 Add code in MipsDAGToDAGISel for selecting constant +0.0. by Akira Hatanaka · 13 years ago
  49. 52346e9 Heed spill slot alignment on ARM. by Jakob Stoklund Olesen · 13 years ago
  50. 5b48431 ARM assembly parsing and encoding for VST2 single-element, double spaced. by Jim Grosbach · 13 years ago
  51. 514806b ARM enable a few more tests. by Jim Grosbach · 13 years ago
  52. 95fad1c ARM assembly parsing and encoding for VLD2 single-element, double spaced. by Jim Grosbach · 13 years ago
  53. afff941 ARM target code clean up. Check for iOS, not Darwin where it makes sense. by Evan Cheng · 13 years ago
  54. ba4f83b This is the second fix related to VZEXT_MOVL node. by Elena Demikhovsky · 13 years ago
  55. f2d7693 Begin teaching the X86 target how to efficiently codegen patterns that by Chandler Carruth · 13 years ago
  56. 1885687 Unit test for r146950: LSR postinc expansion, PR11571. by Andrew Trick · 13 years ago
  57. c0b0e57 Mark ARM eh_sjlj_dispatchsetup as clobbering all registers. Radar 10567930. by Bob Wilson · 13 years ago
  58. 04b5d93 ARM assembly shifts by zero should be plain 'mov' instructions. by Jim Grosbach · 13 years ago
  59. ea93373 Now that PR11464 is fixed, reapply the patch to fix PR11464, by Chris Lattner · 13 years ago
  60. 6891050 fix PR11464 by preventing the linker from mapping two different struct types from the source module onto the same opaque destination type. An opaque type can only be resolved to one thing or another after all. by Chris Lattner · 13 years ago
  61. 26118cf Move tests to FileCheck. by Evan Cheng · 13 years ago
  62. 2f19674 ARM assembly parsing and encoding support for LDRD(label). by Jim Grosbach · 13 years ago
  63. 59eb805 Add a test case for r146900. by Akira Hatanaka · 13 years ago
  64. f06cb2b Add patterns for matching immediates whose lower 16-bit is cleared. These by Akira Hatanaka · 13 years ago
  65. d22170e ARM NEON two-operand aliases for VPADD. by Jim Grosbach · 13 years ago
  66. ee97314 Remove definitions of double word shift plus 32 instructions. Assembler or by Akira Hatanaka · 13 years ago
  67. 89dc8d7 Remove the restriction on the first operand of the add node in SelectAddr. by Akira Hatanaka · 13 years ago
  68. 61b74b4 ARM NEON implied destination aliases for VMAX/VMIN. by Jim Grosbach · 13 years ago
  69. eeaf1c1 ARM NEON relax parse time diagnostics for alignment specifiers. by Jim Grosbach · 13 years ago
  70. 3470693 Allow inlining of functions with returns_twice calls, if they have the by Joerg Sonnenberger · 13 years ago
  71. 2e61194 Revert 146728 as it's causing failures on some of the external bots as well as by Chad Rosier · 13 years ago
  72. 67005b3 Revert r146822 at Pete Cooper's request as it broke clang self hosting. by Kevin Enderby · 13 years ago
  73. 93ca122 SimplifyCFG now predicts some conditional branches to true or false depending on previous branch on same comparison operands. by Pete Cooper · 13 years ago
  74. 5bb210e Deleting the json-bench-test until I understand why it is flaky. by Manuel Klimek · 13 years ago
  75. b16db81 Fix a CPSR liveness tracking bug introduced when I converted IT block to bundle. by Evan Cheng · 13 years ago
  76. 8f7d12c Add back the MC bits of 126425. Original patch by Nathan Jeffords. I added the by Rafael Espindola · 13 years ago
  77. 8b99c1e Make sure that the lower bits on the VSELECT condition are properly set. by Lang Hames · 13 years ago
  78. ce16339 The powers that be have decided that LLVM IR should now support 16-bit by Dan Gohman · 13 years ago
  79. 2e1b0c0 When recursing for the original size of a type, stop if we are at a by Eric Christopher · 13 years ago
  80. b076fb7 Fix off-by-one error in bucket sort. by Jakob Stoklund Olesen · 13 years ago
  81. 9034562 Hexagon: Fix a nasty order-of-initialization bug. by Benjamin Kramer · 13 years ago
  82. 76f1301 Adds a JSON parser and a benchmark (json-bench) to catch performance regressions. by Manuel Klimek · 13 years ago
  83. 9646acf By popular demand, link up types by name if they are isomorphic and one is an by Chris Lattner · 13 years ago
  84. 94438ba Don't try to match 'unpackl/h v, v' for 32xi8 and 16xi16 when only AVX1 is supported. Fix 'unpackh v, v' for 256-bit types to understand 128-bit lanes. by Craig Topper · 13 years ago
  85. 478a4d9 [asan] add a test for instrumenting globals by Kostya Serebryany · 13 years ago
  86. 7e840ef Make sure we correctly note the existence of an i8 immediate for vblendvps and friends, so we compute fixups correctly. PR11586. by Eli Friedman · 13 years ago
  87. a738da7 ARM NEON VCLE is an alias for VCGE w/ the source operands reversed. by Jim Grosbach · 13 years ago
  88. 60d99a5 ARM NEON VTBL/VTBX assembly parsing and encoding. by Jim Grosbach · 13 years ago
  89. c8dd201 Add missing zmovl AVX patterns which were causing crashes. by Chad Rosier · 13 years ago
  90. 0660cfe Fix assert in LowerBUILD_VECTOR for v16i16 type on AVX. by Chad Rosier · 13 years ago
  91. 81fdd7b Set specific target cpu for testcase. by Lang Hames · 13 years ago
  92. 74c86e5 Added test case for r146671. by Lang Hames · 13 years ago
  93. 0481143 Add a test case to make sure that the nop really does follow the bl on ppc64 elf by Hal Finkel · 13 years ago
  94. 3ba19b1 Fix test. by Eli Friedman · 13 years ago
  95. adeb0a6 Make constant folding for GEPs a bit more aggressive. by Eli Friedman · 13 years ago
  96. ca072a3 Don't try to form FGETSIGN after legalization; it is possible in some cases, but the existing code can't do it correctly. PR11570. by Eli Friedman · 13 years ago
  97. a860b18 Add support for lowering fneg when AVX is enabled. rdar://10566486 by Chad Rosier · 13 years ago
  98. 4e5a1ab Added InstCombine for "select cond, ~cond, x" type patterns by Pete Cooper · 13 years ago
  99. 7d1ff37 Make loop preheader insertion in LoopSimplify handle the case where the loop header is a landing pad correctly (by splitting the landingpad out of the loop header). Make some adjustments to the rest of LoopSimplify to make it clear that the rest of LoopSimplify isn't making bad assumptions about the presence of landing pads. PR11575. by Eli Friedman · 13 years ago
  100. f042660 Move Instruction::isSafeToSpeculativelyExecute out of VMCore and by Dan Gohman · 13 years ago