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gerrit-public.fairphone.software / fp2-dev / platform / external / llvm / 1abf2cb59b8d63415780a03329307c0997b2670c / lib / Target
  1. 1abf2cb Rename createAsmInfo to createMCAsmInfo and move registration code to MCTargetDesc to prepare for next round of changes. by Evan Cheng · 14 years ago
  2. 33c16a2 ARM diagnostic when 's' suffix on mnemonic that can't set flags. by Jim Grosbach · 14 years ago
  3. 13123d9 * Redo the permutation encoding for frameless stacks to be more like what the by Bill Wendling · 14 years ago
  4. 151bd17 Add OperandTypes for Thumb branch targets. by Benjamin Kramer · 14 years ago
  5. 3be41b7 Port operand types for ARM and X86 over from EDIS to the .td files. by Benjamin Kramer · 14 years ago
  6. c8ae39e ARM MCRR/MCRR2 immediate operand range checking. by Jim Grosbach · 14 years ago
  7. e540c74 ARM MCR/MCR2 assembly parsing operand constraints. by Jim Grosbach · 14 years ago
  8. 5cf9fcd After type-system-rewrite branch update the Cpp backend to not use OpaqueType. by Nicolas Geoffray · 14 years ago
  9. c60f9b7 Next round of MC refactoring. This patch factor MC table instantiations, MC by Evan Cheng · 14 years ago
  10. 5427ede Check register class matching instead of width of type matching by Eric Christopher · 14 years ago
  11. c83d504 Reorganize ARM assembler aliases. by Jim Grosbach · 14 years ago
  12. 62f67f8 Add 256-bit load/store recognition and matching in several places. by Bruno Cardoso Lopes · 14 years ago
  13. eac0796 Don't leak operands when putting them into a shift. by Benjamin Kramer · 14 years ago
  14. 3b14a5c Update ARM Assembly of LDM/STM. by Jim Grosbach · 14 years ago
  15. 9dec507 ARM ISB instruction assembly parsing. by Jim Grosbach · 14 years ago
  16. c7e3396 Update XCoreRegisterInfo::eliminateFrameIndex() to handle DBG_VALUE by Richard Osborne · 14 years ago
  17. d0f3ef8 by Nadav Rotem · 14 years ago
  18. 672b93a Unfortunately several files in MC are badly violating layering rule by using by Evan Cheng · 14 years ago
  19. 3ff2551 Don't emit a bit test if there is only one case the test can yield false. A simple SETNE is sufficient. by Benjamin Kramer · 14 years ago
  20. 7e94501 Fix up assertion in r135018 so it doesn't trigger on 32-bit; when we're in 32-bit, it doesn't matter whether the operation overflows because the computed address is not wider than the immediate. by Eli Friedman · 14 years ago
  21. e77494e ARM Assembler support for DSB instruction. by Jim Grosbach · 14 years ago
  22. 77f379e DMB instalias needs the same predicate as the instruction. by Jim Grosbach · 14 years ago
  23. 032434d ARM Assembler support for DMB instruction. by Jim Grosbach · 14 years ago
  24. 20fcaff Update comments. These are for assembler, too. by Jim Grosbach · 14 years ago
  25. 1688441 Add a target-indepedent entry to MCInstrDesc to describe the encoded size of an opcode. Switch ARM over to using that rather than its own special MCInstrDesc bits. by Owen Anderson · 14 years ago
  26. efe2a65 Add code to handle a "frameless" unwind stack. by Bill Wendling · 14 years ago
  27. 6f9f884 ARM Assembler support for DBG instruction. by Jim Grosbach · 14 years ago
  28. 1cbb0c1 Revert 135093. Think-o. by Jim Grosbach · 14 years ago
  29. 91eb0aa Correct range for thumb co-processor immediate by Jim Grosbach · 14 years ago
  30. 83ab070 Range checking for CDP[2] immediates. by Jim Grosbach · 14 years ago
  31. 466b022 Make X86ISD::ANDNP more general and Codegen 256-bit VANDNP. A more by Bruno Cardoso Lopes · 14 years ago
  32. c1af477 The target specific node PANDN name is misleading. That happens because by Bruno Cardoso Lopes · 14 years ago
  33. e35c5e0 Cleanup Thumb co-processor instructions a bit. by Jim Grosbach · 14 years ago
  34. 2a01946 Make sure we don't combine a large displacement and a frame index in the same addressing mode on x86-64. It can overflow, leading to a crash/miscompile. by Eli Friedman · 14 years ago
  35. 0d8dae2 Parameterize away the ARM T1Cop class. by Jim Grosbach · 14 years ago
  36. 9bb098a Fix predicates for Thumb co-processor instructions. by Jim Grosbach · 14 years ago
  37. 4977eb5 Refactor out checking for displacements on x86-64 addressing modes. No functionality change. Refactoring in preparation for an additional safety check in FoldOffsetIntoAddress. by Eli Friedman · 14 years ago
  38. 898e7e2 Fix encoding for ARM BXJ instruction. by Jim Grosbach · 14 years ago
  39. d447ac6 Fix encoding of predicate bits on ARM BX_pred. by Jim Grosbach · 14 years ago
  40. fff76ee Range checking for 16-bit immediates in ARM assembly. by Jim Grosbach · 14 years ago
  41. 9bc402c Fix up TargetLoweringObjectFile ctors to properly initialize fields. by Evan Cheng · 14 years ago
  42. 619e0d6 Give the ARM BKPT instruction the right operand type. by Jim Grosbach · 14 years ago
  43. 21101d6 Add tests for ARM parsing of 'BKPT' instruction. by Jim Grosbach · 14 years ago
  44. 1990672 Improve ARM assembly parsing diagnostics a bit. by Jim Grosbach · 14 years ago
  45. 37ee464 Destination register operand is optional for ADC and SBC ARM. by Jim Grosbach · 14 years ago
  46. e8606dc Flesh out ARM Parser support for shifted-register operands. by Jim Grosbach · 14 years ago
  47. aa4cc1a 80 columns. by Jim Grosbach · 14 years ago
  48. b7f689b Update MCParsedAsmOperand debug methods. by Jim Grosbach · 14 years ago
  49. fc6d3a4 Convert InsertValueInst and ExtractValueInst APIs to use ArrayRef. by Jay Foad · 14 years ago
  50. 3b73708 Add an entry. by Evan Cheng · 14 years ago
  51. 61905f0 AVX Codegen support for 256-bit versions of vandps, vandpd, vorps, vorpd, vxorps, vxorpd by Bruno Cardoso Lopes · 14 years ago
  52. 8440fe2 Don't emit the FDE end label if the last thing emitted was a compact unwind and by Bill Wendling · 14 years ago
  53. 5cf2ee1 Add an assert (which should never trigger) that triggers on a testcase I'm looking at. by Eli Friedman · 14 years ago
  54. e721f5c Improve codegen for select's: if (x != 0) x = 1 if (x == 1) x = 1 by Evan Cheng · 14 years ago
  55. 3641e81 Assign variable before we test it. by Bill Wendling · 14 years ago
  56. f4f53f0 Fix obvious think-o. by Bill Wendling · 14 years ago
  57. 595d745 Clean up the handling of an EBP/RBP unwind frame pointer. In particular, don't by Bill Wendling · 14 years ago
  58. d5efb1e There is a cyclic dependency between MC and Target if this method is out-of-line. by Bill Wendling · 14 years ago
  59. 5fdd6c8 Second attempt at de-constifying LLVM Types in FunctionType::get(), by Jay Foad · 14 years ago
  60. e3f5ae7 Remove IntegerType constness from TargetData by Tobias Grosser · 14 years ago
  61. 2280ebd Revert r134893 and r134888 (and related patches in other trees). It was causing by Bill Wendling · 14 years ago
  62. af0a2e6 Most MCCodeEmitter's don't meed MCContext. by Evan Cheng · 14 years ago
  63. 3f00e31 Fix recognition of ARM 'adcs' mnemonic. by Jim Grosbach · 14 years ago
  64. 589130f Simplify printing of ARM shifted immediates. by Jim Grosbach · 14 years ago
  65. eeb64ae De-constify Types in StructType::get() and TargetData::getIntPtrType(). by Jay Foad · 14 years ago
  66. f362aff De-constify Types in FunctionType::get(). by Jay Foad · 14 years ago
  67. 59ee62d - Eliminate MCCodeEmitter's dependency on TargetMachine. It now uses MCInstrInfo by Evan Cheng · 14 years ago
  68. f75ae4c Fix <rdar://problem/9751331>. by Cameron Zwarich · 14 years ago
  69. f81b7f6 Use BranchProbability instead of floating points in IfConverter. by Jakub Staszak · 14 years ago
  70. 1afcace Land the long talked about "type system rewrite" patch. This by Chris Lattner · 14 years ago
  71. 1fe156f Revert accidental commit. by Evan Cheng · 14 years ago
  72. ffc0e73 Change createAsmParser to take a MCSubtargetInfo instead of triple, by Evan Cheng · 14 years ago
  73. 439d05d Really force on 64bit for 64-bit targets. Should fix remaining failures on unknown x86/non-x86 targets. by Eli Friedman · 14 years ago
  74. 6dfef66 Revert earlier unnecessary hack. Make sure we correctly force on 64bit and cmov for 64-bit targets. by Eli Friedman · 14 years ago
  75. eb0caa1 Fix indentation. by Evan Cheng · 14 years ago
  76. 3286920 Add support for ARM / Thumb mode switching with .code 16 and .code 32. by Evan Cheng · 14 years ago
  77. 7e61a31 Mark tBRIND as predicable. by Jim Grosbach · 14 years ago
  78. 4d1a8dd Restore old behavior. Always auto-detect features unless cpu or features are specified. by Evan Cheng · 14 years ago
  79. aa8d1b8 Pseudo-ize tBRIND. by Jim Grosbach · 14 years ago
  80. f06ff4e Default 64-bit target features and SSE2 on when a triple specifies x86-64. Clean up all the other hacks which are now unnecessary. by Eli Friedman · 14 years ago
  81. 25e6d48 Make tBX_RET and tBX_RET_vararg predicable. by Jim Grosbach · 14 years ago
  82. f296082 Add _allrem, _aullrem and _allmul to the runtime for MSVC. by Julien Lerouge · 14 years ago
  83. 3339084 Add an intrinsic and codegen support for fused multiply-accumulate. The intent by Cameron Zwarich · 14 years ago
  84. cc0ddc7 For non-x86 host, used generic as CPU name. by Evan Cheng · 14 years ago
  85. d28ec08 Pseudo-ize tBX_RET and tBX_RET_vararg. by Jim Grosbach · 14 years ago
  86. 75ca4b9 Plug a leak by giving the AsmParser ownership of the MCSubtargetInfo. by Benjamin Kramer · 14 years ago
  87. ead77cd Shuffle productions around a bit. by Jim Grosbach · 14 years ago
  88. 0b44aea Use tPseudoExpand for tTAILJMPrND and tTAILJMPr. by Jim Grosbach · 14 years ago
  89. af7f2d6 Use tPseudoExpand for tTAILJMPd and tTAILJMPdND. by Jim Grosbach · 14 years ago
  90. 70629ab Silence compiler warning. by Benjamin Kramer · 14 years ago
  91. 8dc41f3 Add more info to FIXME. by Jim Grosbach · 14 years ago
  92. e36e21e Move Thumb tail call pseudos to Thumb.td file. by Jim Grosbach · 14 years ago
  93. 480cee5 TargetAsmParser doesn't need reference to Target. by Evan Cheng · 14 years ago
  94. 245f5e8 Use ARMPseudoExpand for ARM tail calls. by Jim Grosbach · 14 years ago
  95. 9ca2a77 Shuffle productions around a bit. by Jim Grosbach · 14 years ago
  96. 4559a7b Use ARMPseudoExpand for BLr9, BLr9_pred, BXr9, and BXr9_pred. by Jim Grosbach · 14 years ago
  97. 549a851 Add CMake support for the new TableGen file introduced in r134705. by Chandler Carruth · 14 years ago
  98. 53e3fc4 Use TableGen'erated pseudo lowering for ARM. by Jim Grosbach · 14 years ago
  99. ebdeeab Eliminate asm parser's dependency on TargetMachine: by Evan Cheng · 14 years ago
  100. 0184336 Raise assertion when MachineOperand has unexpected target flag. by Akira Hatanaka · 14 years ago