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gerrit-public.fairphone.software / fp2-dev / platform / external / llvm / 1b383ba6ae47498ea80250a0369e10e2bf3c6331 / lib / Target / ARM / ARMBaseInstrInfo.cpp
  1. c1d3021 Split ARM::LDRB into LDRBi12 and LDRBrs. Adjust accordingly. Continuing on by Jim Grosbach · 14 years ago
  2. 3e55612 First part of refactoring ARM addrmode2 (load/store) instructions to be more by Jim Grosbach · 14 years ago
  3. c8141df Use instruction itinerary to determine what instructions are 'cheap'. by Evan Cheng · 14 years ago
  4. 19e5702 Move the remaining attribute macros to systematic names based on the attribute by Chandler Carruth · 14 years ago
  5. dd9dd6f Latency between CPSR def and branch is zero. by Evan Cheng · 14 years ago
  6. 2312842 Re-enable register pressure aware machine licm with fixes. Hoist() may have by Evan Cheng · 14 years ago
  7. 9869413 Revert r116781 "- Add a hook for target to determine whether an instruction def by Daniel Dunbar · 14 years ago
  8. 11e8b74 - Add a hook for target to determine whether an instruction def is by Evan Cheng · 14 years ago
  9. b41ee96 Don't recompute MachineRegisterInfo in the Optimize* method. by Bill Wendling · 14 years ago
  10. 0aa38b9 Check to make sure that the iterator isn't at the beginning of the basic block by Bill Wendling · 14 years ago
  11. 344d9db Code refactoring. by Evan Cheng · 14 years ago
  12. 5a50cee Model operand cycles of vldm / vstm; also fixes scheduling itineraries of vldr / vstr, etc. by Evan Cheng · 14 years ago
  13. 3c38f96 Clean up MOVi32imm and t2MOVi32imm pseudo instruction definitions. by Jim Grosbach · 14 years ago
  14. a0792de - Add TargetInstrInfo::getOperandLatency() to compute operand latencies. This by Evan Cheng · 14 years ago
  15. f000a7a fix MSVC 2010 build. by Michael J. Spencer · 14 years ago
  16. 2bbb769 Cleanup Whitespace. by Michael J. Spencer · 14 years ago
  17. e3cc84a Thread the determination of branch prediction hit rates back through the if-conversion heuristic APIs. For now, by Owen Anderson · 14 years ago
  18. 00d4f48 Make the spelling of the flags for old-style if-conversion heuristics consistent between ARM and Thumb2. by Owen Anderson · 14 years ago
  19. b3c04ec Temporarily add a flag to make it easier to compare the new-style ARM if by Owen Anderson · 14 years ago
  20. 05642a3 improve heuristics to find the 'and' corresponding to 'tst' to also catch opportunities on thumb2 by Gabor Greif · 14 years ago
  21. 654d544 Add a subtarget hook for reporting the misprediction penalty. Use this to provide more precise by Owen Anderson · 14 years ago
  22. b20b851 Part one of switching to using a more sane heuristic for determining if-conversion profitability. by Owen Anderson · 14 years ago
  23. a99c3e9 80-col fixups. by Eric Christopher · 14 years ago
  24. 676e258 Fix r114632. Return if the only terminator is an unconditional branch after the redundant ones are deleted. by Evan Cheng · 14 years ago
  25. 108c872 If there are multiple unconditional branches terminating a block, eliminate all by Evan Cheng · 14 years ago
  26. 691e64a OptimizeCompareInstr should avoid iterating pass the beginning of the MBB when the 'and' instruction is after the comparison. by Evan Cheng · 14 years ago
  27. 8ff9bb1 Fix buglet when the TST instruction directly uses the AND result. by Gabor Greif · 14 years ago
  28. 04ac81d Move the search for the appropriate AND instruction by Gabor Greif · 14 years ago
  29. 59db549 convert targets to the new MF.getMachineMemOperand interface. by Chris Lattner · 14 years ago
  30. 06f264e Remember VLDMQ. by Jakob Stoklund Olesen · 14 years ago
  31. 31bbc51 Add missing break. by Jakob Stoklund Olesen · 14 years ago
  32. d64816a Recognize VST1q64Pseudo and VSTMQ as stack slot stores. by Jakob Stoklund Olesen · 14 years ago
  33. 3a95182 Reapply Gabor's 113839, 113840, and 113876 with a fix for a problem by Bob Wilson · 14 years ago
  34. 7602993 the darwin9-powerpc buildbot keeps consistently crashing, by Gabor Greif · 14 years ago
  35. 3432785 Move ARM is{LoadFrom,StoreTo}StackSlot closer to their siblings so they won't be by Jakob Stoklund Olesen · 14 years ago
  36. 064312d Spelling fix. by Bob Wilson · 14 years ago
  37. 168f382 Use VLD1/VST1 pseudo instructions for loadRegFromStackSlot and by Bob Wilson · 14 years ago
  38. 308f64a an attempt to salvage the darwin9-powerpc buildbot, which could be miscompiling this line by Gabor Greif · 14 years ago
  39. de90bfd Eliminate a 'tst' that immediately follows an 'and' by Gabor Greif · 14 years ago
  40. a655686 Rename ConvertToSetZeroFlag to something more general. by Bill Wendling · 14 years ago
  41. 3665661 No need to recompute the SrcReg and CmpValue. by Bill Wendling · 14 years ago
  42. 92ad57f Move some of the decision logic for converting an instruction into one that sets by Bill Wendling · 14 years ago
  43. 220e240 Modify the comparison optimizations in the peephole optimizer to update the by Bill Wendling · 14 years ago
  44. 51f5b67 Add a missing case to duplicateCPV() for LSDA constants. Add a FIXME. rdar://8302157 by Jim Grosbach · 14 years ago
  45. 3ef1c87 Teach if-converter to be more careful with predicating instructions that would by Evan Cheng · 14 years ago
  46. 5f54ce3 For each instruction itinerary class, specify the number of micro-ops each by Evan Cheng · 14 years ago
  47. 707fb64 remove obsolete comment by Jim Grosbach · 14 years ago
  48. 0cfcf93 correct spill code to properly determine if dynamic stack realignment is by Jim Grosbach · 14 years ago
  49. d4bfd54 Change ARM VFP VLDM/VSTM instructions to use addressing mode #4, just like by Bob Wilson · 14 years ago
  50. ad42271 Minor simplification. Gets rid of a needless temporary. by Bill Wendling · 14 years ago
  51. 38ae997 Handle ARM compares as well as converting for ARM adds, subs, and thumb2's adds. by Bill Wendling · 14 years ago
  52. 75486db Turn optimize compares back on with fix. We needed to test that a machine op was by Bill Wendling · 14 years ago
  53. c98af33 Use the "isCompare" machine instruction attribute instead of calling the by Bill Wendling · 14 years ago
  54. e4ddbdf Add the Optimize Compares pass (disabled by default). by Bill Wendling · 14 years ago
  55. 6ccfc50 Many Thumb2 instructions can reference the full ARM register set (i.e., by Jim Grosbach · 14 years ago
  56. 4dbbe34 prune #includes a little. by Chris Lattner · 14 years ago
  57. 78e6e00 Remove the isMoveInstr() hook. by Jakob Stoklund Olesen · 14 years ago
  58. 7431bea Rename DBG_LABEL PROLOG_LABEL, because it's only used during prolog emission and by Bill Wendling · 14 years ago
  59. 600f171 RISC architectures get their memory operand folding for free. by Jakob Stoklund Olesen · 14 years ago
  60. ac27366 Replace copyRegToReg with copyPhysReg for ARM. by Jakob Stoklund Olesen · 14 years ago
  61. 1f32340 Automatically fold COPY instructions into stack load/store. by Jakob Stoklund Olesen · 14 years ago
  62. 8190173 For big-endian systems, VLD2/VST2 with 32-bit vector elements will swap the by Bob Wilson · 14 years ago
  63. f967ca0 Represent NEON load/store alignments in bytes, not bits. by Bob Wilson · 14 years ago
  64. a5e82a5 Don't create neon moves in CopyRegToReg. NEONMoveFixPass will do the conversion by Rafael Espindola · 14 years ago
  65. d31f972 Add a VT argument to getMinimalPhysRegClass and replace the copy related uses by Rafael Espindola · 14 years ago
  66. 1315143 Change if-conversion block size limit checks to add some flexibility. by Evan Cheng · 14 years ago
  67. 57bb394 IT instructions are considered to be scheduling hazards, but are scheduled by Jim Grosbach · 14 years ago
  68. 4b72210 We are missing opportunites to use ldm. Take code like this: by Bill Wendling · 14 years ago
  69. 86050dc Allow ARM if-converter to be run after post allocation scheduling. by Evan Cheng · 14 years ago
  70. ebe99b2 Rewrite chained if's as switches and replace assertions with llvm_unreachable by Bob Wilson · 14 years ago
  71. 3bf9125 Add a DebugLoc parameter to TargetInstrInfo::InsertBranch(). This by Stuart Hastings · 14 years ago
  72. 6470a11 Next round of tail call changes. Register used in a tail by Dale Johannesen · 14 years ago
  73. 14f1d4e VMOVQQ and VMOVQQQQ are pseudo instructions and not predicable. by Bob Wilson · 14 years ago
  74. 99405df Reapply r105521, this time appending "LLU" to 64 bit by Bruno Cardoso Lopes · 14 years ago
  75. 1087f54 revert r105521, which is breaking the buildbots with stuff like this: by Chris Lattner · 14 years ago
  76. 3eca98b Initial AVX support for some instructions. No patterns matched by Bruno Cardoso Lopes · 14 years ago
  77. 9edf7de Slightly change the meaning of the reMaterialize target hook when the original by Jakob Stoklund Olesen · 14 years ago
  78. 18f30e6 Clean up 80 column violations. No functional change. by Jim Grosbach · 14 years ago
  79. 42d075c Remove the TargetRegisterClass member from CalleeSavedInfo by Rafael Espindola · 14 years ago
  80. 0798edd Update the saved stack pointer in the sjlj function context following either by Jim Grosbach · 14 years ago
  81. 558661d Switch ARMRegisterInfo.td to use SubRegIndex and eliminate the parallel enums by Jakob Stoklund Olesen · 14 years ago
  82. 2457f2c Implement @llvm.returnaddress. rdar://8015977. by Evan Cheng · 14 years ago
  83. 5eb1951 Implement eh.sjlj.longjmp for ARM. Clean up the intrinsic a bit. by Jim Grosbach · 14 years ago
  84. 22c687b Added a QQQQ register file to model 4-consecutive Q registers. by Evan Cheng · 15 years ago
  85. 69b9f98 Bring back VLD1q and VST1q and use them for reloading / spilling Q registers. This allows folding loads and stores into VMOVQ. by Evan Cheng · 15 years ago
  86. 435d499 Use VLD2q32 / VST2q32 to reload / spill QQ (pair of Q) registers when stack slot is sufficiently aligned. Use VLDMD / VSTMD otherwise. by Evan Cheng · 15 years ago
  87. 07a6d93 Use VSTMD / VLDMD for spills and reloads of Q registers instead of VSTMQ / VLDQ. The later are aliases which ought to be eliminated but we can't because they are used for storing and loading v2f64 values. by Evan Cheng · 15 years ago
  88. c10b5af Remove VLD1q and VST1q for reloading and spilling Q registers. Just use VLD1q64 / VST1q64 and reference sub-registers. by Evan Cheng · 15 years ago
  89. 34dcc6f Add a DebugLoc argument to TargetInstrInfo::copyRegToReg, so that it by Dan Gohman · 15 years ago
  90. 746ad69 Add argument TargetRegisterInfo to loadRegFromStackSlot and storeRegToStackSlot. by Evan Cheng · 15 years ago
  91. b63387a Re-apply 103156 and 103157. 103156 didn't break anything. 10315 exposed a coalescer bug that's fixed by 103170. by Evan Cheng · 15 years ago
  92. 1ef7c82 Revert r103157, which broke test/CodeGen/ARM/2009-11-30-LiveVariablesBug.ll. by Dan Gohman · 15 years ago
  93. f865cb5 Revert r103156 since it was breaking the build bots. by Eric Christopher · 15 years ago
  94. 9c35ee2 Fix an obvious bug in isMoveInstr. It needs to return sub-register indices. by Evan Cheng · 15 years ago
  95. 4ffc22a Adding pseudo 256-bit registers QQ0 . . . QQ7 to represent pairs of Q registers. These will be used to model VLD2 / VST2 instructions in order to get substantially better codegen for them. by Evan Cheng · 15 years ago
  96. d31c549 Cosmetic changes. by Evan Cheng · 15 years ago
  97. 7f2f436 storeRegToStackSlot has forgotten about QPR_8 register class. by Evan Cheng · 15 years ago
  98. 8601a3d Frame index can be negative. by Evan Cheng · 15 years ago
  99. d100755 by Jim Grosbach · 15 years ago
  100. 62b5065 Add ARM specific emitFrameIndexDebugValue. by Evan Cheng · 15 years ago