- 1fcbca0 It could come about that we parse the inline ASM before we get a potential by Bill Wendling · 12 years ago
- a4bd58b Use SequenceToOffsetTable to generate instruction name table for AsmWriter. by Craig Topper · 12 years ago
- caa2c40 Start cleaning up the InlineCost class. This switches to sentinel values by Chandler Carruth · 12 years ago
- b66e943 Fix some 80-col. violations I introduced with the A2 PPC64 core. by Hal Finkel · 12 years ago
- 19aa2b5 Enable prefetch generation on PPC64. by Hal Finkel · 12 years ago
- 730acfb Add LdStSTD* itin. for the PPC64 A2 core. by Hal Finkel · 12 years ago
- 4ac9081 This commit contains a few changes that had to go in together. by Nadav Rotem · 12 years ago
- 16d6eae Fix typo. by Lang Hames · 12 years ago
- 3f31d49 Set the default PPC node scheduling preference to ILP (for the embedded cores). by Hal Finkel · 12 years ago
- 800125f Add ppc440 itin. entries for LdStSTD* by Hal Finkel · 12 years ago
- 97c9d4c Use full anti-dep. breaking with post-ra sched. on the embedded ppc cores. by Hal Finkel · 12 years ago
- 4d989ac Add instruction itinerary for the PPC64 A2 core. by Hal Finkel · 12 years ago
- 413b2e7 Use SequenceToOffsetTable to create instruction name table. Saves space particularly on X86 where AVX instructions just add a 'v' to the front of other instructions. by Craig Topper · 12 years ago
- 243018f Emit the LLVM<->DWARF register mapping as a sorted table and use binary search to do the lookup. by Benjamin Kramer · 12 years ago
- dafe48e Belatedly address some code review from Chris. by Chandler Carruth · 12 years ago
- 48ec3b5 Add some more testing to cover the remaining two cases where by Chandler Carruth · 12 years ago
- 6052eef Fix a pretty scary bug I introduced into the always inliner with by Chandler Carruth · 12 years ago
- 0b42f9d Replace four tiny tests with various uses of grep and not with a single by Chandler Carruth · 12 years ago
- 830da40 misched: Add finalizeScheduler to complete the target interface. by Andrew Trick · 12 years ago
- d9182d6 Removing a file that's no longer being used after the recent refactorings by Eli Bendersky · 12 years ago
- 20b529b Split the LdStGeneral PPC itin. class into LdStLoad and LdStStore. by Hal Finkel · 12 years ago
- 6226c49 Add a workaround for building with old versions of clang. by Rafael Espindola · 12 years ago
- f10037b Add a triple to the test. by Rafael Espindola · 12 years ago
- 95d594c Teach CodeGen's version of computeMaskedBits to understand the range metadata. by Rafael Espindola · 12 years ago
- 5b00cea Fix dynamic linking on PPC64. by Hal Finkel · 12 years ago
- f5f256c Fix a typo reported in IRC by someone reviewing this code. by Chandler Carruth · 12 years ago
- b594a84 Give the always-inliner its own custom filter. It shouldn't have to pay by Chandler Carruth · 12 years ago
- 45de584 Remove a bunch of empty, dead, and no-op methods from all of these by Chandler Carruth · 12 years ago
- f2286b0 Initial commit for the rewrite of the inline cost analysis to operate by Chandler Carruth · 12 years ago
- 7384530 Add support to the InstVisitor for visiting a generic callsite. The by Chandler Carruth · 12 years ago
- 7baa27d Move trivial functions into the class definition. by Bill Wendling · 12 years ago
- deee238 Trim headers. by Bill Wendling · 12 years ago
- c94c562 Indent according to LLVM's style guide. by Bill Wendling · 12 years ago
- ab53bc7 Cleanup whitespace and trim some of the #includes. by Bill Wendling · 12 years ago
- 1955c9c Internalize: Remove reference of @llvm.noinline, it was replaced with the noinline attribute a long time ago. by Benjamin Kramer · 12 years ago
- f2cc2ee These strings aren't 'const char *' but 'char *'. by Bill Wendling · 12 years ago
- 76b13ed Cleanup whitespace. by Bill Wendling · 12 years ago
- caf71d4 Free the codegen options when deleting LTO code generator object. by Bill Wendling · 12 years ago
- 168f142 Cleanup whitespace and remove unneeded 'extern' keyword on function definitions. by Bill Wendling · 12 years ago
- 426d571 Clean up the naming in this test. Someone pointed this out in review at by Chandler Carruth · 12 years ago
- c3e9559 FileCheck-ize this test, and generally tidy it up prior to changing by Chandler Carruth · 12 years ago
- 4000afe I noticed in passing that the Metadata getIfExists method was creating a new by Duncan Sands · 12 years ago
- 6173ed9 Correctly vectorize powi. by Hal Finkel · 12 years ago
- 9f2a9d7 comment typo by Andrew Trick · 12 years ago
- b2874df Select static relocation model if it is jitting. by Akira Hatanaka · 12 years ago
- dd9a501 Introduce Register Units: Give each leaf register a number. by Andrew Trick · 12 years ago
- 3ee3661 Add a 2 byte safety margin in offset computations. by Jakob Stoklund Olesen · 12 years ago
- 101c03a Add more debugging output to ARMConstantIslandPass. by Jakob Stoklund Olesen · 12 years ago
- 5ff4bc2 * Set the scope attributes for the ASM symbol we added to be the value passed by Bill Wendling · 12 years ago
- cef670a Rip out emission of the regIsInRegClass function for the asm printer. by Benjamin Kramer · 12 years ago
- bf3c322 ARM fix encoding fixup resolution for ldrd and friends. by Jim Grosbach · 12 years ago
- c19f72b Use SequenceToOffsetTable in emitRegisterNameString. by Jakob Stoklund Olesen · 12 years ago
- 0d4e2ea Reapply 153764 and 153761 with a fix. by Jakob Stoklund Olesen · 12 years ago
- 77ff8bb Revert 153764 and 153761. They broke a --enable-optimized --enable-assertions by Rafael Espindola · 12 years ago
- ad353c6 ARM assembler should prefer non-aliases encoding of cmp. by Jim Grosbach · 12 years ago
- a45e374 ARM encoding for VSWP got the second operand incorrect. by Jim Grosbach · 12 years ago
- 8f1148b ARM can only use narrow encoding for low regs. by Jim Grosbach · 12 years ago
- ecf2d9f Compress SimpleValueType lists by sharing. by Jakob Stoklund Olesen · 12 years ago
- 8f36b0b Compress register lists by sharing suffixes. by Jakob Stoklund Olesen · 12 years ago
- 184440e Add a SequenceToOffsetTable to TableGen. by Jakob Stoklund Olesen · 12 years ago
- 2d30d94 ARM integrated assembler should encoding choice for add/sub imm. by Jim Grosbach · 12 years ago
- 092c5cc Handle unreachable code in the dominates functions. This changes users when by Rafael Espindola · 12 years ago
- 0e4fa5f Re-factored RuntimeDyLd: by Danil Malyshev · 12 years ago
- c0164f8 ARM assembly parsing needs to be paranoid about negative immediates. by Jim Grosbach · 12 years ago
- 7c7121e Add computeMaskedBitsLoad back, as it was the change to instsimplify that by Rafael Espindola · 12 years ago
- 2f1abe9 Add a note about a missed cmov -> sbb opportunity. by Benjamin Kramer · 12 years ago
- 8fd3fcd Cleanup whitespace. Doxygenize comments. And indent to llvm coding standards. by Bill Wendling · 12 years ago
- cb0809b Ensure conditional BL instructions for ARM are given the fixup fixup_arm_condbranch. by James Molloy · 12 years ago
- 1c80f56 ARM target should allow codegenprep to duplicate ret instructions to enable tailcall opt. rdar://11140249 by Evan Cheng · 12 years ago
- c459d31 Testcase for r153710. by Bill Wendling · 12 years ago
- 4108bd3 Add testcase for r153705 by Bill Wendling · 12 years ago
- 84364a4 If we have a VLA that has a "use" in a metadata node that's then used by Bill Wendling · 12 years ago
- f9e894d Change the constant in this testcase so that it results in a constant pool load. by Lang Hames · 12 years ago
- 288967d Revert r153694. It was causing failures in the buildbots. by Bill Wendling · 12 years ago
- 7a4c071 Invalidate liveness in ARMConstantIslandPass. by Jakob Stoklund Olesen · 12 years ago
- ccca22e Prefer even-odd D-register pairs. by Jakob Stoklund Olesen · 12 years ago
- 803d134 Filecheck-ize this test so that it actually tests something reasonable. by Chandler Carruth · 12 years ago
- c0a9f82 Try using vmov.i32 to materialize FP32 constants that can't be materialized by by Lang Hames · 12 years ago
- 4b0b8ef Re-factored RuntimeDyld. Added ExecutionEngine/MCJIT tests. by Danil Malyshev · 12 years ago
- 6c31ee2 Lowercase the tag name to match the rest of dwarf. by Eric Christopher · 12 years ago
- b22e70d ARM assembly 'cmp lr, #0' should not encode using 'cmn'. by Jim Grosbach · 12 years ago
- 182c34b The shuffle scheduler is only available in asserts build - make misched-new.ll by Lang Hames · 12 years ago
- 85bdf2e Handle register copies for the new ARM register classes. by Jakob Stoklund Olesen · 12 years ago
- e13cea4 Drop O4 from the llc manpage, it was removed in r70445. by Benjamin Kramer · 12 years ago
- 616c841 Make x86 REP_MOV* and REP_STO instructions use the correct operand sizes in 64-bit mode. by Lang Hames · 12 years ago
- 95c677e Fix missed files in JIT unittests Makefile by Danil Malyshev · 12 years ago
- 21ecc2f Expand FREM. by Akira Hatanaka · 12 years ago
- c6a96ff Add more constness to CodeGenRegisters. by Jakob Stoklund Olesen · 12 years ago
- 41e2073 Don't PRE compares. by Jakob Stoklund Olesen · 12 years ago
- 7347840 Replace assert(0) with llvm_unreachable to avoid warnings about dropping off the end of a non-void function in Release builds. by Benjamin Kramer · 12 years ago
- b8ca988 Add support for objc property decls according to the page at: by Eric Christopher · 12 years ago
- 24b8780 Make some headway towards compiling all of LLVM. by Bill Wendling · 12 years ago
- 9e6ddcb Only allow symbolic names for (v)cmpss/sd/ps/pd encodings 8-31 to be used with 'v' version of instructions. by Craig Topper · 12 years ago
- 76d0310 For X86, change load/dec-or-inc/store into dec-or-inc, respectively. by Joel Jones · 12 years ago
- 3c6b29b Cleanup whitespace. by Bill Wendling · 12 years ago
- 9f3b483 Cache the end() iterator. by Bill Wendling · 12 years ago
- f75f427 Reverted to revision 153616 to unblock build by Joel Jones · 12 years ago
- c367a3e For X86, change load/dec-or-inc/store into dec-or-inc, respectively. by Joel Jones · 12 years ago
- 8b4c502 Enable machine code verification in the entire code generator. by Jakob Stoklund Olesen · 12 years ago
- 7881166 Enable machine code verification after PreSched2 passes. by Jakob Stoklund Olesen · 12 years ago