- 23a22cd Don't print default values for NumberOfAuxSymbols and AuxiliaryData. by Rafael Espindola · 11 years ago
- 0962b16 Handle (at least don't crash on) relocations with no symbols. by Rafael Espindola · 11 years ago
- 5fd5fe0 Move BinaryRef to a new include/llvm/Object/YAML.h file. by Rafael Espindola · 11 years ago
- 6afb65c Revert "R600: Add a pass that merge Vector Register" by Rafael Espindola · 11 years ago
- 6c1202c Handle relocations that don't point to symbols. by Rafael Espindola · 11 years ago
- cc5a6cb [docs] Replace non-existent LLVM_YAML_UNIQUE_TYPE() macro by Sean Silva · 11 years ago
- bbbdba8 R600: Add a pass that merge Vector Register by Vincent Lejeune · 11 years ago
- e67a4af R600: Const/Neg/Abs can be folded to dot4 by Vincent Lejeune · 11 years ago
- 00ed010 Cortex-R5 can issue Thumb2 integer division instructions. by Evan Cheng · 11 years ago
- 8a22708 Revert series of sched model patches until I figure out what is going on. by Arnold Schwaighofer · 11 years ago
- f500aa0 ARM sched model: Add VFP div instruction on Swift by Arnold Schwaighofer · 11 years ago
- 858f6f8 ARM sched model: Add SIMD/VFP load/store instructions on Swift by Arnold Schwaighofer · 11 years ago
- e52041c ARM sched model: Add integer VFP/SIMD instructions on Swift by Arnold Schwaighofer · 11 years ago
- f3a2329 ARM sched model: Add integer load/store instructions on Swift by Arnold Schwaighofer · 11 years ago
- 755d129 ARM sched model: Add integer arithmetic instructions on Swift by Arnold Schwaighofer · 11 years ago
- eb9948e ARM sched model: Cortex A9 - More InstRW sched resources by Arnold Schwaighofer · 11 years ago
- 002faf2 ARM sched model: Add branch thumb instructions by Arnold Schwaighofer · 11 years ago
- 16d9150 ARM sched model: Add branch thumb2 instructions by Arnold Schwaighofer · 11 years ago
- 36ea791 ARM sched model: Add branch instructions by Arnold Schwaighofer · 11 years ago
- fdbca2f ARM sched model: Add preload thumb2 instructions by Arnold Schwaighofer · 11 years ago
- d3b8445 ARM sched model: Add preload instructions by Arnold Schwaighofer · 11 years ago
- 23cb39a ARM sched model: Add more ALU and CMP thumb instructions by Arnold Schwaighofer · 11 years ago
- 1942e32 ARM sched model: Add more ALU and CMP thumb2 instructions by Arnold Schwaighofer · 11 years ago
- 4c53731 ARM sched model: Add more ALU and CMP instructions by Arnold Schwaighofer · 11 years ago
- 611c6e1 ARM sched model: Add divsion, loads, branches, vfp cvt by Arnold Schwaighofer · 11 years ago
- ede7eea ARMInstrInfo: Improve isSwiftFastImmShift by Arnold Schwaighofer · 11 years ago
- 54d63cc SubtargetEmitter fix by Arnold Schwaighofer · 11 years ago
- 2b18526 Fix link. by Richard Smith · 11 years ago
- 1e06bcb Sparc: No functionality change. Cleanup whitespaces, comment formatting etc., by Venkatraman Govindaraju · 11 years ago
- 5a57dbe IndVarSimplify: check if loop invariant expansion can trap by David Majnemer · 11 years ago
- 35e7751 ARM: Fix crash in ARM backend inside of ARMConstantIslandPass by David Majnemer · 11 years ago
- 8240ef0 Remove "-Wl,-seg1addr -Wl,0xE0000000" from link options. by Bob Wilson · 11 years ago
- 98017a0 R600: Swizzle texture/export instructions by Vincent Lejeune · 11 years ago
- 932843832 R600: Add a test for r183108 by Vincent Lejeune · 11 years ago
- babae05 Second part of pr16069 by Rafael Espindola · 11 years ago
- deb2e9c Typo: s/caes/cases/ in SimplifyCFG by Hans Wennborg · 11 years ago
- f102f31 Preserve const correctness. by Benjamin Kramer · 11 years ago
- 164de54 Test commit for user vmedic, to verify commit access. One line of comment is added to MipsAsmParser.cpp. by Vladimir Medic · 11 years ago
- 888ca96 [llvm-symbolizer] Avoid calling slow getSymbolSize for Mach-O files. Assume that symbols with zero size are in fact large enough. by Alexey Samsonov · 11 years ago
- 1c611ec We are now in 3.4 land. We don't need the 3.3 releaese notes in ToT anymore. by Bill Wendling · 11 years ago
- b30718a IEEE-754R 5.7.2 General Operations is* operations (except for isCanonical). by Michael Gottesman · 11 years ago
- f3d3952 Silencing an MSVC warning about mixing bool and unsigned int. by Aaron Ballman · 11 years ago
- f56a6de Silencing an MSVC warning about */ being found outside of a comment. by Aaron Ballman · 11 years ago
- 45c7544 Fix a defect in code-layout pass, improving Benchmarks/Olden/em3d/em3d by about 30% by Shuxin Yang · 11 years ago
- 4526d1c Delete dead safety check. by Nick Lewycky · 11 years ago
- 3931bdb SimplifyCFG: Do not transform PHI to select if doing so would be unsafe by David Majnemer · 11 years ago
- 404fa72 SimplifyCFG: Small cleanup, use ICmpInst::isEquality() by David Majnemer · 11 years ago
- 031a179 Remove dead code. by Rafael Espindola · 11 years ago
- 15e5c46 Update RuntimeDyldELF::findOPDEntrySection the new relocation iterators. by Rafael Espindola · 11 years ago
- d1100b3 Enable mcjit tests on ppc64 when building with cmake. by Rafael Espindola · 11 years ago
- e5fcc0d R600/SI: Add support for work item and work group intrinsics by Tom Stellard · 11 years ago
- e7397ee R600/SI: Add a calling convention for compute shaders by Tom Stellard · 11 years ago
- e86f9d7 R600/SI: Custom lower i64 sign_extend by Tom Stellard · 11 years ago
- 17e8ad6 R600/SI: Adjust some instructions' out register class after ISel by Tom Stellard · 11 years ago
- b89a467 R600/SI: Handle REG_SEQUENCE in fitsRegClass() by Tom Stellard · 11 years ago
- 051a28e R600/SI: Handle nodes with glue results correctly SITargetLowering::foldOperands() by Tom Stellard · 11 years ago
- 8a72c73 R600/SI: Fixup CopyToReg register class in PostprocessISelDAG() by Tom Stellard · 11 years ago
- 1321835 R600/SI: Add support for global loads by Tom Stellard · 11 years ago
- 4956bc6 R600/SI: Rework MUBUF store instructions by Tom Stellard · 11 years ago
- 0c92287 R600: 3 op instructions have no write bit but the result are store in PV by Vincent Lejeune · 11 years ago
- fdf7ab1 R600: CALL_FS consumes a stack size entry by Vincent Lejeune · 11 years ago
- 96fe0be R600: use capital letter for PV channel by Vincent Lejeune · 11 years ago
- 0962e14 R600: Constraints input regs of interp_xy,_zw by Vincent Lejeune · 11 years ago
- 3e1d45b [asan] ASan Linux MIPS32 support (llvm part), patch by Jyun-Yan Y by Kostya Serebryany · 11 years ago
- b8ce457 X86: sub_xmm registers are 128 bits wide. by Ahmed Bougacha · 11 years ago
- 625b109 Correct handling invalid filename in llvm-symbolizer by Alexey Samsonov · 11 years ago
- abff3aa Introduce needsCleanup() for APFloat and APInt. by Manuel Klimek · 11 years ago
- e7cbb79 Sparc: Add support for indirect branch and blockaddress in Sparc backend. by Venkatraman Govindaraju · 11 years ago
- 891c0cd [Object/COFF] Fix Windows .lib name handling. by Rui Ueyama · 11 years ago
- 85cc972 Sparc: When storing 0, use %g0 directly in the store instruction instead of by Venkatraman Govindaraju · 11 years ago
- 65ca7aa Sparc: Combine add/or/sethi instruction with restore if possible. by Venkatraman Govindaraju · 11 years ago
- 0a972fa [Object/COFF] Add dos_header, pe32{,plus}_header and data_directory. by Rui Ueyama · 11 years ago
- 2ee6c7f Whitespace. by Jim Grosbach · 11 years ago
- dd48226 Sparc: Perform leaf procedure optimization by default by Venkatraman Govindaraju · 11 years ago
- 44dbb74 Try to avoid "integer literal too big" warnings from older GCCs. by Benjamin Kramer · 11 years ago
- e4546cb When determining the new index for an insertelement, we may not assume that an by Nick Lewycky · 11 years ago
- a0b34d6 Sparc: Mark functions calling llvm.vastart and llvm.returnaddress intrinsics as non-leaf functions. by Venkatraman Govindaraju · 11 years ago
- f7dad78 SimplifyCFG: Fix typo in comment for ComputeSpeculationCost by David Majnemer · 11 years ago
- 7c2b4be Move getRealLinkageName to a common place and remove all the duplicates of it. by Benjamin Kramer · 11 years ago
- 6dd56e6 Move object construction into [] so the temporary can be moved. by Benjamin Kramer · 11 years ago
- da8b91a DenseMap: Move the key into place when we use the move version of operator[]. by Benjamin Kramer · 11 years ago
- 8e85192 APInt: Simplify code. No functionality change. by Benjamin Kramer · 11 years ago
- 77e5c2a APFloat: Use isDenormal instead of hand-rolled code to check for denormals. by Benjamin Kramer · 11 years ago
- 95a565a Disable new legacy JIT test on ARM. by Tim Northover · 11 years ago
- 3ba14fa Revert r183069: "TMP: LEA64_32r fixing" by Tim Northover · 11 years ago
- 4d3ace4 TMP: LEA64_32r fixing by Tim Northover · 11 years ago
- 85c622d X86: change MOV64ri64i32 into MOV32ri64 by Tim Northover · 11 years ago
- 72ad17c [Sparc] Generate correct code for leaf functions with stack objects by Venkatraman Govindaraju · 11 years ago
- 2e2922c Removed a comment above an include which is unnecessary and added a missing closing @} for a doxygen comment. by Michael Gottesman · 11 years ago
- 8a70f58 Added method comments for getZero,getInf. by Michael Gottesman · 11 years ago
- 7f88a3b Updated APFloat's comments to fit the LLVM style guide. by Michael Gottesman · 11 years ago
- 23ed37a Make SubRegIndex size mandatory, following r183020. by Ahmed Bougacha · 11 years ago
- cd8e3c4 Prevent loop-unroll from making assumptions about undefined behavior. by Andrew Trick · 11 years ago
- 3443108 Temporarily Revert "X86: change MOV64ri64i32 into MOV32ri64" as it by Eric Christopher · 11 years ago
- 813419e Const-ify some printing and dumping code for DIEValues. by Eric Christopher · 11 years ago
- 769d24a Add support for adding the contents of a StringRef to the MD5 hash. by Eric Christopher · 11 years ago
- cbb45aa Convert more unsigned char -> uint8_t. by Eric Christopher · 11 years ago
- 92bd43b Fix comment. by Eric Christopher · 11 years ago
- 800e6ee Move "unsigned char" -> "uint8_t". by Eric Christopher · 11 years ago
- 35b4cf8 LoopVectorize: Change API call to get the backedge taken count by Arnold Schwaighofer · 11 years ago