- 1633076 Neon does not support vector divide or remainder. Expand them. by Bob Wilson · 16 years ago
- 74dc72e Expand all v2f64 arithmetic operations for Neon. by Bob Wilson · 16 years ago
- cd3b9a4 Fix pr4939: Change FPCCToARMCC to translate SETOLE to ARMCC::LS. by Bob Wilson · 16 years ago
- 2ba62ef Unbreak getOnesVector() / getZeroVector() to use valid ARM extended imm's. by Anton Korobeynikov · 16 years ago
- 63476a8 Reference to hidden symbols do not have to go through non-lazy pointer in non-pic mode. rdar://7187172. by Evan Cheng · 16 years ago
- 65c3c8f Retype from unsigned to CallingConv::ID accordingly. Approved by Bob Wilson. by Sandeep Patel · 16 years ago
- 8a3198b Add support for generating code for vst{234}lane intrinsics. by Bob Wilson · 16 years ago
- 243fcc5 Generate code for vld{234}_lane intrinsics. by Bob Wilson · 16 years ago
- 3fb2b1e Clean up LSDA name generation and use for SJLJ exception handling. This by Jim Grosbach · 16 years ago
- b00c03b EXTRACT_VECTOR_ELEMENT can have result type different from element type. by Anton Korobeynikov · 16 years ago
- 71624cc Do not assert on too wide splats we don't support. by Anton Korobeynikov · 16 years ago
- e4e4ed3 Let Darwin linker auto-synthesize stubs and lazy-pointers. This deletes a bunch of nasty code in ARM asm printer. by Evan Cheng · 16 years ago
- b5fb428 Hopefully the final missing part :( scalar_to_vector is fully legal now by Anton Korobeynikov · 16 years ago
- fdf189a Transform float scalar_to_vector into subreg accesses. by Anton Korobeynikov · 16 years ago
- 31fb12f Remove unneeded ARM-specific DAG nodes for VLD* and VST* Neon operations. by Bob Wilson · 16 years ago
- 1cb852b Expand scalar_to_vector - we don't have any isel logic for it now by Anton Korobeynikov · 16 years ago
- ce392eb Make x86 test actually test x86 code generation. Fix the by Eli Friedman · 16 years ago
- c692cb7 Match VTRN, VZIP, and VUZP shuffles. Restore the tests for these operations, by Bob Wilson · 16 years ago
- 051cfd6 Fix some typos and use type-based isel for VZIP/VUZP/VTRN by Anton Korobeynikov · 16 years ago
- 1c8e581 Add lowering of ARM 4-element shuffles to multiple instructios via perfectshuffle-generated table. by Anton Korobeynikov · 16 years ago
- 62e84f1 Add nodes & dummy matchers for some v{zip,uzp,trn} instructions by Anton Korobeynikov · 16 years ago
- 8e6c2b9 Expand EXTRACT_SUBVECTOR by Anton Korobeynikov · 16 years ago
- 5da894f Provide vext.{16,32} by Anton Korobeynikov · 16 years ago
- d0ac234 Use masks not nodes for vector shuffle predicates. Provide set of 'legal' masks, so legalizer won't infinite cycle by Anton Korobeynikov · 16 years ago
- de95c1b8 Add support for Neon VEXT (vector extract) shuffles. by Bob Wilson · 16 years ago
- af56634 Reapply r79127. It was fixed by d0k. by Bill Wendling · 16 years ago
- f865ea8 Revert r79127. It was causing compilation errors. by Bill Wendling · 16 years ago
- 088880c Change allowsUnalignedMemoryAccesses to take type argument since some targets by Evan Cheng · 16 years ago
- bc9b754 Turn on if-conversion for thumb2. by Evan Cheng · 16 years ago
- 72977a4 Allow targets to specify their choice of calling conventions per by Anton Korobeynikov · 16 years ago
- e6c835f Add Thumb2 lsr hooks. by Evan Cheng · 16 years ago
- 59bc060 80 col violation. by Evan Cheng · 16 years ago
- 22cac0d Now that all the legal Neon shuffles (or at least the ones that have been by Bob Wilson · 16 years ago
- c1d287b Create a new ARM-specific DAG node, VDUP, to represent a splat from a by Bob Wilson · 16 years ago
- 0ce3710 During legalization, change Neon vdup_lane operations from shuffles to by Bob Wilson · 16 years ago
- 1d0be15 Push LLVMContexts through the IntegerType APIs. by Owen Anderson · 16 years ago
- bfcbb50 Add a fixme message about canonicalizing floating-point vector types. by Bob Wilson · 16 years ago
- bab812b Revert r78852 for now. I want to do this differently, but I don't have time by Bob Wilson · 16 years ago
- 2886506 Add a comment to describe why vector shuffles are legalized to custom DAG nodes. by Bob Wilson · 16 years ago
- d06791f Use cast<> instead of dyn_cast<> in places where the type is known. by Bob Wilson · 16 years ago
- af385ba Recognize Neon VDUP shuffles during legalization instead of selection. by Bob Wilson · 16 years ago
- d8e1757 Recognize Neon VREV shuffles during legalization instead of selection. by Bob Wilson · 16 years ago
- bff3923 Add catch block handling to SjLj exception handling. by Jim Grosbach · 16 years ago
- 007ea27 Shrink Thumb2 movcc instructions. by Evan Cheng · 16 years ago
- 825b72b Split EVT into MVT and EVT, the former representing _just_ a primitive type, while by Owen Anderson · 16 years ago
- 764ab52 Whitespace cleanup. Remove trailing whitespace. by Jim Grosbach · 16 years ago
- b0abb4d Use vAny type to get rid of Neon intrinsics that differed only in whether by Bob Wilson · 16 years ago
- 1b747ad SjLj based exception handling unwinding support. This patch is nasty, brutish by Jim Grosbach · 16 years ago
- e50ed30 Rename MVT to EVT, in preparation for splitting SimpleValueType out into its own struct type. by Owen Anderson · 16 years ago
- d6662ad SimpleValueType-ify a few more methods on TargetLowering. by Owen Anderson · 16 years ago
- 7067184 Continue the SimpleValueType-ification. by Owen Anderson · 16 years ago
- 8619864 It turns out most of the thumb2 instructions are not allowed to touch SP. The semantics of such instructions are unpredictable. We have just been lucky that tests have been passing. by Evan Cheng · 16 years ago
- b36ec86 Implement Neon VST[234] operations. by Bob Wilson · 16 years ago
- 058c251 Remove redundand checks: the only way to have, e.g. f32 RegVT is exactly by Anton Korobeynikov · 16 years ago
- 14d9495 Unbreak the stuff, this is ugly, but we cannot do better for now with 'plain' C calling conv. by Anton Korobeynikov · 16 years ago
- 567d14f Missed pieces for ARM HardFP ABI. Patch by Sandeep Patel! by Anton Korobeynikov · 16 years ago
- 98ca4f2 Major calling convention code refactoring. by Dan Gohman · 16 years ago
- 4a3d35a Change DAG nodes for Neon VLD2/3/4 operations to return multiple results. by Bob Wilson · 16 years ago
- a599bff Lower Neon VLD* intrinsics to custom DAG nodes, and manually allocate the by Bob Wilson · 16 years ago
- 916afdb Minor cleanup. No functional changes intended. by Bob Wilson · 16 years ago
- a6d6586 Lower CONCAT_VECTOR during legalization instead of matching it during isel. by Bob Wilson · 16 years ago
- 80ec279 convert ctors/dtors section to be in TLOF instead of TAI. by Chris Lattner · 16 years ago
- b620724 Fix Thumb2 function call isel. Thumb1 and Thumb2 should share the same by Evan Cheng · 16 years ago
- f26e03b refactor section construction in TLOF to be through an explicit by Chris Lattner · 16 years ago
- cf661e2 Lower a 128-bit BUILD_VECTOR with 2 elements to a pair of INSERT_VECTOR_ELTs. by Bob Wilson · 16 years ago
- 5657c01 Optimize Thumb2 jumptable to use tbb / tbh when all the offsets fit in byte / halfword. by Evan Cheng · 16 years ago
- e7c329b In thumb2 mode, add pc is unpredictable. Use add + mov pc instead (that is until more optimization goes in). by Evan Cheng · 16 years ago
- 4bb253c the apple "ld_classic" linker doesn't support .literal16 in 32-bit by Chris Lattner · 16 years ago
- f014412 Rip all of the global variable lowering logic out of TargetAsmInfo. Since by Chris Lattner · 16 years ago
- 8bb9e48 Add support for ARM Neon VREV instructions. by Bob Wilson · 16 years ago
- 66ac531 Change Thumb2 jumptable codegen to one that uses two level jumps: by Evan Cheng · 16 years ago
- e922c02 Get rid of the Pass+Context magic. by Owen Anderson · 16 years ago
- 4fb63d0 fix an arm codegen bug (the same as PR4482 on ppc) where available_externally by Chris Lattner · 16 years ago
- 3eadf00 Remove an extra space. by Bob Wilson · 16 years ago
- c23197a llvm_unreachable->llvm_unreachable(0), LLVM_UNREACHABLE->llvm_unreachable. by Torok Edwin · 16 years ago
- d2559bf Fix comment typos. by Bob Wilson · 16 years ago
- c25e758 assert(0) -> LLVM_UNREACHABLE. by Torok Edwin · 16 years ago
- d1474d0 Thread LLVMContext through MVT and related parts of SDISel. by Owen Anderson · 16 years ago
- f1daf7d Use common code for both ARM and Thumb-2 instruction and register info. by David Goodwin · 16 years ago
- ab7c09b Start converting to new error handling API. by Torok Edwin · 16 years ago
- 7f6aa2b Remove the vicmp and vfcmp instructions. Because we never had a release with by Nick Lewycky · 16 years ago
- 5b9fcd1 Add some more Thumb2 multiplication instructions. by Evan Cheng · 16 years ago
- 6b61cd1 Add NumFixedArgs attribute to CallSDNode which indicates the number of fixed arguments in a vararg call. by Tilmann Scheller · 16 years ago
- d27c9fc Add thumb2 sign / zero extend with rotate instructions. by Evan Cheng · 16 years ago
- e88d5ce Thumb2 pre/post indexed loads. by Evan Cheng · 16 years ago
- 0412957 80 col violation. by Evan Cheng · 16 years ago
- b4202b8 Update comments to make it clear that the function alignment is the Log2 of the by Bill Wendling · 16 years ago
- 20c568f Add an "alignment" field to the MachineFunction object. It makes more sense to by Bill Wendling · 16 years ago
- c0309b4 Rename ARMcmpNZ to ARMcmpZ and use it to represent comparisons that set only the Z flag (i.e. eq and ne). Make ARMcmpZ commutative. by David Goodwin · 16 years ago
- 24062ac Thumb-2 has CLZ. by David Goodwin · 16 years ago
- 5bafff3 Add support for ARM's Advanced SIMD (NEON) instruction set. by Bob Wilson · 16 years ago
- b101948 Add comments. by Evan Cheng · 16 years ago
- 7a42b08 Should be using Bcc (average) latency to determine if-conversion threshold, not BL. by Evan Cheng · 16 years ago
- 8557c2b Latency information for ARM v6. It's rough and not yet hooked up. Right now we are only using branch latency to determine if-conversion limits. by Evan Cheng · 16 years ago
- cd82861 Remove UseThumbBacktraces. Just check if subtarget is darwin. by Evan Cheng · 16 years ago
- 385f5a9 Address review comments: add 3 ARM calling conventions. by Anton Korobeynikov · 16 years ago
- 0eebf65 The attached patches implement most of the ARM AAPCS-VFP hard float by Anton Korobeynikov · 16 years ago
- 2f95461 Only 64-bit targets support TImode libcalls. Disable the TImode shift libcalls by Bob Wilson · 16 years ago
- e6abdff Fix pr4202: Disable CodePlacementOpt for ARM. The ARMConstantIslandPass has by Bob Wilson · 16 years ago
- f957012 Update the names of the exception handling sjlj instrinsics to by Jim Grosbach · 16 years ago