- ffde080 Convert VLD1 and VLD2 instructions to use pseudo-instructions until by Bob Wilson · 15 years ago
- 5bcb8a6 temporarily revert r112664, it is causing a decoding conflict, and by Chris Lattner · 15 years ago
- 43a6c5e We have a chance for an optimization. Consider this code: by Bill Wendling · 15 years ago
- e5ce4f6 Use pseudo instructions for VST1 and VST2. by Bob Wilson · 15 years ago
- fd7fd94 We don't need to custom-select VLDMQ and VSTMQ anymore. by Bob Wilson · 15 years ago
- d4bfd54 Change ARM VFP VLDM/VSTM instructions to use addressing mode #4, just like by Bob Wilson · 15 years ago
- 01ba461 Use pseudo instructions for VST3. by Bob Wilson · 15 years ago
- 70e48b2 Use pseudo instructions for VST1d64Q. by Bob Wilson · 15 years ago
- 709d592 Start converting NEON load/stores to use pseudo instructions, beginning here by Bob Wilson · 15 years ago
- 00d3dda Don't call tablegen'ed Predicate_* functions in the ARM target. by Jakob Stoklund Olesen · 15 years ago
- a2c519b Add -disable-shifter-op to disable isel of shifter ops. On Cortex-a9 the shifts cost extra instructions so it might be better to emit them separately to take advantage of dual-issues. by Evan Cheng · 15 years ago
- 78dfbc3 Also use REG_SEQUENCE for VTBX instructions. by Bob Wilson · 15 years ago
- d491d6e Use REG_SEQUENCE nodes to make the table registers for VTBL instructions be by Bob Wilson · 15 years ago
- 978189e Remove an unused and a pointless variable. by Duncan Sands · 15 years ago
- e368b46 Eliminate unnecessary uses of getZExtValue(). by Dan Gohman · 15 years ago
- 07f6e80 Remove the hidden "neon-reg-sequence" option. The reg sequences are working by Bob Wilson · 15 years ago
- 40cbe7d For NEON vectors with 32- or 64-bit elements, select BUILD_VECTORs and by Bob Wilson · 15 years ago
- 51e28e6 Early implementation of tail call for ARM. by Dale Johannesen · 15 years ago
- 18f30e6 Clean up 80 column violations. No functional change. by Jim Grosbach · 15 years ago
- 13ef840 Add the cc_out operand for t2RSBrs instructions. I missed this when I changed by Bob Wilson · 15 years ago
- 7bb31e3 Fix a few places that depended on the numeric value of subreg indices. by Jakob Stoklund Olesen · 15 years ago
- 558661d Switch ARMRegisterInfo.td to use SubRegIndex and eliminate the parallel enums by Jakob Stoklund Olesen · 15 years ago
- 3c3195c Target instruction selection should copy memoperands. by Evan Cheng · 15 years ago
- 6206124 Turn on -neon-reg-sequence by default. by Evan Cheng · 15 years ago
- 8f6de38 Model vst lane instructions with REG_SEQUENCE. by Evan Cheng · 15 years ago
- 7189fd0 Model 128-bit vld lane with REG_SEQUENCE. by Evan Cheng · 15 years ago
- 7092c2b Model 64-bit lane vld with REG_SEQUENCE. by Evan Cheng · 15 years ago
- 12c2469 Model VST*_UPD and VST*oddUPD pair with REG_SEQUENCE. by Evan Cheng · 15 years ago
- 5c6aba2 Model VLD*_UPD and VLD*odd_UPD pair with REG_SEQUENCE. by Evan Cheng · 15 years ago
- 7f68719 Fix comments. by Evan Cheng · 15 years ago
- 0ce537a Model some vst3 and vst4 with reg_sequence. by Evan Cheng · 15 years ago
- e9e2ba0 Model some vld3 instructions with REG_SEQUENCE. by Evan Cheng · 15 years ago
- 603afbf Model vld2 / vst2 with reg_sequence. by Evan Cheng · 15 years ago
- 429009b Add a missing break statement to fix unintentional fall-through by Bob Wilson · 15 years ago
- d31f00b Fix unintentional fallthrough. Patch by Edmund Grimley-Evans <Edmund.Grimley-Evans@arm.com> by Jim Grosbach · 15 years ago
- de8aa4e Model CONCAT_VECTORS of two 64-bit values as a REG_SEQUENCE. by Evan Cheng · 15 years ago
- 94cc6d3 With -neon-reg-sequence, models forming a Q register from a pair of consecutive D registers as a REG_SEQUENCE. by Evan Cheng · 15 years ago
- 3a1287b Update ARM DAGtoDAG for matching UBFX instruction for unsigned bitfield by Jim Grosbach · 15 years ago
- d858e90 Use const qualifiers with TargetLowering. This eliminates several by Dan Gohman · 15 years ago
- 47b7b9f Use getAL() rather than a major constant. by Evan Cheng · 15 years ago
- 3a1588a Use default lowering of DYNAMIC_STACKALLOC. As far as I can tell, ARM isle is doing the right thing and codegen looks correct for both Thumb and Thumb2. by Evan Cheng · 15 years ago
- 0ea7d21 ARM SelectDYN_ALLOC should emit a copy from SP rather than referencing SP directly. In cases where there are two dyn_alloc in the same BB it would have caused the old SP value to be reused and badness ensues. rdar://7493908 by Evan Cheng · 15 years ago
- df9a4f0 Fix VLDMQ and VSTMQ instructions to use the correct encoding and address modes. by Bob Wilson · 15 years ago
- 11d9899 Change VST1 instructions for loading Q register values to operate on pairs by Bob Wilson · 15 years ago
- 621f195 Change VLD1 instructions for loading Q register values to operate on pairs by Bob Wilson · 15 years ago
- a697975 Rename some VLD1/VST1 instructions to match the implementation, i.e., the by Bob Wilson · 15 years ago
- 226036e Re-commit r98683 ("remove redundant writeback flag from ARM address mode 6") by Bob Wilson · 15 years ago
- 95ffecd Rename some instructions for consistency and sanity: use "_UPD" suffix for by Bob Wilson · 15 years ago
- a43e6bf Revert 98683. It is breaking something in the disassembler. by Bob Wilson · 15 years ago
- bb6c77e Remove redundant writeback flag from ARM address mode 6. Also remove the by Bob Wilson · 15 years ago
- 7c306da Sink InstructionSelect() out of each target into SDISel, and rename it by Chris Lattner · 15 years ago
- 014bf21 Split SelectionDAGISel::IsLegalAndProfitableToFold to by Evan Cheng · 15 years ago
- 518bb53 move target-independent opcodes out of TargetInstrInfo by Chris Lattner · 16 years ago
- f609bb8 Fix r93758. Use isel patterns instead of c++ selection code to select rbit and make sure we pick different instructions for ARM vs. Thumb2. by Evan Cheng · 16 years ago
- 3482c80 Patch by David Conrad: by Jim Grosbach · 16 years ago
- 507d32a Fix an off-by-one error that caused the chain operand to be dropped from Neon by Bob Wilson · 16 years ago
- eeb3a00 Change SelectCode's argument from SDValue to SDNode *, to make it more by Dan Gohman · 16 years ago
- 5cdc3a9 Materialize global addresses via movt/movw pair, this is always better by Anton Korobeynikov · 16 years ago
- ac0869d Add predicate operand to NEON instructions. Fix lots (but not all) 80 col violations in ARMInstrNEON.td. by Evan Cheng · 16 years ago
- 9ef4835 Fix codegen of conditional move of immediates. We were not making use of the immediate forms of cmov instructions at all. by Evan Cheng · 16 years ago
- 07ba906 Refactor cmov selection code out to a separate function. No functionality change. by Evan Cheng · 16 years ago
- ed54de4 80 col violation. by Evan Cheng · 16 years ago
- e516549 Use Unified Assembly Syntax for the ARM backend. by Jim Grosbach · 16 years ago
- 8a5ec86 Support alignment specifier for NEON vld/vst instructions by Jim Grosbach · 16 years ago
- 73bb251 Remove uninteresting and confusing debug output. by Dan Gohman · 16 years ago
- 69e8445 Prune unnecessary include. by Bob Wilson · 16 years ago
- 6a3b5ee Test commit. Added '.' to the comment line. by Johnny Chen · 16 years ago
- 8000c6c Don't generate sbfx / ubfx with negative lsb field. Patch by David Conrad. by Evan Cheng · 16 years ago
- 2095659 Match more patterns to movt. by Evan Cheng · 16 years ago
- 681a2ad Remove unused variables to fix build warning. by Bob Wilson · 16 years ago
- 24f995d Refactor code to select NEON VST intrinsics. by Bob Wilson · 16 years ago
- 3e36f13 Refactor code to select NEON VLD intrinsics. by Bob Wilson · 16 years ago
- 9649344 More refactoring. NEON vst lane intrinsics can share almost all the code for by Bob Wilson · 16 years ago
- a7c397c Refactor code for selecting NEON load lane intrinsics. by Bob Wilson · 16 years ago
- e72142a More Neon clean-up: avoid the need for custom-lowering vld/st-lane intrinsics by Bob Wilson · 16 years ago
- 765cc0b Revise ARM inline assembly memory operands to require the memory address to by Bob Wilson · 16 years ago
- 4e1ed88 Fix method name in comment, per Bob Wilson. by Sandeep Patel · 16 years ago
- 47eedaa Add ARMv6T2 SBFX/UBFX instructions. Approved by Anton Korobeynikov. by Sandeep Patel · 16 years ago
- 5631139 Add codegen support for NEON vst4lane intrinsics with 128-bit vectors. by Bob Wilson · 16 years ago
- 8cdb269 Add codegen support for NEON vst3lane intrinsics with 128-bit vectors. by Bob Wilson · 16 years ago
- c5c6edb Add codegen support for NEON vst2lane intrinsics with 128-bit vectors. by Bob Wilson · 16 years ago
- 62e053e Add codegen support for NEON vld4lane intrinsics with 128-bit vectors. by Bob Wilson · 16 years ago
- 0bf7d99 Add codegen support for NEON vld3lane intrinsics with 128-bit vectors. by Bob Wilson · 16 years ago
- 30aea9d Add codegen support for NEON vld2lane intrinsics with 128-bit vectors. by Bob Wilson · 16 years ago
- cd7e327 Clean up some unnecessary initializations. by Bob Wilson · 16 years ago
- af4a891 Clean up a comment (indentation was wrong). by Bob Wilson · 16 years ago
- deb3141 Add codegen support for NEON vst4 intrinsics with <1 x i64> vectors. by Bob Wilson · 16 years ago
- 5adf60c Add codegen support for NEON vst3 intrinsics with <1 x i64> vectors. by Bob Wilson · 16 years ago
- 24e04c5 Add codegen support for NEON vst2 intrinsics with <1 x i64> vectors. by Bob Wilson · 16 years ago
- 0ea38bb Add codegen support for NEON vld4 intrinsics with <1 x i64> vectors. by Bob Wilson · 16 years ago
- c67160c Add codegen support for NEON vld3 intrinsics with <1 x i64> vectors. by Bob Wilson · 16 years ago
- a428808 Add codegen support for NEON vld2 intrinsics with <1 x i64> vectors. by Bob Wilson · 16 years ago
- 63c9063 Add codegen support for NEON vst4 intrinsics with 128-bit vectors. by Bob Wilson · 16 years ago
- 66a7063 Add codegen support for NEON vst3 intrinsics with 128-bit vectors. by Bob Wilson · 16 years ago
- d285575 Add codegen support for NEON vst2 intrinsics with 128-bit vectors. by Bob Wilson · 16 years ago
- 7708c22 Add codegen support for NEON vld4 intrinsics with 128-bit vectors. by Bob Wilson · 16 years ago
- ff8952e Add codegen support for NEON vld3 intrinsics with 128-bit vectors. by Bob Wilson · 16 years ago
- 228c08b Rearrange code for selecting vld2 intrinsics. No functionality change. by Bob Wilson · 16 years ago
- 3bf12ab Add codegen support for NEON vld2 operations on quad registers. by Bob Wilson · 16 years ago
- 522ce97 Pass the optimization level when constructing the ARM instruction selector. by Bob Wilson · 16 years ago