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gerrit-public.fairphone.software / fp2-dev / platform / external / llvm / 28a193ed8b4b37593afb76f9130eacf393ea9383
  1. 28a193e Add an LLVM IR version of code sinking. This uses the same simple algorithm by Dan Gohman · 14 years ago
  2. 5374195 Const-ify some stuff. by Dan Gohman · 14 years ago
  3. 5040436 Convert the DebugInfo classes dump() methods into print(raw_ostream &) by Dan Gohman · 14 years ago
  4. 733783b Document graphviz passes for the (post) dominator tree. by Tobias Grosser · 14 years ago
  5. 435d499 Use VLD2q32 / VST2q32 to reload / spill QQ (pair of Q) registers when stack slot is sufficiently aligned. Use VLDMD / VSTMD otherwise. by Evan Cheng · 14 years ago
  6. 07a6d93 Use VSTMD / VLDMD for spills and reloads of Q registers instead of VSTMQ / VLDQ. The later are aliases which ought to be eliminated but we can't because they are used for storing and loading v2f64 values. by Evan Cheng · 14 years ago
  7. 403d312 Revert r103133 and add testcase from PR7066. by Nick Lewycky · 14 years ago
  8. 0d88104 When rematerializing, use the debug location of the original by Dan Gohman · 14 years ago
  9. ad9e619 Adjust tests affected by llvm-gcc 103229. All results here match gcc-4.2. by Dale Johannesen · 14 years ago
  10. fb95f89 Transfer debug location information from PHI nodes to resulting lowered copies. by Dan Gohman · 14 years ago
  11. cc751bb Print debug information for SDNodes. by Dan Gohman · 14 years ago
  12. 281d65d Disable the new unknown-location code for now. It causes a major by Dan Gohman · 14 years ago
  13. e2c3a49 Revert r103213. It broke several sections of live website. by mike-m · 14 years ago
  14. c10b5af Remove VLD1q and VST1q for reloading and spilling Q registers. Just use VLD1q64 / VST1q64 and reference sub-registers. by Evan Cheng · 14 years ago
  15. 271cc67 Disable man->postscript and man->pdf doc generation unless explicitly by mike-m · 14 years ago
  16. d0d425b Cleanup unneeded dirs after docs overhaul. by mike-m · 14 years ago
  17. 68cb319 Overhauled llvm/clang docs builds. Closes PR6613. by mike-m · 14 years ago
  18. c26ae5a MC/X86: X86AbsMemAsmOperand is subclass of X86NoSegMemAsmOperand. by Daniel Dunbar · 14 years ago
  19. e1611f2 fix rdar://7947167 - llvm-mc doesn't match movsq by Chris Lattner · 14 years ago
  20. 1a8b789 Eliminated the classification of control registers into %ecr_ by Sean Callanan · 14 years ago
  21. a5d0b54 MC/X86: Error out if we see a non-constant FK_Data_1 or FK_Data_2 fixup, since by Daniel Dunbar · 14 years ago
  22. 34dcc6f Add a DebugLoc argument to TargetInstrInfo::copyRegToReg, so that it by Dan Gohman · 14 years ago
  23. 746ad69 Add argument TargetRegisterInfo to loadRegFromStackSlot and storeRegToStackSlot. by Evan Cheng · 14 years ago
  24. ac963b3 Add a testcase for r103135, explicitly representing unknown by Dan Gohman · 14 years ago
  25. e9b3ac2 80 col violation. by Evan Cheng · 14 years ago
  26. c52edc7 Fix handling of unreachable blocks in the SSAUpdater. The previous code only by Bob Wilson · 14 years ago
  27. 429009b Add a missing break statement to fix unintentional fall-through by Bob Wilson · 14 years ago
  28. d31f00b Fix unintentional fallthrough. Patch by Edmund Grimley-Evans <Edmund.Grimley-Evans@arm.com> by Jim Grosbach · 14 years ago
  29. eae216c Fix "warning: extra ';' inside a struct or union" when building llvm with clang by Shantonu Sen · 14 years ago
  30. 5fe03c0 Revert r103137, fix for $ in labels. It looks like we can't actually handle this by Daniel Dunbar · 14 years ago
  31. b63387a Re-apply 103156 and 103157. 103156 didn't break anything. 10315 exposed a coalescer bug that's fixed by 103170. by Evan Cheng · 14 years ago
  32. 62bb2f6 Fixes a coalescer bug that caused llc to crash on 2009-11-30-LiveVariablesBug.ll by Evan Cheng · 14 years ago
  33. 44ed2c3 Fix some stylistic issues with my last commit. by Sean Hunt · 14 years ago
  34. 1ef7c82 Revert r103157, which broke test/CodeGen/ARM/2009-11-30-LiveVariablesBug.ll. by Dan Gohman · 14 years ago
  35. f865cb5 Revert r103156 since it was breaking the build bots. by Eric Christopher · 14 years ago
  36. 0657279 Handle the case where open(2) or close(2) is interrupted by a signal when by Dan Gohman · 14 years ago
  37. 9c35ee2 Fix an obvious bug in isMoveInstr. It needs to return sub-register indices. by Evan Cheng · 14 years ago
  38. 4ffc22a Adding pseudo 256-bit registers QQ0 . . . QQ7 to represent pairs of Q registers. These will be used to model VLD2 / VST2 instructions in order to get substantially better codegen for them. by Evan Cheng · 14 years ago
  39. d31c549 Cosmetic changes. by Evan Cheng · 14 years ago
  40. 7f2f436 storeRegToStackSlot has forgotten about QPR_8 register class. by Evan Cheng · 14 years ago
  41. 5fe89d0 Handle EWOULDBLOCK as EAGAIN. And add a comment explaining why by Dan Gohman · 14 years ago
  42. 5758d4c make -filetype=obj default to emitting its output to foo.obj by Chris Lattner · 14 years ago
  43. 7539584 Update LabelsBeforeInsn also, when creating unknown-position labels. by Dan Gohman · 14 years ago
  44. b4202db Fix PR7054 - Assertion `Symbol->isUndefined() && "Cannot define a symbol twice!"' failed. by Chris Lattner · 14 years ago
  45. 97c94b8 In bottom-up mode, defer the materialization of local constant values. by Dan Gohman · 14 years ago
  46. a7a0ed7 Add an "IsBottomUp" member function to FastISel, which will be used to by Dan Gohman · 14 years ago
  47. 851f87c fix rdar://7946934 - in some limited cases, the assembler should by Chris Lattner · 14 years ago
  48. 2940213 Cleanup of ARMv7M support. Move hardware divide and Thumb2 extract/pack by Jim Grosbach · 14 years ago
  49. 1cc0d62 Emit debug info for MachineInstrs with unknown debug locations, instead by Dan Gohman · 14 years ago
  50. b7d0688 Fix some ..'s by Chris Lattner · 14 years ago
  51. 51bfd45 Fix PR6520. An earlyclobber physreg must not be allocated to anything else. by Jakob Stoklund Olesen · 14 years ago
  52. 08bbda3 Test case for pr2394 and r102979. by Stuart Hastings · 14 years ago
  53. be192dd Fixed a sign-extension bug in the X86 disassembler by Sean Callanan · 14 years ago
  54. d47f3c8 Use getValue() for PHINodes when direct NodeMap access does not work. by Devang Patel · 14 years ago
  55. 7d25521 Select an ARM-hosted cross build with a separate makefile target instead of by Bob Wilson · 14 years ago
  56. 676b2df Do not pre-allocate references of D registers pairs if they are extracted from the same Q register and are in the right order. by Evan Cheng · 14 years ago
  57. bc1c98d fix copy/paste oops. by Jim Grosbach · 14 years ago
  58. 9f2cda7 No-ops emitted for scheduling don't correspond with anything in the by Dan Gohman · 14 years ago
  59. 3a548e7 Add tests for ARMV7M divide instruction use by Jim Grosbach · 14 years ago
  60. b1dc393 Add initial support for ARMv7M subtarget and cortex-m3 cpu. Patch by by Jim Grosbach · 14 years ago
  61. bc78653 Use the right version of "append" to combine two SmallVectors. by Bob Wilson · 14 years ago
  62. 9ad2aaf remove unneeded underscores. by Jim Grosbach · 14 years ago
  63. ab42ec3 Convert to filecheck by Jim Grosbach · 14 years ago
  64. 2d7fd61 MC/Mach-O: Mark absolute variable's appropriately, and add Mach-O support for by Daniel Dunbar · 14 years ago
  65. c304718 MC: Reject attempts to define a variable symbol. by Daniel Dunbar · 14 years ago
  66. 8d627d3 MC: Make setVariableValue check the redefinition condition a bit more strongly. by Daniel Dunbar · 14 years ago
  67. 3d720fb Move REG_SEQUENCE removal to 2addr pass. by Evan Cheng · 14 years ago
  68. ea03e10 Implement rdar://7415680 - Twine integer support lacks greatness by Chris Lattner · 14 years ago
  69. 15cdda2 Rearrange the suppressions files to be by-architecture instead of by-problem. by Jeffrey Yasskin · 14 years ago
  70. de8aa4e Model CONCAT_VECTORS of two 64-bit values as a REG_SEQUENCE. by Evan Cheng · 14 years ago
  71. d2c2d18 Trim include. by Evan Cheng · 14 years ago
  72. 3749943 Teach liveintervalanalysis about virtual registers which are defined by reg_sequence instructions that are formed by registers defined by distinct instructions. e.g. by Evan Cheng · 14 years ago
  73. 91dd419b Add a suppressions file for an intermittent "leak" under RegisterPass. by Jeffrey Yasskin · 14 years ago
  74. 08a408a MC: Rename MCSymbol::{g,s}etValue -> MCSymbol::{g,s}etVariableValue. by Daniel Dunbar · 14 years ago
  75. ae7fb0b MC/Mach-O/x86_64: Relocations in debug sections should use local relocations by Daniel Dunbar · 14 years ago
  76. e4eae84 lit: Allow test_format to be None. by Daniel Dunbar · 14 years ago
  77. 66760be Try again if write(2) reports an recoverable error. by Benjamin Kramer · 14 years ago
  78. d1dd5ed Add newline to end of file to avoid warning when building llvm with clang by Shantonu Sen · 14 years ago
  79. f4f0690 Revert 102941, we're going to do this via attr and can just by Eric Christopher · 14 years ago
  80. dc896a4 Include the right header for toupper by Sean Hunt · 14 years ago
  81. 84e2f95 Add an emitter to handle the list of clang statement nodes. by Sean Hunt · 14 years ago
  82. 4aad88d Combine the implementations of the core part of the SSAUpdater and by Bob Wilson · 14 years ago
  83. d2760d1 Update comment. by Eric Christopher · 14 years ago
  84. af1465b add the ability to associate 'category' names with clang diagnostics by Chris Lattner · 14 years ago
  85. 94cc6d3 With -neon-reg-sequence, models forming a Q register from a pair of consecutive D registers as a REG_SEQUENCE. by Evan Cheng · 14 years ago
  86. 826bdfa Do not pre-allocate for registers which form a REG_SEQUENCE. by Evan Cheng · 14 years ago
  87. afff40a Teach PHI elimination to remove REG_SEQUENCE instructions and update references of the source operands with references of the destination with subreg indices. e.g. by Evan Cheng · 14 years ago
  88. 55cd6cb Use llvm.foo as the intrinsic, rather than llvm.dbg.value. Since the by Duncan Sands · 14 years ago
  89. 34414a6 Defer adding critical edges to the "toSplit" list until after checking for by Bob Wilson · 14 years ago
  90. cd46501 one more thing. by Chris Lattner · 14 years ago
  91. 860e0b4 update instructions for llvm-gcc4, the brave new world! PR7037 by Chris Lattner · 14 years ago
  92. d4ac35b "on the rare occasion the SPU BE produces illegal assembly - it tries to emit an add instruction of the form 'a reg, reg, imm'." by Chris Lattner · 14 years ago
  93. e9f0fb4 MC/X86: Chris pointed that 'as' isn't consistent in accepting the long form of by Daniel Dunbar · 14 years ago
  94. 28428cd Rename variables for consistency. by Evan Cheng · 14 years ago
  95. c918d60 MC/X86: Add "support" for matching ATT style mnemonic prefixes. by Daniel Dunbar · 14 years ago
  96. d29f528 Fix a problem exposed by my previous commit and noticed by a release-asserts by Duncan Sands · 14 years ago
  97. 203f7cb Fix a variant of PR6112 found by thinking about it: when doing by Duncan Sands · 14 years ago
  98. 2f256f4 fix operand indexes when outputting InvokeInsts by Gabor Greif · 14 years ago
  99. 9c48837 Set DW_AT_APPLE_omit_frame_ptr in endFunction() where MachineFunction is available all the time. by Devang Patel · 14 years ago
  100. acd8cab Use the SCEVAddRecExpr::getPostIncExpr utility function instead by Dan Gohman · 14 years ago