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gerrit-public.fairphone.software / fp2-dev / platform / external / llvm / 28c1d29b09a1d6d92ba91211aceeee59d7f5f07f / lib / Target / X86 / X86InstrSSE.td
  1. 28c1d29 lower the last of the MRMInitReg instructions in MCInstLower. by Chris Lattner · 15 years ago
  2. 95eb2ee by David Greene · 15 years ago
  3. b1f4981 Remove target attribute break-sse-dep. Instead, do not fold load into sse partial update instructions unless optimizing for size. by Evan Cheng · 15 years ago
  4. 400073d On recent Intel u-arch's, folding loads into some unary SSE instructions can by Evan Cheng · 15 years ago
  5. 108934c Instruction fixes, added instructions, and AsmString changes in the by Sean Callanan · 15 years ago
  6. c363094 Optimize splat of a scalar load into a shuffle of a vector load when it's legal. e.g. by Evan Cheng · 15 years ago
  7. b9e6b34 Recommitting PALIGNR shift width fixes. by Sean Callanan · 15 years ago
  8. 1bbf6d1 Reverting PALIGNR fix until I figure out how this broke the Clang testsuite. by Sean Callanan · 15 years ago
  9. 201dfa7 Fixed PALIGNR to take 8-bit rotations in all cases. by Sean Callanan · 15 years ago
  10. d15ac2f Re-apply 89011. It's not to be blamed. by Evan Cheng · 15 years ago
  11. 6db07ea Revert 89011. Buildbot thinks it might be breaking stuff. by Evan Cheng · 15 years ago
  12. 574186f A few more instructions that should be marked re-materializable. by Evan Cheng · 15 years ago
  13. 600c043 - Check memoperand alignment instead of checking stack alignment. Most load / store folding instructions are not referencing spill stack slots. by Evan Cheng · 15 years ago
  14. 0b10b91 x86 vector shuffle cleanup/fixes: by Nate Begeman · 15 years ago
  15. 761411c Fix a couple of shuffle patterns to use movhlps instead by Eric Christopher · 15 years ago
  16. 533297b Rename usesCustomDAGSchedInserter to usesCustomInserter, and update a by Dan Gohman · 15 years ago
  17. 8932116 X86 palignr intrinsics immediate field is in bits. ISel must transform it into bytes. by Evan Cheng · 15 years ago
  18. a09008b Add support for matching shuffle patterns with palignr. by Nate Begeman · 15 years ago
  19. 4a0b3e1 Add support for rematerializing FsFLD0SS and FsFLD0SD as constant-pool by Dan Gohman · 15 years ago
  20. 5ab9403 Added a variety of floating-point and SSE instructions. by Sean Callanan · 15 years ago
  21. 47234e6 Fixed PCMPESTRM128 to have opcode 0x60 instead of 0x62, as specified by the by Sean Callanan · 15 years ago
  22. b120ab4 Implement sse4.2 string/text processing instructions: by Eric Christopher · 15 years ago
  23. 7417b76 Add 'isCodeGenOnly' bit to Instruction .td records. by Daniel Dunbar · 15 years ago
  24. 027c2b1 Fix up whitespace, remove commented out code. by Eric Christopher · 15 years ago
  25. 338825c llvm-mc/AsmMatcher: Change assembler parser match classes to their own record by Daniel Dunbar · 15 years ago
  26. 98164af Extend comment on ParserMatchClass .td field, and add some missing by Daniel Dunbar · 15 years ago
  27. b4dc13c Add crc32 instruction and intrinsics. Add a new class of prefix by Eric Christopher · 15 years ago
  28. 44b93ff Whitespace and 80-col cleanup. by Eric Christopher · 15 years ago
  29. a4714e0 Add a new register class to describe operands that can't be SP, by Dan Gohman · 15 years ago
  30. 71c6753 Add support for gcc __builtin_ia32_ptest{z,c,nzc} intrinsics. Lower by Eric Christopher · 15 years ago
  31. fbd6687 Update insertps handling based on feedback. Move to a v4f32 style by Eric Christopher · 15 years ago
  32. 1e5cdea Support insertps via the intrinsic and add a couple of simple by Eric Christopher · 15 years ago
  33. 7e2242b Fix for PR2484: add an SSE1 pattern for a shuffle we normally prefer to by Eli Friedman · 15 years ago
  34. 9d47b8d Fix an obvious typo. by Eli Friedman · 15 years ago
  35. 2265ba0 The MONITOR and MWAIT instructions have insufficient information for by Bill Wendling · 15 years ago
  36. 8a0b2da Fix MOVMSKPDrr encoding. by Evan Cheng · 15 years ago
  37. ed7f56b Fix PSIGND encoding bug. Patch by Sean Callanan. by Evan Cheng · 15 years ago
  38. 3b1259b "The instructions MMX_PSADBWrm and MMX_PSADBWrr have opcode 0b11100000 (e0), but by Bill Wendling · 15 years ago
  39. bc9be21 Fix sfence jit encoding. Patch by Sean Callanan. by Evan Cheng · 15 years ago
  40. 0af934e 80 col violations. by Evan Cheng · 15 years ago
  41. ec8eee2 Fix infinite recursion in the C++ code which handles movddup by making it unnecessary. by Nate Begeman · 15 years ago
  42. 9008ca6 2nd attempt, fixing SSE4.1 issues and implementing feedback from duncan. by Nate Begeman · 15 years ago
  43. 15684b2 Revert 69952. Causes testsuite failures on linux x86-64. by Rafael Espindola · 15 years ago
  44. b706d29 PR2957 by Nate Begeman · 15 years ago
  45. 094fad3 Re-apply 68552. Tested by bootstrapping llvm-gcc and using that to build llvm. by Rafael Espindola · 15 years ago
  46. 044b534 Temporarily revert r68552. This was causing a failure in the self-hosting LLVM by Bill Wendling · 15 years ago
  47. 2a6411b Reduce code duplication on the TLS implementation. by Rafael Espindola · 15 years ago
  48. 236aa8a ADDS{D|S}rr_Int and MULS{D|S}rr_Int are not commutable. The users of these intrinsics expect the high bits will not be modified. by Evan Cheng · 16 years ago
  49. b9a47b8 Generate better code for v8i16 shuffles on SSE2 by Nate Begeman · 16 years ago
  50. 1d76864 Handle llvm.x86.sse2.maskmov.dqu in 64-bit. by Evan Cheng · 16 years ago
  51. b3379fb A few more isAsCheapAsAMove. by Evan Cheng · 16 years ago
  52. 1632782 The memory alignment requirement on some of the mov{h|l}p{d|s} patterns are 16-byte. That is overly strict. These instructions read / write f64 memory locations without alignment requirement. by Evan Cheng · 16 years ago
  53. b134709 Whitespace and other minor adjustments to make SSE instructions have by Dan Gohman · 16 years ago
  54. af9b952 Fixed x86 code generation of multiple for v2i64. It was incorrect for SSE4.1. by Mon P Wang · 16 years ago
  55. 15511cf Rename isSimpleLoad to canFoldAsLoad, to better reflect its meaning. by Dan Gohman · 16 years ago
  56. 62c939d Mark x86's V_SET0 and V_SETALLONES with isSimpleLoad, and teach X86's by Dan Gohman · 16 years ago
  57. 4b299d4 Fix lfence and mfence encoding. These look like MRM5r and MRM6r instructions except they do not have any operands. The RegModRM byte is encoded with register number 0. by Evan Cheng · 16 years ago
  58. a7250dd Fix the predicate for memop64 to be a regular load, not just an unindexed load. by Dan Gohman · 16 years ago
  59. 3358629 Now that predicates can be composed, simplify several of by Dan Gohman · 16 years ago
  60. e397acc Fix SSE4.1 roundss, roundsd. While the instructions have by Dale Johannesen · 16 years ago
  61. ae436ce Certain patterns involving the "movss" instruction were marked as requiring SSE2, when in reality movss is an SSE1 instruction. by Anders Carlsson · 16 years ago
  62. 5e249b4 "The original bug was a complaint that _mm_srli_si128 mis-compiled when passed by Bill Wendling · 16 years ago
  63. b7a75a5 Implement "punpckldq %xmm0, $xmm0" as "pshufd $0x50, %xmm0, %xmm" unless optimizing for code size. by Evan Cheng · 16 years ago
  64. c739489 unpckhps requires sse1, punpckhdq requires sse2. by Evan Cheng · 16 years ago
  65. 0b457f0 With sse3 and when the source is a load or has multiple uses, favors movddup over shuffp*, pshufd, etc. Without sse3 or when the source is from a register, make use of movlhps by Evan Cheng · 16 years ago
  66. 89d4a28 pmovsxbq etc. requires sse4.1. by Evan Cheng · 16 years ago
  67. ca57f78 Fix patterns for SSE4.1 move and sign extend instructions. Also add instructions which fold VZEXT_MOVL and VZEXT_LOAD. by Evan Cheng · 16 years ago
  68. f5aeb1a Rename ConstantSDNode::getValue to getZExtValue, for consistency by Dan Gohman · 16 years ago
  69. d0c0fae Fix for PR2687: Add patterns to match sint_to_fp and fp_to_sint for <2 x by Eli Friedman · 16 years ago
  70. 66e1315 FsFLD0S{S|D} and V_SETALLONES are as cheap as moves. by Evan Cheng · 16 years ago
  71. 67ca6be Tablegen generated code already tests the opcode value, so it's not by Dan Gohman · 16 years ago
  72. d9ced09 Add an EXTRACTPSmr pattern to match the pattern that X86ISelLowering creates. by Dan Gohman · 16 years ago
  73. e9d5035 Fix PR2620: Fix X86cmppd selection code so it expects operands to be v2f64. by Evan Cheng · 16 years ago
  74. e99b255 Fix a typo in last commit by Nate Begeman · 16 years ago
  75. 30a0de9 SSE codegen for vsetcc nodes by Nate Begeman · 16 years ago
  76. 331e2bd Fix for PR2472. Use movss to set lower 32-bits of a zero XMM vector. by Evan Cheng · 16 years ago
  77. 4e44443 Horizontal-add instructions are not commutative. by Evan Cheng · 16 years ago
  78. 35b9a77 mpsadbw is commutable. by Evan Cheng · 16 years ago
  79. d4b9c17 Disable some DAG combiner optimizations that may be by Duncan Sands · 16 years ago
  80. f26ffe9 Implement vector shift up / down and insert zero with ps{rl}lq / ps{rl}ldq. by Evan Cheng · 16 years ago
  81. c2ecdc5 Fix the encoding for two more "rm" instructions that were using MRMSrcReg. by Dan Gohman · 16 years ago
  82. bfbbd4d Fixed X86 encoding error CVTPS2PD and CVTPD2PS when the source operand by Mon P Wang · 16 years ago
  83. a315939 Eliminate x86.sse2.punpckh.qdq and x86.sse2.punpckl.qdq. by Evan Cheng · 16 years ago
  84. e716bb1 Eliminate x86.sse2.movs.d, x86.sse2.shuf.pd, x86.sse2.unpckh.pd, and x86.sse2.unpckl.pd intrinsics. These will be lowered into shuffles. by Evan Cheng · 16 years ago
  85. 999dbe6 Remove x86.sse2.loadh.pd and x86.sse2.loadl.pd. These will be lowered into load and shuffle instructions. by Evan Cheng · 16 years ago
  86. cd0baf2 Use movlps / movhps to modify low / high half of 16-byet memory location. by Evan Cheng · 16 years ago
  87. 50f778d Fix a duplicated pattern. by Evan Cheng · 16 years ago
  88. 0b924dc Use PMULDQ for v2i64 multiplies when SSE4.1 is available. And add by Dan Gohman · 16 years ago
  89. b193826 Bug: rcpps can only folds a load if the address is 16-byte aligned. Fixed many 'ps' load folding patterns in X86InstrSSE.td which are missing the proper alignment checks. by Evan Cheng · 16 years ago
  90. c36c0ab Add missing patterns. by Evan Cheng · 16 years ago
  91. 8e8de68 movsd and movq do not require 16-byte alignment. This fixes vec_set-5.ll on Linux. by Evan Cheng · 16 years ago
  92. 32097bd Fix one more encoding bug. by Nate Begeman · 16 years ago
  93. c9bdb00 Fix and encoding error in the psrad xmm, imm8 instruction. by Nate Begeman · 16 years ago
  94. 0d1704b Teach Legalize how to scalarize VSETCC by Nate Begeman · 16 years ago
  95. c2616e4 Initial X86 codegen support for VSETCC. by Nate Begeman · 16 years ago
  96. b70ea0b Some clean up. by Evan Cheng · 16 years ago
  97. 23573e5 Add a pattern to do move the low element of a v4f32 and zero extend the rest. by Evan Cheng · 16 years ago
  98. d880b97 Handle a few more cases of folding load i64 into xmm and zero top bits. by Evan Cheng · 16 years ago
  99. fd17f42 Use movq to move low half of XMM register and zero-extend the rest. by Evan Cheng · 16 years ago
  100. 7e2ff77 Handle vector move / load which zero the destination register top bits (i.e. movd, movq, movss (addr), movsd (addr)) with X86 specific dag combine. by Evan Cheng · 16 years ago