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gerrit-public.fairphone.software / fp2-dev / platform / external / llvm / 2a6411bbbdc6a23605fa206e07fc4f99a3d5dff2 / lib / Target / X86 / X86ISelLowering.h
  1. 2a6411b Reduce code duplication on the TLS implementation. by Rafael Espindola · 15 years ago
  2. 73f24c9 When optimzing a mul by immediate into two, the resulting mul's should get a x86 specific node to avoid dag combiner from hacking on them further. by Evan Cheng · 15 years ago
  3. bddc442 Doxygen-ify comments. by Bill Wendling · 15 years ago
  4. 2004eb6 Correct some comments. Operand numbers start at 0. by Dan Gohman · 15 years ago
  5. 2b9f434 improve comment. by Chris Lattner · 15 years ago
  6. 3112581 Arithmetic instructions don't set EFLAGS bits OF and CF bits by Dan Gohman · 15 years ago
  7. 076aee3 Re-apply 66008, now that the unfoldMemoryOperand bug is fixed. by Dan Gohman · 15 years ago
  8. 29582d1 Revert r66004 for now; it's causing a variety of test failures. by Dan Gohman · 15 years ago
  9. 12bbc52 Teach the x86 backend to eliminate "test" instructions by using the EFLAGS by Dan Gohman · 15 years ago
  10. b9a47b8 Generate better code for v8i16 shuffles on SSE2 by Nate Begeman · 15 years ago
  11. 1fdbc1d Constify TargetInstrInfo::EmitInstrWithCustomInserter, allowing by Dan Gohman · 16 years ago
  12. 33c960f Remove non-DebugLoc versions of getLoad and getStore. by Dale Johannesen · 16 years ago
  13. eacf2dc Need this file too. by Dale Johannesen · 16 years ago
  14. ace1610 DebugLoc propagation. 2/3 through file. by Dale Johannesen · 16 years ago
  15. 9b99485 Fix an indent and a typo. by Nate Begeman · 16 years ago
  16. 8b8a636 Implement a special algorithm for converting uint_to_fp for i32 values on by Bill Wendling · 16 years ago
  17. c13cf13 Make getWidenVectorType const. by Dan Gohman · 16 years ago
  18. 83489bb by Devang Patel · 16 years ago
  19. 5480c04 Fix PR3274: when promoting the condition of a BRCOND node, by Duncan Sands · 16 years ago
  20. c7a37d4 Add instruction patterns and encodings for the x86 bt instructions. by Dan Gohman · 16 years ago
  21. af9b952 Fixed x86 code generation of multiple for v2i64. It was incorrect for SSE4.1. by Mon P Wang · 16 years ago
  22. d350e02 - Use patterns instead of creating completely new instruction matching patterns, by Bill Wendling · 16 years ago
  23. ab55ebd Redo the arithmetic with overflow architecture. I was changing the semantics of by Bill Wendling · 16 years ago
  24. 74c3765 Add sub/mul overflow intrinsics. This currently doesn't have a by Bill Wendling · 16 years ago
  25. 61edeb5 Second stab at target-dependent lowering of everyone's favorite nodes: [SU]ADDO by Bill Wendling · 16 years ago
  26. 1607f05 Change the interface to the type legalization method by Duncan Sands · 16 years ago
  27. 41ea7e7 - Make lowering of "add with overflow" customizable by back-ends. by Bill Wendling · 16 years ago
  28. 0c39719 Add initial support for vector widening. Logic is set to widen for X86. by Mon P Wang · 16 years ago
  29. 1c15bf5 Add an SSE2 algorithm for uint64->f64 conversion. by Dale Johannesen · 16 years ago
  30. 6520e20 Teach DAGCombine to fold constant offsets into GlobalAddress nodes, by Dan Gohman · 16 years ago
  31. dd5b58a FastISel support for exception-handling constructs. by Dan Gohman · 16 years ago
  32. 880ae36 Make atomic Swap work, 64-bit on x86-32. Make it all work in non-pic mode. by Dale Johannesen · 16 years ago
  33. 48c1bc2 Handle some 64-bit atomics on x86-32, some of the time. by Dale Johannesen · 16 years ago
  34. 6158d84 Implement the -fno-builtin option in the front-end, not in the back-end. by Bill Wendling · 16 years ago
  35. 6f287b2 Add the new `-no-builtin' flag. This flag is meant to mimic the GCC by Bill Wendling · 16 years ago
  36. 71d1bf5 Remove misuse of ReplaceNodeResults for atomics with by Dale Johannesen · 16 years ago
  37. 0b457f0 With sse3 and when the source is a load or has multiple uses, favors movddup over shuffp*, pshufd, etc. Without sse3 or when the source is from a register, make use of movlhps by Evan Cheng · 16 years ago
  38. da43bcf Properly handle 'm' inline asm constraints. If a GV is being selected for the addressing mode, it requires the same logic for PIC relative addressing, etc. by Evan Cheng · 16 years ago
  39. d57dd5f Arrange for FastISel code to have access to the MachineModuleInfo by Dan Gohman · 16 years ago
  40. 0ba2bcf Fix these enums' starting values to reflect the way that by Dan Gohman · 16 years ago
  41. 056292f Reverting r56249. On further investigation, this functionality isn't needed. by Bill Wendling · 16 years ago
  42. 9468a9b - Change "ExternalSymbolSDNode" to "SymbolSDNode". by Bill Wendling · 16 years ago
  43. 095cc29 Define CallSDNode, an SDNode subclass for use with ISD::CALL. by Dan Gohman · 16 years ago
  44. 0586d91 Add X86FastISel support for static allocas, and refences by Dan Gohman · 16 years ago
  45. bff66b0 Replace explicit pointer-size constants to TargetData query. by Anton Korobeynikov · 16 years ago
  46. 3df24e6 Create HandlePHINodesInSuccessorBlocksFast, a version of by Dan Gohman · 16 years ago
  47. b388eb8 Fix capitalization in #include of FastISel.h. This unbreaks the build on case-sensitive filesystems. by Ted Kremenek · 16 years ago
  48. c3f44b0 Let tblgen only generate fastisel routines, not the class definition. This makes it easier for targets to define its own fastisel class. by Evan Cheng · 16 years ago
  49. bb46633 Simplify FastISel's constructor argument list, make the FastISel by Dan Gohman · 16 years ago
  50. d9f3c48 The X86 target will soon have an implementation of createFastISel. by Dan Gohman · 16 years ago
  51. 140be2d Add support for 8 and 16 bit forms of __sync builtins on X86. by Dale Johannesen · 16 years ago
  52. 475871a Rename SDOperand to SDValue. by Dan Gohman · 16 years ago
  53. 30a0de9 SSE codegen for vsetcc nodes by Nate Begeman · 16 years ago
  54. 126d907 Rather than having a different custom legalization by Duncan Sands · 16 years ago
  55. 2887310 Added MemOperands to Atomic operations since Atomics touches memory. by Mon P Wang · 16 years ago
  56. 507a58a add missing atomic intrinsic from gcc by Andrew Lenharth · 16 years ago
  57. 83ec4b6 Wrap MVT::ValueType in a struct to get type safety by Duncan Sands · 16 years ago
  58. f26ffe9 Implement vector shift up / down and insert zero with ps{rl}lq / ps{rl}ldq. by Evan Cheng · 16 years ago
  59. 0ef8de3 Fix typos and comments. by Evan Cheng · 16 years ago
  60. f0df031 Make use of vector load and store operations to implement memcpy, memmove, and memset. Currently only X86 target is taking advantage of these. by Evan Cheng · 16 years ago
  61. c9f5f3f Change target-specific classes to use more precise static types. by Dan Gohman · 16 years ago
  62. c2616e4 Initial X86 codegen support for VSETCC. by Nate Begeman · 16 years ago
  63. ad4196b Refactor isConsecutiveLoad from X86 to TargetLowering so DAG combiner can make use of it. by Evan Cheng · 16 years ago
  64. 9018e83 For now, abort when an ISD::VAARG is encountered on x86-64, rather by Dan Gohman · 16 years ago
  65. d880b97 Handle a few more cases of folding load i64 into xmm and zero top bits. by Evan Cheng · 16 years ago
  66. 7e2ff77 Handle vector move / load which zero the destination register top bits (i.e. movd, movq, movss (addr), movsd (addr)) with X86 specific dag combine. by Evan Cheng · 16 years ago
  67. 63307c3 Added addition atomic instrinsics and, or, xor, min, and max. by Mon P Wang · 16 years ago
  68. 30e62c0 Tail call optimization improvements: by Arnold Schwaighofer · 16 years ago
  69. 1f13c68 Fix the SVOffset values for loads and stores produced by by Dan Gohman · 16 years ago
  70. 5e76423 A few inline asm cleanups: by Chris Lattner · 16 years ago
  71. 302cd54 Remove X86_64SRet; it isn't used anymore. by Dan Gohman · 16 years ago
  72. 29e4bdb Fix const-correctness issues with the SrcValue handling in the by Dan Gohman · 16 years ago
  73. 4b5324a This patch corrects the handling of byval arguments for tailcall by Arnold Schwaighofer · 16 years ago
  74. 707e018 Drop ISD::MEMSET, ISD::MEMMOVE, and ISD::MEMCPY, which are not Legal by Dan Gohman · 16 years ago
  75. 7d8143f Make isVectorClearMaskLegal's operand list const. by Dan Gohman · 16 years ago
  76. 920c37a remove Evan's "ugly hack" that sorta attempted to get by Chris Lattner · 16 years ago
  77. 4fe3073 Don't loose incoming argument registers. Fix documentation style. by Arnold Schwaighofer · 16 years ago
  78. 8e6da15 Eliminate the FP_GET_ST0/FP_SET_ST0 target-specific dag nodes, just lower to by Chris Lattner · 16 years ago
  79. 5b8f82e Give TargetLowering::getSetCCResultType() a parameter so that ISD::SETCC's by Scott Michel · 16 years ago
  80. afb23f4 rename FP_SETRESULT -> FP_SET_ST0 by Chris Lattner · 16 years ago
  81. 6fa2f9c rename FpGETRESULT32 -> FpGET_ST0_32 etc. Add support for by Chris Lattner · 16 years ago
  82. 6fd599f Add a target lowering hook to control whether it's worthwhile to compress fp constant. by Evan Cheng · 16 years ago
  83. d19189e 64bit CAS on 32bit x86. by Andrew Lenharth · 16 years ago
  84. 26ed869 all but CAS working on x86 by Andrew Lenharth · 16 years ago
  85. 258bb1b Refactor according to Evan's and Anton's suggestions. by Arnold Schwaighofer · 16 years ago
  86. 865c681 Change the lowering of arguments for tail call optimized by Arnold Schwaighofer · 16 years ago
  87. efec751 - When DAG combiner is folding a bit convert into a BUILD_VECTOR, it should check if it's essentially a SCALAR_TO_VECTOR. Avoid turning (v8i16) <10, u, u, u> to <10, 0, u, u, u, u, u, u>. Instead, simply convert it to a SCALAR_TO_VECTOR of the proper type. by Evan Cheng · 16 years ago
  88. 977a76f Simplify some logic in ComputeMaskedBits. And change ComputeMaskedBits by Dan Gohman · 16 years ago
  89. fd29e0e Convert SelectionDAG::ComputeMaskedBits to use APInt instead of uint64_t. by Dan Gohman · 16 years ago
  90. 14d12ca Enable SSE4 codegen and pattern matching. Add some notes to the README. by Nate Begeman · 16 years ago
  91. 6f0d024 Rename MRegisterInfo to TargetRegisterInfo. by Dan Gohman · 16 years ago
  92. 1a02486 Rename ISD::FLT_ROUNDS to ISD::FLT_ROUNDS_ to avoid conflicting by Dan Gohman · 17 years ago
  93. ff9b373 Even though InsertAtEndOfBasicBlock is an ugly hack it still deserves a proper name. Rename it to EmitInstrWithCustomInserter since it does not necessarily insert by Evan Cheng · 17 years ago
  94. 0d9e976 Work in progress. This patch *fixes* x86-64 calls which are modelled as StructRet but really should be return in registers, e.g. _Complex long double, some 128-bit aggregates. This is a short term solution that is necessary only because llvm, for now, cannot model i128 nor call's with multiple results. by Evan Cheng · 17 years ago
  95. ba2a0b9 Handle 'X' constraint in asm's better. by Dale Johannesen · 17 years ago
  96. 2928650 Let each target decide byval alignment. For X86, it's 4-byte unless the aggregare contains SSE vector(s). For x86-64, it's max of 8 or alignment of the type. by Evan Cheng · 17 years ago
  97. 3d66185 make a method public by Chris Lattner · 17 years ago
  98. 7863116 make it more clear that this predicate only applies to scalar FP types. by Chris Lattner · 17 years ago
  99. 1956d15 introduce a isTypeInSSEReg predicate, which allows us to simplify by Chris Lattner · 17 years ago
  100. da68d30 no need to expand ISD::TRAP to X86ISD::TRAP, just match ISD::TRAP. by Chris Lattner · 17 years ago