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gerrit-public.fairphone.software / fp2-dev / platform / external / llvm / 2a6411bbbdc6a23605fa206e07fc4f99a3d5dff2 / lib / Target / X86 / X86InstrInfo.td
  1. 2a6411b Reduce code duplication on the TLS implementation. by Rafael Espindola · 16 years ago
  2. 73f24c9 When optimzing a mul by immediate into two, the resulting mul's should get a x86 specific node to avoid dag combiner from hacking on them further. by Evan Cheng · 16 years ago
  3. 520ebe6 add 8 and 16 bit TLS moves. add a fixme note on how to remove code duplication. by Rafael Espindola · 16 years ago
  4. 9b922aa Improve sext and zext of TLS variables. by Rafael Espindola · 16 years ago
  5. a065200 Re-apply 66024 with fixes: 1. Fixed indirect call to immediate address assembly. 2. Fixed JIT encoding by making the address pc-relative. by Evan Cheng · 16 years ago
  6. 3014376 Revert r66024. The JIT encoding for CALLpcrel32 is wrong -- see PR3773, and the by Dan Gohman · 16 years ago
  7. b316f90 optimize i8 and i16 tls values. by Rafael Espindola · 16 years ago
  8. 1f4af26 Don't use plain INC32 and DEC32 on x86-64; it needs by Dan Gohman · 16 years ago
  9. 076aee3 Re-apply 66008, now that the unfoldMemoryOperand bug is fixed. by Dan Gohman · 16 years ago
  10. ae3f2b6 Fix PR3666: isel calls to constant addresses. by Evan Cheng · 16 years ago
  11. 29582d1 Revert r66004 for now; it's causing a variety of test failures. by Dan Gohman · 16 years ago
  12. 12bbc52 Teach the x86 backend to eliminate "test" instructions by using the EFLAGS by Dan Gohman · 16 years ago
  13. 09a2609e Add '(implicit EFLAGS)' for AND, OR, XOR, NEG, INC, and DEC by Dan Gohman · 16 years ago
  14. b3379fb A few more isAsCheapAsAMove. by Evan Cheng · 16 years ago
  15. 6a86bd7 Implement multiple with overflow by 2 with an add instruction. by Evan Cheng · 16 years ago
  16. 51a0437 Map address space 256 to gs; similar mappings could be supported for the by Nate Begeman · 16 years ago
  17. aaf414c Favors generating "not" over "xor -1". For example. by Evan Cheng · 16 years ago
  18. f31408d Disable the register+memory forms of the bt instructions for now. Thanks by Dan Gohman · 16 years ago
  19. 4afe15b Add bt instructions that take immediate operands. by Dan Gohman · 16 years ago
  20. 0c89b7e Fix a few more JIT encoding issues in the BT instructions. by Dan Gohman · 16 years ago
  21. fbb7486 Add patterns to match conditional moves with loads folded by Dan Gohman · 16 years ago
  22. 305fceb Define instructions for cmovo and cmovno. by Dan Gohman · 16 years ago
  23. 653456c X86_COND_C and X86_COND_NC are alternate mnemonics for by Dan Gohman · 16 years ago
  24. ccb6976 Do not isel load folding bt instructions for pentium m, core, core2, and AMD processors. These are significantly slower than a load followed by a bt of a register. by Evan Cheng · 16 years ago
  25. f1e9fd5 Fix some JIT encodings. by Chris Lattner · 16 years ago
  26. d1e3229 BT memory operands load from their address operand. by Chris Lattner · 16 years ago
  27. c7a37d4 Add instruction patterns and encodings for the x86 bt instructions. by Dan Gohman · 16 years ago
  28. d350e02 - Use patterns instead of creating completely new instruction matching patterns, by Bill Wendling · 16 years ago
  29. ab55ebd Redo the arithmetic with overflow architecture. I was changing the semantics of by Bill Wendling · 16 years ago
  30. 74c3765 Add sub/mul overflow intrinsics. This currently doesn't have a by Bill Wendling · 16 years ago
  31. 6ecf5ce Fix typo, psuedo -> pseudo. by Nick Lewycky · 16 years ago
  32. 15511cf Rename isSimpleLoad to canFoldAsLoad, to better reflect its meaning. by Dan Gohman · 16 years ago
  33. 9f24874 Reapply r60382. This time, don't mark "ADC" nodes with "implicit EFLAGS". by Bill Wendling · 16 years ago
  34. e3b3c00 Temporarily revert r60382. It caused CodeGen/X86/i2k.ll and others to fail. by Bill Wendling · 16 years ago
  35. a047bca - Have "ADD" instructions return an implicit EFLAGS. by Bill Wendling · 16 years ago
  36. 3fafd93 Generate something sensible for an [SU]ADDO op when the overflow/carry flag is by Bill Wendling · 16 years ago
  37. c99da13 Don't set neverHasSideEffects on x86's divide instructions, since by Dan Gohman · 16 years ago
  38. b74f370 Generate code for TLS instructions. by Nicolas Geoffray · 16 years ago
  39. 109a562 Add implicit defs of XMM8 to XMM15 on 32-bit call instructions. While this is not technically true, it tells tblgen that these instructions "clobber" the entire XMM register file. by Evan Cheng · 16 years ago
  40. 63f9720 Fun x86 encoding tricks: when adding an immediate value of 128, by Dan Gohman · 16 years ago
  41. 74feef2 Define patterns for shld and shrd that match immediate by Dan Gohman · 16 years ago
  42. 3358629 Now that predicates can be composed, simplify several of by Dan Gohman · 16 years ago
  43. e563bbc Change CALLSEQ_BEGIN and CALLSEQ_END to take TargetConstant's as by Chris Lattner · 16 years ago
  44. 2cb48ea Model hardwired inputs & outputs of x86 8-bit divides correctly. by Dale Johannesen · 16 years ago
  45. 880ae36 Make atomic Swap work, 64-bit on x86-32. Make it all work in non-pic mode. by Dale Johannesen · 16 years ago
  46. 1b54c7f Pass MemOperand through for 64-bit atomics on 32-bit, by Dale Johannesen · 16 years ago
  47. 48c1bc2 Handle some 64-bit atomics on x86-32, some of the time. by Dale Johannesen · 16 years ago
  48. 6d4b052 Split x86's ADJCALLSTACK instructions into 32-bit and 64-bit forms. by Dan Gohman · 16 years ago
  49. 2662d55 Mark CALL instructions as having a Use of ESP/RSP. by Dan Gohman · 16 years ago
  50. d47e0b6 Fix PR2835. Do not change the width of a volatile load. by Evan Cheng · 16 years ago
  51. b7a75a5 Implement "punpckldq %xmm0, $xmm0" as "pshufd $0x50, %xmm0, %xmm" unless optimizing for code size. by Evan Cheng · 16 years ago
  52. ca57f78 Fix patterns for SSE4.1 move and sign extend instructions. Also add instructions which fold VZEXT_MOVL and VZEXT_LOAD. by Evan Cheng · 16 years ago
  53. 056292f Reverting r56249. On further investigation, this functionality isn't needed. by Bill Wendling · 16 years ago
  54. 9468a9b - Change "ExternalSymbolSDNode" to "SymbolSDNode". by Bill Wendling · 16 years ago
  55. f5aeb1a Rename ConstantSDNode::getValue to getZExtValue, for consistency by Dan Gohman · 16 years ago
  56. eb9f892 Transform (x << (y&31)) -> (x << y). This takes advantage of the fact x86 shift instructions 2nd operand (shift count) is limited to 0 to 31 (or 63 in the x86-64 case). by Evan Cheng · 16 years ago
  57. e00a8a2 Split the ATOMIC NodeType's to include the size, e.g. by Dale Johannesen · 16 years ago
  58. 449416d Reverting r55190, r55191, and r55192. They broke the build with this error message: by Bill Wendling · 16 years ago
  59. b4ae2da Anyext tweaks for x86. When extloading a value to i32 or i64, choose by Dan Gohman · 16 years ago
  60. 0bfa1bf Move the handling of ANY_EXTEND, SIGN_EXTEND_INREG, and TRUNCATE by Dan Gohman · 16 years ago
  61. 67ca6be Tablegen generated code already tests the opcode value, so it's not by Dan Gohman · 16 years ago
  62. 5bf1b4e Revert r55018 and apply the correct "fix" for the 64-bit sub_and_fetch atomic. by Bill Wendling · 16 years ago
  63. 108ecf3 Add support for the __sync_sub_and_fetch atomics and friends for X86. The code by Bill Wendling · 16 years ago
  64. 140be2d Add support for 8 and 16 bit forms of __sync builtins on X86. by Dale Johannesen · 16 years ago
  65. 8a1510d Re-introduce the 8-bit subreg zext-inreg patterns for x86-32, by Dan Gohman · 16 years ago
  66. 165660e xchg does not modify FLAGS. by Dan Gohman · 16 years ago
  67. 11ba3b1 Reapply r54147 with a constraint to only use the 8-bit by Dan Gohman · 16 years ago
  68. 7ba145b Revert 54147. by Dan Gohman · 16 years ago
  69. b1e8cad Add x86 isel patterns to match what would be a ZERO_EXTEND_INREG operation, by Dan Gohman · 16 years ago
  70. f88a6fa Fix encoding of atomic compare and swap for i64 by Anton Korobeynikov · 16 years ago
  71. 2887310 Added MemOperands to Atomic operations since Atomics touches memory. by Mon P Wang · 16 years ago
  72. 359e937 XOR32rr, etc. are not AsCheapAsMove, but MOV32ri, etc. are. by Evan Cheng · 16 years ago
  73. 507a58a add missing atomic intrinsic from gcc by Andrew Lenharth · 16 years ago
  74. e4c67cd Teach the DAGISelEmitter to not compute the variable_ops operand by Dan Gohman · 16 years ago
  75. b410617 Add patterns for CALL32m and CALL64m. They aren't matched in most by Dan Gohman · 16 years ago
  76. d35121a Fix a tblgen problem handling variable_ops in tblgen instruction by Dan Gohman · 16 years ago
  77. 75cf88f XOR?RI instructions aren't as cheap as moves. by Bill Wendling · 16 years ago
  78. bd0879d Implement "AsCheapAsAMove" for some obviously cheap instructions: xor and the by Bill Wendling · 16 years ago
  79. 6bf8770 Doh. Alignment is in bytes, not in bits. by Evan Cheng · 16 years ago
  80. b656443 - Fix the pasto in the fix for a previous pasto. by Evan Cheng · 16 years ago
  81. 11b6793 - Don't treat anyext 16-bit load as a 32-bit load if it's volatile. by Evan Cheng · 16 years ago
  82. fa7fd33 On x86, it's safe to treat i32 load anyext as a normal i32 load. Ditto for i8 anyext load to i16. by Evan Cheng · 16 years ago
  83. 9499b71 Fix a copy+paste bug; pseudo-instructions shouldn't have encoding information. by Dan Gohman · 16 years ago
  84. 63307c3 Added addition atomic instrinsics and, or, xor, min, and max. by Mon P Wang · 16 years ago
  85. 6625eff Add General Dynamic TLS model for X86-64. Some parts looks really ugly (look for tlsaddr pattern), by Anton Korobeynikov · 16 years ago
  86. 30e62c0 Tail call optimization improvements: by Arnold Schwaighofer · 16 years ago
  87. 80f5404 Fix MMX_MOVQ2DQrr pattern. It's illegal to do a bitconvert from a smaller type to a larger one. by Evan Cheng · 16 years ago
  88. bb6939d xchg which references a memory operand does not need to lock prefix. Atomicity is guaranteed. by Evan Cheng · 16 years ago
  89. 7e03280 - Fix atomic operation JIT encoding. - Remove unused instructions. by Evan Cheng · 16 years ago
  90. 3f73bea Also support Intel asm syntax. by Evan Cheng · 16 years ago
  91. 9d1a81a Fix assembly code for atomic operations. by Evan Cheng · 16 years ago
  92. 6795ebb 80 col fix by Nate Begeman · 17 years ago
  93. e771ebd Allow certain lea instructions to be rematerialized. by Evan Cheng · 17 years ago
  94. 4fe3073 Don't loose incoming argument registers. Fix documentation style. by Arnold Schwaighofer · 17 years ago
  95. da47e6e Replace all target specific implicit def instructions with a target independent one: TargetInstrInfo::IMPLICIT_DEF. by Evan Cheng · 17 years ago
  96. 6634e26 Get rid of a pseudo instruction and replace it with subreg based operation on real instructions, ridding the asm printers of the hack used to do this previously. In the process, update LowerSubregs to be careful about eliminating copies that have side affects. by Christopher Lamb · 17 years ago
  97. 1fab4a6 Recommitting parts of r48130. These do not appear to cause the observed failures. by Christopher Lamb · 17 years ago
  98. 447ff68 Change the model for FP Stack return to use fp operands on the by Chris Lattner · 17 years ago
  99. 4499e49 Revert 48125, 48126, and 48130 for now to unbreak some x86-64 tests. by Evan Cheng · 17 years ago
  100. 3feb017 Allow insert_subreg into implicit, target-specific values. by Christopher Lamb · 17 years ago