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gerrit-public.fairphone.software / fp2-dev / platform / external / llvm / 2a6411bbbdc6a23605fa206e07fc4f99a3d5dff2 / lib / Target / X86 / X86RegisterInfo.td
  1. 2a6411b Reduce code duplication on the TLS implementation. by Rafael Espindola · 15 years ago
  2. 599a6a8 Fix PR3701. 1. X86 target renamed eflags register to flags. This matches what llvm-gcc generates so codegen knows flags register is being clobbered by inline asm. 2. BURR scheduler should also check if inline asm nodes can clobber "live" physical registers. Previously it was only checking target nodes with implicit defs. by Evan Cheng · 15 years ago
  3. d3f1849 Reformat the allocation-order arrays to a more conventional style. by Dan Gohman · 16 years ago
  4. be362ab <rdar://problem/6351057> by Stuart Hastings · 16 years ago
  5. fb88f1f Remove unneeded stuff from GRAD register class. by Dale Johannesen · 16 years ago
  6. 330169f Extend InlineAsm::C_Register to allow multiple specific registers by Dale Johannesen · 16 years ago
  7. 9ed08f4 Change x86 register allocation ordering to match that of gcc. Otherwise some tools get confused by prologue generated by llvm. by Evan Cheng · 16 years ago
  8. ae270f6 ATT asm printer just print register AsmName's instead of calling tolower on each charater of Name. This speeds it up by 10%. by Evan Cheng · 16 years ago
  9. a68f901 Add v2f32 (MMX) type to X86. Support is primitive: by Dale Johannesen · 16 years ago
  10. 1fab4a6 Recommitting parts of r48130. These do not appear to cause the observed failures. by Christopher Lamb · 16 years ago
  11. 204496d In 32-bit mode, mark 64-bit GPR's as unallocatable. by Evan Cheng · 16 years ago
  12. 8e6da15 Eliminate the FP_GET_ST0/FP_SET_ST0 target-specific dag nodes, just lower to by Chris Lattner · 16 years ago
  13. 4499e49 Revert 48125, 48126, and 48130 for now to unbreak some x86-64 tests. by Evan Cheng · 16 years ago
  14. 3feb017 Allow insert_subreg into implicit, target-specific values. by Christopher Lamb · 16 years ago
  15. 8dc023f claim ST(x) registers are 80 bits, which is true. This doesn't affect by Chris Lattner · 16 years ago
  16. 6f0d024 Rename MRegisterInfo to TargetRegisterInfo. by Dan Gohman · 16 years ago
  17. 8eea339 Provide correct DWARF register numbering for debug information emission on x86-32/Darwin. by Anton Korobeynikov · 17 years ago
  18. 4ee451d Remove attribution from file headers, per discussion on llvmdev. by Chris Lattner · 17 years ago
  19. f191c80 Use TableGen to emit information for dwarf register numbers. by Anton Korobeynikov · 17 years ago
  20. 7a42f24 Revert previous rewrite per chris's comments. by Dale Johannesen · 17 years ago
  21. 3556bc1 Rewrite Dwarf number handling per review comments. by Dale Johannesen · 17 years ago
  22. 4542edc Complete conditionalization of Dwarf reg numbers. by Dale Johannesen · 17 years ago
  23. 48abc5c Corrected many typing errors. And removed 'nest' parameter handling by Arnold Schwaighofer · 17 years ago
  24. dcfa73f Set CCR (EFLAGS) copy cost to -1, i.e. extremely expensive to copy. by Evan Cheng · 17 years ago
  25. 3054dde Added status flags register: EFLAGS. by Evan Cheng · 17 years ago
  26. a3231ba Temporarily backing out this change until we know why some dejagnu tests are failing. by Evan Cheng · 17 years ago
  27. a333b41 GR16_ sub-register class should be GR8_, not GR8. That is, it should only be 8-bit registers in 32-bit mode. Ditto for GR32_. by Evan Cheng · 17 years ago
  28. 59a5873 Long double patch 4 of N: initial x87 implementation. by Dale Johannesen · 17 years ago
  29. f9b90ea Add register info needed to use subreg sets on X86. by Christopher Lamb · 17 years ago
  30. 849f214 Fix for PR 1505 (and 1489). Rewrite X87 register by Dale Johannesen · 17 years ago
  31. 038082d Emit correct DWARF reg # for RA (return address) register by Anton Korobeynikov · 17 years ago
  32. 6120433 Specify sub-register relations. e.g. RAX: [EAX], EAX: [AX], AX: [AL,AH]. by Evan Cheng · 17 years ago
  33. eebc8a1 Add support for the v1i64 type. This makes better code for this: by Bill Wendling · 17 years ago
  34. dc77540 hasFP() is now a virtual method of MRegisterInfo. by Evan Cheng · 18 years ago
  35. 25ab690 Committing X86-64 support. by Evan Cheng · 18 years ago
  36. 5ea64fd Constify some methods. Patch provided by Anton Vayvod, thanks! by Chris Lattner · 18 years ago
  37. e46e1a5 Make XMM, FP register dwarf register numbers consistent with gcc. by Evan Cheng · 18 years ago
  38. 6b59a36 Get darwin intel debugging up and running. by Jim Laskey · 18 years ago
  39. 069287d X86 integer register classes naming changes. Make them consistent with FP, vector classes. by Evan Cheng · 18 years ago
  40. 403be7e Fixing truncate. Previously we were emitting truncate from r16 to r8 as by Evan Cheng · 18 years ago
  41. 7481145 Typo's by Evan Cheng · 18 years ago
  42. 47622e3 Add dwarf register numbering to register data. by Jim Laskey · 18 years ago
  43. 5c791c8 Junk unused vector register classes. by Evan Cheng · 18 years ago
  44. 933be33 Added SSE2 128-bit integer packed types: V16I8, V8I16, V4I32, and V2I64. by Evan Cheng · 18 years ago
  45. aea20f5 Added x86 integer vector types: 64-bit packed byte integer (v16i8), 64-bit by Evan Cheng · 18 years ago
  46. 71fb9ad Remove the uses of STATUS flag register. Rely on node property SDNPInFlag, by Evan Cheng · 19 years ago
  47. 5bc4da4 Bye bye HACKTROCITY. by Evan Cheng · 19 years ago
  48. b077b84 * Added lowering hook for external weak global address. It inserts a load by Evan Cheng · 19 years ago
  49. bbc8ddb SSE2 floating point load / store patterns. SSE2 fp to int conversion patterns. by Evan Cheng · 19 years ago
  50. aed7c72 Added support for cmp, test, and conditional move instructions. by Evan Cheng · 19 years ago
  51. 6510b22 Support multiple ValueTypes per RegisterClass, needed for upcoming vector by Nate Begeman · 19 years ago
  52. 14e2cf6 Properly split f32 and f64 into separate register classes for scalar sse fp by Nate Begeman · 19 years ago
  53. ecbce61 Split RegisterClass 'Methods' into MethodProtos and MethodBodies by Chris Lattner · 19 years ago
  54. 03ba7b9 Put register classes into namespaces by Chris Lattner · 19 years ago
  55. f63be7d First round of support for doing scalar FP using the SSE2 ISA extension and by Nate Begeman · 19 years ago
  56. f1702ac Initial set of .td file changes necessary to get scalar fp in xmm registers by Nate Begeman · 19 years ago
  57. 0539313 Minor optimization to allocate R8 registers in a better order. by Chris Lattner · 20 years ago
  58. 45de191 Spill/restore X86 floating point stack registers with 64-bits of precision by Chris Lattner · 20 years ago
  59. 65cbfa0 The real x87 floating point registers should not be allocatable. They by Alkis Evlogimenos · 20 years ago
  60. a270019 Fit long lines into 80 cols via creative space elimination by Misha Brukman · 20 years ago
  61. b228657 Revamp the Register class, and allow the use of the RegisterGroup class to by Chris Lattner · 20 years ago
  62. 47d2f2b Nuke commented out stuff by Chris Lattner · 20 years ago
  63. ff0a6e6 Switch from bytes to bits for alignment for consistency by Chris Lattner · 20 years ago
  64. 068758e give FP stack registers names by Chris Lattner · 20 years ago
  65. 9c22aeb Improve allocation order: by Alkis Evlogimenos · 20 years ago
  66. 856ba76 Added LLVM copyright header. by John Criswell · 21 years ago
  67. bf2f8a9 Converted tabs to spaces. by Misha Brukman · 21 years ago
  68. 69666e5 This register is never used, disable it. by Chris Lattner · 21 years ago
  69. 6770aed Rename register classes to be upper case to make it obvious that they are X86 by Chris Lattner · 21 years ago
  70. c8f4587 transition to using let instead of set by Chris Lattner · 21 years ago
  71. 7af9a38 Specify custom name for registers to get the ()'s in the name. by Chris Lattner · 21 years ago
  72. 9eab316 The RegisterInfo class is obsolete by Chris Lattner · 21 years ago
  73. b76d6fc Initial checkin of X86 Register File description by Chris Lattner · 21 years ago