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gerrit-public.fairphone.software / fp2-dev / platform / external / llvm / 350afb16ecab216d5ea887b93112b24ba87ececb / lib / Target / ARM / ARMISelLowering.cpp
  1. 350afb1 revert so I can get the right PR# in the log message. by Jim Grosbach · 15 years ago
  2. 0bb9895 Since ARM emits inline jump tables as part of the ConstantIsland pass, by Jim Grosbach · 15 years ago
  3. 5423856 Add combiner patterns to more effectively utilize the BFI (bitfield insert) by Jim Grosbach · 15 years ago
  4. dd7d28a add BFI to getTargetNodeName() by Jim Grosbach · 15 years ago
  5. 15a2f2e Fix logic think-o by Jim Grosbach · 15 years ago
  6. 469bbdb Add basic support to code-gen the ARM/Thumb2 bit-field insert (BFI) instruction by Jim Grosbach · 15 years ago
  7. 60108e9 Split -enable-finite-only-fp-math to two options: by Evan Cheng · 15 years ago
  8. 7e3f0d2 Add support for NEON VMVN immediate instructions. by Bob Wilson · 15 years ago
  9. 9e82bf1 Add an ARM-specific DAG combining to avoid redundant VDUPLANE nodes. by Bob Wilson · 15 years ago
  10. cba270d Use a target-specific VMOVIMM DAG node instead of BUILD_VECTOR to represent by Bob Wilson · 15 years ago
  11. 218977b Extend the r107852 optimization which turns some fp compare to code sequence using only i32 operations. It now optimize some f64 compares when fp compare is exceptionally slow (e.g. cortex-a8). It also catches comparison against 0.0. by Evan Cheng · 15 years ago
  12. 6dce00c Move NEON "modified immediate" encode/decode into ARMAddressingModes.h to by Bob Wilson · 15 years ago
  13. c7a797b Remove some code that doesn't appear to do anything. All the ARM call by Bob Wilson · 15 years ago
  14. cbeeae2 Fix va_arg for doubles. With this patch VAARG nodes always contain the by Rafael Espindola · 15 years ago
  15. 5d115a0 Check for FiniteOnlyFPMath as well. by Evan Cheng · 15 years ago
  16. 4ff7ab6 r107852 is only safe with -enable-unsafe-fp-math to account for +0.0 == -0.0. by Evan Cheng · 15 years ago
  17. 515fe3a Optimize some vfp comparisons to integer ones. This patch implements the simplest case when the following conditions are met: by Evan Cheng · 15 years ago
  18. 7835f1f Changes to ARM tail calls, mostly cosmetic. by Dale Johannesen · 15 years ago
  19. c940365 Split the SDValue out of OutputArg so that SelectionDAG-independent by Dan Gohman · 15 years ago
  20. e97f968 Mark eh.sjlj.set/longjmp custom lowerings as Darwin-only since that's where by Jim Grosbach · 15 years ago
  21. c66e150b By default, the eh.sjlj.setjmp/longjmp intrinsics should just do nothing rather by Jim Grosbach · 15 years ago
  22. 0d881da Propagate debug loc. by Devang Patel · 15 years ago
  23. 14152b4 Reapply r107655 with fixes; insert the pseudo instruction into by Dan Gohman · 15 years ago
  24. 258c58c Revert r107655. by Dan Gohman · 15 years ago
  25. b81c771 Fix a bunch of custom-inserter functions to handle the case where by Dan Gohman · 15 years ago
  26. ed2ae13 Remove isSS argument from CreateFixedObject. Fixed objects cannot be spill slots so it's always false. by Evan Cheng · 15 years ago
  27. b5b5057 ARM function alignments were off by a power of two. svn 83242 changed by Bob Wilson · 15 years ago
  28. 90c64f4 Remove initialized but otherwise unused variables. by Duncan Sands · 15 years ago
  29. a2c6f45 Followup to r106770: actually generate SXTB and SXTH for sign-extensions. by Eli Friedman · 15 years ago
  30. f679939 It's now possible to run code placement pass for ARM. by Evan Cheng · 15 years ago
  31. 1315143 Change if-conversion block size limit checks to add some flexibility. by Evan Cheng · 15 years ago
  32. 1784d16 The hasMemory argument is irrelevant to how the argument by Dale Johannesen · 15 years ago
  33. 86fe66d Reduce indentation. by Bob Wilson · 15 years ago
  34. e39fdbe Do not do tail calls to external symbols. If the by Dale Johannesen · 15 years ago
  35. 5def57a When using libcall expansions for the atomic intrinsics, the explicit by Jim Grosbach · 15 years ago
  36. 56a1a69 sign_extend_inreg needs to be expanded for pre-v6 Thumb as well as ARM. by Bob Wilson · 15 years ago
  37. dc076da Fix error message to match function name. by Bob Wilson · 15 years ago
  38. 0110ac6 Disable sibcall optimization for Thumb1 for now since Thumb1RegisterInfo::emitEpilogue is not expecting them. by Evan Cheng · 15 years ago
  39. ef6eb9c back-end libcall handling for ATOMIC_SWAP (__sync_lock_test_and_set) by Jim Grosbach · 15 years ago
  40. 68741be Enable Expand handling of atomics for subtargets that can't do them inline. by Jim Grosbach · 15 years ago
  41. c66cdf7 Enable tail calls on ARM by default, with some basic tests. by Dale Johannesen · 15 years ago
  42. df50d7e Last round of changes for ARM tail calls. Not turning them on yet. by Dale Johannesen · 15 years ago
  43. 0d8ba33 Treat the ARM inline asm {cc} constraint as a physreg (%CPSR), just like X86 by Jakob Stoklund Olesen · 15 years ago
  44. 7072cf6 Thumb1 and any pre-v6 ARM target should use the libcall expansion of by Jim Grosbach · 15 years ago
  45. c73993b simplify code a bit and add a more explanatory assert for cases that by Jim Grosbach · 15 years ago
  46. 7616b64 format and 80-column cleanup by Jim Grosbach · 15 years ago
  47. 07f6e80 Remove the hidden "neon-reg-sequence" option. The reg sequences are working by Bob Wilson · 15 years ago
  48. 46df4eb Make post-ra scheduling, anti-dep breaking, and register scavenger (conservatively) aware of predicated instructions. This enables ARM to move if-conversion before post-ra scheduler. by Evan Cheng · 15 years ago
  49. 6470a11 Next round of tail call changes. Register used in a tail by Dale Johannesen · 15 years ago
  50. 827b210 Add basic support for NEON modified immediates besides VMOV. by Bob Wilson · 15 years ago
  51. d3c4284 Rename functions referring to VMOV immediates to refer to NEON "modified by Bob Wilson · 15 years ago
  52. 1114f56 Add a missing bitcast. This code used to only handle conversions between by Bob Wilson · 15 years ago
  53. 1a913ed Add instruction encoding for the Neon VMOV immediate instruction. This changes by Bob Wilson · 15 years ago
  54. 53dd245 Further changes for Neon vector shuffles: by Bob Wilson · 15 years ago
  55. cf296fa Improvements to tail call code. No functional effect by Dale Johannesen · 15 years ago
  56. 8fa8e7f More thoroughly disable tails calls by default. by Dale Johannesen · 15 years ago
  57. 40cbe7d For NEON vectors with 32- or 64-bit elements, select BUILD_VECTORs and by Bob Wilson · 15 years ago
  58. 51e28e6 Early implementation of tail call for ARM. by Dale Johannesen · 15 years ago
  59. 18f30e6 Clean up 80 column violations. No functional change. by Jim Grosbach · 15 years ago
  60. c10f543 Schedule high latency instructions for latency reduction even if they are not vfp / NEON instructions. by Evan Cheng · 15 years ago
  61. 0798edd Update the saved stack pointer in the sjlj function context following either by Jim Grosbach · 15 years ago
  62. a658502 back out 104862/104869. Can reuse stacksave after all. Very cool. by Jim Grosbach · 15 years ago
  63. ad9aaf0 add ISD::STACKADDR to get the current stack pointer. Will be used by sjlj EH by Jim Grosbach · 15 years ago
  64. 23ff7cf Adjust eh.sjlj.setjmp to properly have a chain and to have an opcode entry in by Jim Grosbach · 15 years ago
  65. ab3912e Clean up indentation. by Bob Wilson · 15 years ago
  66. c7cf10c LR is in GPR, not tGPR even in Thumb1 mode. by Evan Cheng · 15 years ago
  67. 069e434 VDUP doesn't support vectors with 64-bit elements. by Bob Wilson · 15 years ago
  68. 2457f2c Implement @llvm.returnaddress. rdar://8015977. by Evan Cheng · 15 years ago
  69. 5eb1951 Implement eh.sjlj.longjmp for ARM. Clean up the intrinsic a bit. by Jim Grosbach · 15 years ago
  70. be751cf Recognize more BUILD_VECTORs and VECTOR_SHUFFLEs that can be implemented by by Bob Wilson · 15 years ago
  71. f7d87ee Change ARM scheduling default to list-hybrid if the target supports floating point instructions (and is not using soft float). by Evan Cheng · 15 years ago
  72. 1cc3984 Allow targets more controls on what nodes are scheduled by reg pressure, what for latency in hybrid mode. by Evan Cheng · 15 years ago
  73. 63b8845 Handle Neon v2f64 and v2i64 vector shuffles as register copies. by Bob Wilson · 15 years ago
  74. 211ffa1 Code refactoring: pull SchedPreference enum from TargetLowering.h to TargetMachine.h and put it in its own namespace. by Evan Cheng · 15 years ago
  75. 28dad2a Sink dag combine's post index load / store code that swap base ptr and index into the target hook. Only the target knows whether the swap is safe. In Thumb2 mode, the offset must be an immediate. rdar://7998649 by Evan Cheng · 15 years ago
  76. 4878b84 Generalize the ARM DAG combiner of mul with constants to all power-of-two cases. by Anton Korobeynikov · 15 years ago
  77. a9790d7 Some cheap DAG combine goodness for multiplication with a particular constant. by Anton Korobeynikov · 15 years ago
  78. 4782b1e v4i64 and v8i64 are only synthesizable when NEON is available. by Evan Cheng · 15 years ago
  79. 06b666c Allow TargetLowering::getRegClassFor() to be called on illegal types. Also by Evan Cheng · 15 years ago
  80. 22c687b Added a QQQQ register file to model 4-consecutive Q registers. by Evan Cheng · 15 years ago
  81. ff7a562 Implement a bunch more TargetSelectionDAGInfo infrastructure. by Dan Gohman · 15 years ago
  82. fb3611d Select @llvm.trap to the special B with 1111 condition (i.e. trap) instruction. by Evan Cheng · 15 years ago
  83. 603afbf Model vld2 / vst2 with reg_sequence. by Evan Cheng · 15 years ago
  84. 4b77f6a Clean up the conditional for handling of sign_extend_inreg based on by Jim Grosbach · 15 years ago
  85. 2940213 Cleanup of ARMv7M support. Move hardware divide and Thumb2 extract/pack by Jim Grosbach · 15 years ago
  86. b1dc393 Add initial support for ARMv7M subtarget and cortex-m3 cpu. Patch by by Jim Grosbach · 15 years ago
  87. de8aa4e Model CONCAT_VECTORS of two 64-bit values as a REG_SEQUENCE. by Evan Cheng · 15 years ago
  88. af1d8ca Get rid of the EdgeMapping map. Instead, just check for BasicBlock by Dan Gohman · 15 years ago
  89. d858e90 Use const qualifiers with TargetLowering. This eliminates several by Dan Gohman · 15 years ago
  90. 1e93df6 Move per-function state out of TargetLowering subclasses and into by Dan Gohman · 15 years ago
  91. 9f3f061 Revise my previous change to ExpandBIT_CONVERT. I hadn't realized that this by Bob Wilson · 15 years ago
  92. 3a1588a Use default lowering of DYNAMIC_STACKALLOC. As far as I can tell, ARM isle is doing the right thing and codegen looks correct for both Thumb and Thumb2. by Evan Cheng · 15 years ago
  93. 0dbdca5 Fix build. by Anders Carlsson · 15 years ago
  94. 46510a7 Add const qualifiers to CodeGen's use of LLVM IR constructs. by Dan Gohman · 15 years ago
  95. e7b5252 Add -arm-long-calls option to force calls to be indirect. This makes the by Jim Grosbach · 15 years ago
  96. 164cd8b Don't custom lower bit converts to ARM VMOVDRRD or VMOVDRR when the operand by Bob Wilson · 15 years ago
  97. 6a234f0 Handle a v2f64 formal parameter that is split between registers and memory by Bob Wilson · 15 years ago
  98. d0910c4 Expand SELECT and SELECT_CC for NEON vector types. Radar 7770501. by Bob Wilson · 15 years ago
  99. 20adc9d Reapply address space patch after fixing an issue in MemCopyOptimizer. by Mon P Wang · 15 years ago
  100. e754d3f Revert r100191 since it breaks objc in clang by Mon P Wang · 15 years ago