- 36fa532 Fix another problem with ARM constant pools. Radar 7303551. by Bob Wilson · 16 years ago
- b3642dc Fix instruction encoding bits for NEON VPADAL. Patch by Johnny Chen. by Bob Wilson · 16 years ago
- 681a2ad Remove unused variables to fix build warning. by Bob Wilson · 16 years ago
- b9d319b Inst{11-8} for vshl should be 0b0101, not 0b1111. Refs: A7-17 & A8-750. by Jim Grosbach · 16 years ago
- 8e86b51 Set instruction encoding bits 4 and 7 for ARM register-register and by Bob Wilson · 16 years ago
- 24f995d Refactor code to select NEON VST intrinsics. by Bob Wilson · 16 years ago
- 3e36f13 Refactor code to select NEON VLD intrinsics. by Bob Wilson · 16 years ago
- 9649344 More refactoring. NEON vst lane intrinsics can share almost all the code for by Bob Wilson · 16 years ago
- a7c397c Refactor code for selecting NEON load lane intrinsics. by Bob Wilson · 16 years ago
- 079469f Correct comment about ARM immediates using '#' not '$' and TODO for modifiers. by Kevin Enderby · 16 years ago
- e72142a More Neon clean-up: avoid the need for custom-lowering vld/st-lane intrinsics by Bob Wilson · 16 years ago
- cfe0724 More bits of the ARM target assembler for llvm-mc to parse immediates. by Kevin Enderby · 16 years ago
- 73d64a6 NEON VLD/VST are now fully implemented. For operations that expand to by Bob Wilson · 16 years ago
- 765cc0b Revise ARM inline assembly memory operands to require the memory address to by Bob Wilson · 16 years ago
- 4e1ed88 Fix method name in comment, per Bob Wilson. by Sandeep Patel · 16 years ago
- 47eedaa Add ARMv6T2 SBFX/UBFX instructions. Approved by Anton Korobeynikov. by Sandeep Patel · 16 years ago
- 5361cd2 Add some ARM instruction encoding bits. Patch by Johnny Chen. by Bob Wilson · 16 years ago
- 4796ba2 Fix regression introduced by r83894. by Bob Wilson · 16 years ago
- a7fcb9b Fix a tab. Thanks to Johnny Chen for pointing it out. by Bob Wilson · 16 years ago
- 6bd266e Fix two warnings about unused variables that are only used in assert() calls. by Kevin Enderby · 16 years ago
- af4b735 Delete a comment that makes no sense to me. The statement that moving a CPE by Bob Wilson · 16 years ago
- 9d36962 Fix a problem in the code where ARMAsmParser::ParseShift() second argument by Kevin Enderby · 16 years ago
- 757652c Change CreateNewWater method to return NewMBB by reference. by Bob Wilson · 16 years ago
- f98032e Last week, ARMConstantIslandPass was failing to converge for the by Bob Wilson · 16 years ago
- 32c50e8 Another minor clean-up. by Bob Wilson · 16 years ago
- d637c1a Remove redundant parameter. by Bob Wilson · 16 years ago
- 3b75735 Use early exit to reduce indentation. by Bob Wilson · 16 years ago
- 9d16f2c Change to return a value by reference. by Bob Wilson · 16 years ago
- 034de5f Add a typedef for an iterator. by Bob Wilson · 16 years ago
- 59ac571 Mark the LDR instruction with isReMaterializable, as it is rematerializable by Dan Gohman · 16 years ago
- d7894f1 Added another bit of the ARM target assembler to llvm-mc to parse register by Kevin Enderby · 16 years ago
- 5631139 Add codegen support for NEON vst4lane intrinsics with 128-bit vectors. by Bob Wilson · 16 years ago
- 8cdb269 Add codegen support for NEON vst3lane intrinsics with 128-bit vectors. by Bob Wilson · 16 years ago
- c5c6edb Add codegen support for NEON vst2lane intrinsics with 128-bit vectors. by Bob Wilson · 16 years ago
- 62e053e Add codegen support for NEON vld4lane intrinsics with 128-bit vectors. by Bob Wilson · 16 years ago
- 0bf7d99 Add codegen support for NEON vld3lane intrinsics with 128-bit vectors. by Bob Wilson · 16 years ago
- 632606c Use lower16 / upper16 imm modifiers to asmprint 32-bit imms splitted via movt/movw pair. by Anton Korobeynikov · 16 years ago
- 30aea9d Add codegen support for NEON vld2lane intrinsics with 128-bit vectors. by Bob Wilson · 16 years ago
- cd7e327 Clean up some unnecessary initializations. by Bob Wilson · 16 years ago
- af4a891 Clean up a comment (indentation was wrong). by Bob Wilson · 16 years ago
- deb3141 Add codegen support for NEON vst4 intrinsics with <1 x i64> vectors. by Bob Wilson · 16 years ago
- 1f30dcb Cleanup up unused R3LiveIn tracking. by Jim Grosbach · 16 years ago
- 65c58da Re-enable register scavenging in Thumb1 by default. by Jim Grosbach · 16 years ago
- 5adf60c Add codegen support for NEON vst3 intrinsics with <1 x i64> vectors. by Bob Wilson · 16 years ago
- 24e04c5 Add codegen support for NEON vst2 intrinsics with <1 x i64> vectors. by Bob Wilson · 16 years ago
- 0ea38bb Add codegen support for NEON vld4 intrinsics with <1 x i64> vectors. by Bob Wilson · 16 years ago
- c67160c Add codegen support for NEON vld3 intrinsics with <1 x i64> vectors. by Bob Wilson · 16 years ago
- a428808 Add codegen support for NEON vld2 intrinsics with <1 x i64> vectors. by Bob Wilson · 16 years ago
- 9f3a559 reverting thumb1 scavenging default due to test failure while I figure out what's up. by Jim Grosbach · 16 years ago
- ec1434d Enable thumb1 register scavenging by default. by Jim Grosbach · 16 years ago
- b07c171 Add some instruction encoding bits for NEON load/store instructions. by Bob Wilson · 16 years ago
- 63c9063 Add codegen support for NEON vst4 intrinsics with 128-bit vectors. by Bob Wilson · 16 years ago
- 66a7063 Add codegen support for NEON vst3 intrinsics with 128-bit vectors. by Bob Wilson · 16 years ago
- d285575 Add codegen support for NEON vst2 intrinsics with 128-bit vectors. by Bob Wilson · 16 years ago
- 7708c22 Add codegen support for NEON vld4 intrinsics with 128-bit vectors. by Bob Wilson · 16 years ago
- 99e6d4e Add another bit of the ARM target assembler to llvm-mc to parse registers by Kevin Enderby · 16 years ago
- ff8952e Add codegen support for NEON vld3 intrinsics with 128-bit vectors. by Bob Wilson · 16 years ago
- 228c08b Rearrange code for selecting vld2 intrinsics. No functionality change. by Bob Wilson · 16 years ago
- b58f498 Add register-reuse to frame-index register scavenging. When a target uses by Jim Grosbach · 16 years ago
- 249fb33 Add PseudoSourceValues for constpool stuff on ELF (Darwin should use something similar) by Anton Korobeynikov · 16 years ago
- a7ba3a8 Added bits of the ARM target assembler to llvm-mc to parse some load instruction by Kevin Enderby · 16 years ago
- 3bf12ab Add codegen support for NEON vld2 operations on quad registers. by Bob Wilson · 16 years ago
- 349d82d Use copyRegToReg hook to copy registers. by Bob Wilson · 16 years ago
- a3e8bf8 Fix a comment typo. Patch by Johnny Chen. by Bob Wilson · 16 years ago
- e3cc3f3 Instead of printing unnecessary basic block labels as labels in by Dan Gohman · 16 years ago
- af0e272 Update processDebugLoc() so that it can be used to process debug info before and after printing an instruction. by Devang Patel · 16 years ago
- 540b05d In Thumb1, the register scavenger is not always able to use an emergency by Jim Grosbach · 16 years ago
- cf0fe8d strength reduce a ton of type equality tests to check the typeid (Through by Chris Lattner · 16 years ago
- 916ac5b Add a comment to describe letters used in multiclass name suffixes. by Bob Wilson · 16 years ago
- 8f07b9e Fix encoding problem for VMLS instruction. by Bob Wilson · 16 years ago
- 048e36f getFunctionAlignment should return log2 alignment. by Evan Cheng · 16 years ago
- 8925979 Forgot about ARM::tPUSH. It also has a new writeback operand. by Evan Cheng · 16 years ago
- 62a1b5d Move load / store multiple before post-alloc scheduling. by Evan Cheng · 16 years ago
- 9843a93 Remove neonfp attribute and instead set default based on CPU string. Add -arm-use-neon-fp to override the default. by David Goodwin · 16 years ago
- 471850a Restore the -post-RA-scheduler flag as an override for the target specification. Remove -mattr for setting PostRAScheduler enable and instead use CPU string. by David Goodwin · 16 years ago
- 10469f8 ARM::tPOP and tPOP_RET each has an extra writeback operand now. by Evan Cheng · 16 years ago
- 0d92f5f Add hasExtraSrcRegAllocReq and hasExtraDefRegAllocReq flags to ld / st multiple, by Evan Cheng · 16 years ago
- 7c043d7 Update ARM JIT emitter to account for ld/st multiple changes. by Evan Cheng · 16 years ago
- d20d658 Change ld/st multiples to explicitly model the writeback to base register. This fixes most of the -ldstopti-before-sched2 regressions. by Evan Cheng · 16 years ago
- b0fdedb Use MachineInstr as an processDebugLoc() argument. by Devang Patel · 16 years ago
- 29e0669 Use OutStreamer.SwitchSection instead of writing out textual section directives. by Bob Wilson · 16 years ago
- 812209a Add a new virtual EmitStartOfAsmFile method to the AsmPrinter and use this by Bob Wilson · 16 years ago
- b6e4742 The AsmPrinter base class contains a DwarfWriter member, so there's no need by Bob Wilson · 16 years ago
- 460c482 Clarify comment phrasing. by Jim Grosbach · 16 years ago
- 792e1f6 Add a option which would move ld/st multiple pass before post-alloc scheduling. by Evan Cheng · 16 years ago
- d1a5ca6 When checking whether we need to reserve a register for the scavenger, by Jim Grosbach · 16 years ago
- c732adf Add "isBarrier = 1" to return instructions. by Jim Grosbach · 16 years ago
- 0fb3468 For Darwin, emit all the text section directives together before the dwarf by Bob Wilson · 16 years ago
- 0dad89f Remove -post-RA-schedule flag and add a TargetSubtarget method to enable post-register-allocation scheduling. By default it is off. For ARM, enable/disable with -mattr=+/-postrasched. Enable by default for cortex-a8. by David Goodwin · 16 years ago
- 17487ba minor cleanup and add clarifying comment by Jim Grosbach · 16 years ago
- fa1be5d Fix PR4687. Pre ARMv5te does not support ldrd / strd. Patch by John Tytgat. by Evan Cheng · 16 years ago
- ec9eef4 Adjust processFunctionBeforeCalleeSavedScan() to correctly reserve a stack by Jim Grosbach · 16 years ago
- fd84711 Fix Thumb2 IT block pass bug. t2MOVi32imm may not be the start of a IT block. by Evan Cheng · 16 years ago
- 26207e5 Introduce the TargetInstrInfo::KILL machine instruction and get rid of the by Jakob Stoklund Olesen · 16 years ago
- 522ce97 Pass the optimization level when constructing the ARM instruction selector. by Bob Wilson · 16 years ago
- 5adb66a Make ARM and Thumb2 32-bit immediate materialization into a single 32-bit pseudo by Evan Cheng · 16 years ago
- b0d8d78 Fix thinko in my recent movt commit: it's not safe to remat movt, since it has input reg argument. by Anton Korobeynikov · 16 years ago
- 6a2fa32 Use movt/movw pair to materialize 32 bit constants on ARMv6T2+. by Anton Korobeynikov · 16 years ago
- e298ab2 Enable pre-regalloc load / store multiple pass for Thumb2. by Evan Cheng · 16 years ago
- 72c158f Really remove this option. by Evan Cheng · 16 years ago