Gitiles
Code Review Sign In
gerrit-public.fairphone.software / fp2-dev / platform / external / llvm / 3aef70314b053a1df4f85ca4a6f3890d06ebbdd6 / lib / Target / X86
  1. 3aef703 Update LLVM for merge to r171905. by Stephen Hines · 12 years ago
  2. 059800f Merge remote-tracking branch 'upstream/master' into merge-llvm by Stephen Hines · 12 years ago
  3. c7b902e Pad Short Functions for Intel Atom by Preston Gurd · 12 years ago
  4. 251040b Renamed MCInstFragment to MCRelaxableFragment and added some comments. by Eli Bendersky · 12 years ago
  5. 3ebe59c Change SMRange to be half-open (exclusive end) instead of closed (inclusive) by Jordan Rose · 12 years ago
  6. c12979a Remove # from the beginning and end of def names. by Craig Topper · 12 years ago
  7. df3bf55 Remove unnecessary # tokens at the beginning and end of defm names. by Craig Topper · 12 years ago
  8. bb00800 Fix the enumerator names for ShuffleKind to match tho coding standards, by Chandler Carruth · 12 years ago
  9. d1b8ef9 Make the popcnt support enums and methods have more clear names and by Chandler Carruth · 12 years ago
  10. be04929 Move TargetTransformInfo to live under the Analysis library. This no by Chandler Carruth · 12 years ago
  11. aeef83c Switch TargetTransformInfo from an immutable analysis pass that requires by Chandler Carruth · 12 years ago
  12. f564a93 Fix suffix handling for parsing and printing of cvtsi2ss, cvtsi2sd, cvtss2si, cvttss2si, cvtsd2si, and cvttsd2si to match gas behavior. by Craig Topper · 12 years ago
  13. 700843e Fix for PR14739. It's not safe to fold a load into a call across a store. Thanks to Nick Lewycky for the initial patch. by Evan Cheng · 12 years ago
  14. 835e7bc Recommit r171461 which was incorrectly reverted. Mark DIV/IDIV instructions hasSideEffects=1 because they can trap when dividing by 0. This is needed to keep early if conversion from moving them across basic blocks. by Craig Topper · 12 years ago
  15. 5d1f5c1 Revert revision 171524. Original message: by Nadav Rotem · 12 years ago
  16. 18d0f12 Move 'break' to the right place to prevent fallthru. There is no test-case by Jakub Staszak · 12 years ago
  17. dd30b47 The current Intel Atom microarchitecture has a feature whereby when a function by Preston Gurd · 12 years ago
  18. e503319 LoopVectorizer: by Nadav Rotem · 12 years ago
  19. e12bf18 by Nadav Rotem · 12 years ago
  20. ab70320 Simplified TRUNCATE operation that comes after SETCC. It is possible since SETCC result is 0 or -1. by Elena Demikhovsky · 12 years ago
  21. e33a8b8 Revert "Mark DIV/IDIV instructions hasSideEffects=1 because they can trap when dividing by 0. This is needed to keep early if conversion from moving them across basic blocks." by Michael Gottesman · 12 years ago
  22. 56bc0ab Mark DIV/IDIV instructions hasSideEffects=1 because they can trap when dividing by 0. This is needed to keep early if conversion from moving them across basic blocks. by Craig Topper · 12 years ago
  23. 82860f6 Add a subtype parameter to VTTI::getShuffleCost by Hal Finkel · 12 years ago
  24. 5bf3a28 Adds missing aliases for fcom and fcomp instructions without arguments. by Kevin Enderby · 12 years ago
  25. e3b2489 AVX: Fix a bug in WidenMaskArithmetic. by Nadav Rotem · 12 years ago
  26. 0b8c9a8 Move all of the header files which are involved in modelling the LLVM IR by Chandler Carruth · 12 years ago
  27. 3af9323 Merge SSE and AVX instruction definitions for scalar forms of SQRT, RSQRT, and RCP. by Craig Topper · 12 years ago
  28. 3cca7df Merge SSE and AVX instruction definitions for PSHUFD/PSHUFHW/PSHUFLW. by Craig Topper · 12 years ago
  29. 9478673 Revert 171351. It broke MC/X86/x86-32-avx.s. by Rafael Espindola · 12 years ago
  30. b511048 Merge SSE and AVX instruction definitions for scalar forms of SQRT, RSQRT, and RCP. by Craig Topper · 12 years ago
  31. 117e4d2 Remove unused argument from a multiclass. by Craig Topper · 12 years ago
  32. 76f94fd Merge intrinsic instruction definitions for SSE and AVX versions of RCPPS and RSQRTPS. by Craig Topper · 12 years ago
  33. 42ab0d7 Remove 2 unused multiclasses. by Craig Topper · 12 years ago
  34. 5284f97 Merge AVX/SSE instruction definitions for SQRTPS/PD, RSQRTPS, RCPPS. No funcitonal change intended. by Craig Topper · 12 years ago
  35. dd9ccdb Use packed instead of scalar itineraries for SSE1/2 SQRTPS/PD, RCPPS, and RSQRTPS. VEX-encoded forms already use packed. by Craig Topper · 12 years ago
  36. 94e94b3 Use the predicate methods off of AttributeSet instead of Attribute. by Bill Wendling · 12 years ago
  37. 8b62abd Remove the Function::getRetAttributes method in favor of using the AttributeSet accessor method. by Bill Wendling · 12 years ago
  38. 831737d Remove the Function::getFnAttributes method in favor of using the AttributeSet by Bill Wendling · 12 years ago
  39. 22d8f0d Remove intrinsic specific instructions for (V)SQRTPS/PD. Instead lower to target-independent ISD nodes and use the existing patterns for those. by Craig Topper · 12 years ago
  40. 6f57f39 Merge similar functionality using a nested switch. by Craig Topper · 12 years ago
  41. 6d183e4 Remove intrinsic specific instructions for SSE/SSE2/AVX floating point max/min instructions. Lower them to target specific nodes and use those patterns instead. This also allows them to be commuted if UnsafeFPMath is enabled. by Craig Topper · 12 years ago
  42. c20323a Simplify code, no functionality change. by Jakub Staszak · 12 years ago
  43. ae34b42 CostModel: initial checkin for code that estimates the cost of special shuffles. by Nadav Rotem · 12 years ago
  44. 40ef8b7 wrap 80-col lines. by Nadav Rotem · 12 years ago
  45. 0509db2 AVX: Move the ZEXT/ANYEXT DAGCo optimizations to the lowering of these optimizations. The old test cases still cover all of these lowering/optimizations. The single change that we have is that now anyext does not need to zero a register, because it does not use the exact code path as the zero_extend. by Nadav Rotem · 12 years ago
  46. 587fb1d Reverse the 'if' condition and reduce the indentation. by Nadav Rotem · 12 years ago
  47. cccccab Merge basic_sse12_fp_binop_p_int and basic_sse12_fp_binop_p_y_int multiclasses. by Craig Topper · 12 years ago
  48. 1a330af AVX/AVX2: Move the SEXT lowering code from a target specific DAGco to a lowering function. by Nadav Rotem · 12 years ago
  49. d5fc507 Merge basic_sse12_fp_binop_p and basic_sse12_fp_binop_p_y multiclasses. by Craig Topper · 12 years ago
  50. d6fb53a On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized by Nadav Rotem · 12 years ago
  51. 3c22a44 AVX/AVX2: Move the code that lowers vector-trunc from a DAGCo-hook to custom lowering hook. by Nadav Rotem · 12 years ago
  52. 068aec5 Add hasSideEffects=0 to some forms of ROUND, RCP, and RSQRT. by Craig Topper · 12 years ago
  53. d0f28c0 Move single letter 'P' prefix out of multiclass now that tablegen allows defm to start with #NAME. This makes instruction names more searchable again. by Craig Topper · 12 years ago
  54. 87073aa Add hasSideEffects=0 to some shift and rotate instructions. None of which are currently used by code generation. by Craig Topper · 12 years ago
  55. 766cbae Mark the divide instructions as hasSideEffects=0. by Craig Topper · 12 years ago
  56. 0b9c5e2 Add hasSideEffects=0 to CMP*rr_REV. by Craig Topper · 12 years ago
  57. 5e6a86c Add mayLoad, mayStore, and hasSideEffects tags to BT/BTS/BTR/BTC instructions. Shouldn't change any functionality since they don't have patterns to select them. by Craig Topper · 12 years ago
  58. e9fd6ad Fix operands and encoding form for ARPL instruction. Register form had and reversed. Memory form writes memory, but was marked as MRMSrcMem. by Craig Topper · 12 years ago
  59. ee5b63c Add hasSideEffects=0 to some atomic instructions. by Craig Topper · 12 years ago
  60. b87a5b3 Mark the AL/AX/EAX forms of the basic arithmetic operations has never having side effects. by Craig Topper · 12 years ago
  61. 37cb839 Mark all the _REV instructions as not having side effects. They aren't really emitted by the backend, but it reduces the number of instructions in the output files with unmodelled side effects to make auditing easier. by Craig Topper · 12 years ago
  62. a85cbfe Remove a special conditional setting of neverHasSideEffects if the instruction didn't have a pattern. This was leftover from when tablegen used to complain if things were already inferred from patterns. by Craig Topper · 12 years ago
  63. 0a5ead9 Merge still more SSE/AVX instruction definitions. by Craig Topper · 12 years ago
  64. 07555fc Merge more SSE/AVX instruction definitions. by Craig Topper · 12 years ago
  65. 755841d Fix 80 column violation. by Craig Topper · 12 years ago
  66. 6f9d44e Fix class name in comment. by Craig Topper · 12 years ago
  67. 219bc2d Merge SSE/AVX PCMPEQ/PCMPGT instruction definitions. by Craig Topper · 12 years ago
  68. 02082ef Remove 'v' from mnemonic to fix asm matching failures. by Craig Topper · 12 years ago
  69. 3cdc382 Use an additional multiclass to merge the 128/256-bit SSE/AVX instruction definitions for a bunch of SSE2 integer arithmetic instructions. by Craig Topper · 12 years ago
  70. a05f7cb Reformat the docs. by Nadav Rotem · 12 years ago
  71. 09a326d Use an additional multiclass to merge the 128/256-bit SSE/AVX instruction definitions for PAND/POR/PXOR/PANDN by Craig Topper · 12 years ago
  72. 1fe132a Merge an AVX/SSE 256-bit and 128-bit multiclass. by Craig Topper · 12 years ago
  73. b5c590a Mark VANDNPD/VANDNPDS as not commutable. by Craig Topper · 12 years ago
  74. 174a3d3 Remove alignment from a bunch more VEX encoded operations in the folding tables. by Craig Topper · 12 years ago
  75. d83a73a Remove alignment from folding table for VMOVUPD as an unaligned instruction it shouldn't require alignment... by Craig Topper · 12 years ago
  76. 1ac0046 Remove alignment requirements from (V)EXTRACTPS. This instruction does 32-bit stores which aren't required to be aligned on SSE or AVX. by Craig Topper · 12 years ago
  77. 0f77910 Remove alignment requirement from VCVTSS2SD in folding tables. Reverting r171049. This instruction doesn't require alignment. by Craig Topper · 12 years ago
  78. 99f7806 X86: Shave off one shuffle from the pcmpeqq sequence for SSE2 by making use of and commutativity. by Benjamin Kramer · 12 years ago
  79. 382ed78 X86: Custom lower <2 x i64> eq and ne when SSE41 is not available. by Benjamin Kramer · 12 years ago
  80. a4c8a32 VCVTSS2SD requires a strict alignment. Thanks Elena. by Nadav Rotem · 12 years ago
  81. 71f30bf Quiet gcc's -Wparenthesis warning. No functionality change. by Nick Lewycky · 12 years ago
  82. ace0c2f Some x86 instructions can load/store one of the operands to memory. On SSE, this memory needs to be aligned. by Nadav Rotem · 12 years ago
  83. 40b04a4 whitespace by Nadav Rotem · 12 years ago
  84. 677689c Rename a function. by Nadav Rotem · 12 years ago
  85. d54fed2 Loop Vectorizer: Update the cost model of scatter/gather operations and make by Nadav Rotem · 12 years ago
  86. 2f8a6cd X86: Turn mul of <4 x i32> into pmuludq when no SSE4.1 is available. by Benjamin Kramer · 12 years ago
  87. 1734791 X86: Emit vector sext as shuffle + sra if vpmovsx is not available. by Benjamin Kramer · 12 years ago
  88. d0696ef In some cases, due to scheduling constraints we copy the EFLAGS. by Nadav Rotem · 12 years ago
  89. 2556c6b X86: Match pmin/pmax as a target specific dag combine. This occurs during vectorization. by Benjamin Kramer · 12 years ago
  90. 739c7a8 X86: Match the SSE/AVX min/max vector ops using a custom node instead of intrinsics by Benjamin Kramer · 12 years ago
  91. 042a9a2 Add a missing "virtual" keyword. by Nadav Rotem · 12 years ago
  92. f5637c3 Improve the X86 cost model for loads and stores. by Nadav Rotem · 12 years ago
  93. be06aac Add an MF argument to MI::copyImplicitOps(). by Jakob Stoklund Olesen · 12 years ago
  94. 6af228a Remove MCTargetAsmLexer and its derived classes now that edis, by Roman Divacky · 12 years ago
  95. ba836a2 Fix use-before-construction of X86TargetLowering. by Richard Smith · 12 years ago
  96. fbf3b4a MC: Add MCInstrDesc::mayAffectControlFlow() method. by Jim Grosbach · 12 years ago
  97. 37a942c Remove the explicit MachineInstrBuilder(MI) constructor. by Jakob Stoklund Olesen · 12 years ago
  98. 759e3fa Remove edis - the enhanced disassembler. Fixes PR14654. by Roman Divacky · 12 years ago
  99. 6da2e22 Transform (x&C)>V into (x&C)!=0 where possible by Paul Redmond · 12 years ago
  100. e5c6591 Change TargetLowering::getTypeForExtArgOrReturn to take and return by Patrik Hagglund · 12 years ago