1. 3bc8a76 Implement PPC64 relocations types by Chris Lattner · 19 years ago
  2. 3d6721a An overaggressive #ifdef allows a function to fall off the bottom of the by Chris Lattner · 19 years ago
  3. 6d34657 Add information preventing several register class constraints from working. by Chris Lattner · 19 years ago
  4. be6a039 The PPC64 JIT needs register numbers to encode instructions. by Chris Lattner · 19 years ago
  5. f7eb5d0 Emit inc / dec of registers as one byte instruction. by Evan Cheng · 19 years ago
  6. 16d42c6 It was pointed out that DEBUG() is only available with -debug. by Jim Laskey · 19 years ago
  7. e37fe9b Ensure that dump calls that are associated with asserts are removed from by Jim Laskey · 19 years ago
  8. a4e6435 add the memri memory operand by Rafael Espindola · 19 years ago
  9. f4dff84 Implement the inline asm 'A' constraint. This implements PR825 and by Chris Lattner · 19 years ago
  10. 804e067 In 64-bit mode, 64-bit GPRs are callee saved, not 32-bit ones. by Chris Lattner · 19 years ago
  11. 20adf47 New entry. by Evan Cheng · 19 years ago
  12. 1e60c09 Fixed stack objects do not specify alignments, but their offsets are known. by Evan Cheng · 19 years ago
  13. d998938 Implement Regression/CodeGen/PowerPC/bswap-load-store.ll by folding bswaps by Chris Lattner · 19 years ago
  14. 5c5f4ca Mark internal function static by Chris Lattner · 19 years ago
  15. aefe142 create the raddr addressing mode that matches any register and the frame index by Rafael Espindola · 19 years ago
  16. 206ee9d X86 target specific DAG combine: turn build_vector (load x), (load x+4), by Evan Cheng · 19 years ago
  17. 90ac1c0 Undisable ppc64 jit by Chris Lattner · 19 years ago
  18. 152ed05 Added option -code-model to set code model (only used in 64-bit) mode. Valid by Evan Cheng · 19 years ago
  19. 60c07e1 Reorg. No functionality change. by Evan Cheng · 19 years ago
  20. 507b0aa Fix JIT on non MacOS X i386 systems. by Evan Cheng · 19 years ago
  21. 441a570 These are already implemented by Andrew Lenharth · 19 years ago
  22. 78c252c 0 offsets for memory operands by Andrew Lenharth · 19 years ago
  23. 775ff18 Should just use xorps to clear XMM registers for all data types. pxor is also one byte longer. by Evan Cheng · 19 years ago
  24. be33dd9 Let X86CompilationCallback pass previous frame and return address to X86CompilationCallback2. Remove alloca hack. by Evan Cheng · 19 years ago
  25. 09c5457 Add shift and rotate by 1 instructions / patterns. by Evan Cheng · 19 years ago
  26. a8e83ec Always use xorps to clear XMM registers. by Evan Cheng · 19 years ago
  27. d3f6981 Move .literal4 and .literal8 support into AsmPrinter.cpp by Evan Cheng · 19 years ago
  28. 2c79de8 Hide x86 symbols by Chris Lattner · 19 years ago
  29. 9525528 Use hidden visibility to make symbols in an anonymous namespace get by Chris Lattner · 19 years ago
  30. 2a41a98 shrink libllvmgcc.dylib another 25K by Chris Lattner · 19 years ago
  31. 33c36f30 Doh. by Evan Cheng · 19 years ago
  32. ee12e8f Oops. Need to keep CP index. by Evan Cheng · 19 years ago
  33. 07103d3 Darwin puts float and double literal constants into literal4 and literal8 sections. by Evan Cheng · 19 years ago
  34. 7794bd3 this case isn't handled by Andrew Lenharth · 19 years ago
  35. 49e4415 handle the "mov reg1, reg2" case in isMoveInstr by Rafael Espindola · 19 years ago
  36. cccef1c Don't match 64-bit bitfield inserts into rlwimi's. todo add rldimi. :) by Chris Lattner · 19 years ago
  37. 6b76b96 Fix ppc64 jump tables by Chris Lattner · 19 years ago
  38. 4df24f2 Remove dead code. by Evan Cheng · 19 years ago
  39. 9f029a6 Print stubs for external globals right. by Chris Lattner · 19 years ago
  40. f89437d Implement 64-bit select, bswap, etc. by Chris Lattner · 19 years ago
  41. e4172be Add a pattern for i64 sra. Print 8-byte units with a space between the .quad by Chris Lattner · 19 years ago
  42. 7ffa9ab Fix rewriting frame offsets with ixaddr instructions, which implicitly shift by Chris Lattner · 19 years ago
  43. 5f9faea PPC doesn't have bit converts to/from i64 by Chris Lattner · 19 years ago
  44. 2e6b77d Add 64-bit MTCTR so that indirect calls work. by Chris Lattner · 19 years ago
  45. 1fd8110 Fix an incorrect store pattern. This fixes em3d. by Chris Lattner · 19 years ago
  46. 563ecfb Implement 64-bit undef, sub, shl/shr, srem/urem by Chris Lattner · 19 years ago
  47. 7b0c58c Use i32 for shift amounts instead of i64. This gets bisort working. by Chris Lattner · 19 years ago
  48. 00659b1 Add zextload from i32 -> i64, with this, perimeter works. by Chris Lattner · 19 years ago
  49. 7e097e4 Print darwin stub stuff correctly in 64-bit mode. With this, treeadd works in by Chris Lattner · 19 years ago
  50. 529c233 Fix variable shadowing issue by Chris Lattner · 19 years ago
  51. c08f902 Implement a bunch of 64-bit cleanliness work. With this, treeadd builds (but by Chris Lattner · 19 years ago
  52. 041e9d3 Rearrange compares, add ADDI8, add sext from 32-to-64 bit register by Chris Lattner · 19 years ago
  53. c91a475 Improve PPC64 calling convention support by Chris Lattner · 19 years ago
  54. 924c576 Remove two more definitions by Chris Lattner · 19 years ago
  55. 7b4e478 remove two unused instructions. by Chris Lattner · 19 years ago
  56. da08d2c Simplify X86CompilationCallback: always align to 16-byte boundary; don't save EAX/EDX if unnecessary. by Evan Cheng · 19 years ago
  57. 89d67fa Add and sort "sections" in debug lines. This always stepping through by Jim Laskey · 19 years ago
  58. 74cb064 Eliminate unneeded parameter. by Evan Cheng · 19 years ago
  59. 22f7131 variable_ops instructions such as call can have any number of operands. by Evan Cheng · 19 years ago
  60. df97cc6 Add memory operand and int regs by Andrew Lenharth · 19 years ago
  61. 1725599 inline asm, at least for floats by Andrew Lenharth · 19 years ago
  62. d1aab35 fix argument problem by Andrew Lenharth · 19 years ago
  63. ef95710 Correct returns of 64-bit values, though they seemed to work before... by Chris Lattner · 19 years ago
  64. 7f7b346e Make these predicates correct in 64-bit mode too. by Chris Lattner · 19 years ago
  65. b410dc9 Rename OR4 -> OR. Move some PPC64-specific stuff to the 64-bit file by Chris Lattner · 19 years ago
  66. 96dc5e5 remove unused flag by Chris Lattner · 19 years ago
  67. f2c5bca add some logical ops by Chris Lattner · 19 years ago
  68. 4b25b40 remove some unused patterns by Chris Lattner · 19 years ago
  69. 3ae5eef Add some more immediate patterns. This allows us to compile: by Chris Lattner · 19 years ago
  70. eded521 Instead of li/xoris use li/oris. Note that this doesn't work if bit 15 is by Chris Lattner · 19 years ago
  71. 0ea70b2 Add some 64-bit logical ops. by Chris Lattner · 19 years ago
  72. e3db4da __i386__, __i386, etc. are not defined for x86-64. Use __x86_64__. by Evan Cheng · 19 years ago
  73. dd58343 64-bit bugfix: 0xFFFF0000 cannot be formed with a single lis. by Chris Lattner · 19 years ago
  74. f27bb6d Add some patterns for globals, so we can now compile this: by Chris Lattner · 19 years ago
  75. 4e85e64 Remove some now-unneeded casts from instruction patterns. With the casts by Chris Lattner · 19 years ago
  76. 047854f Add some patterns for ppc64 by Chris Lattner · 19 years ago
  77. 30da68a Remove some ugly now-redundant casts. by Chris Lattner · 19 years ago
  78. a973993 Fix some mismatched type constraints by Chris Lattner · 19 years ago
  79. b214950 Minor clean up. by Evan Cheng · 19 years ago
  80. 58421d7 initial implementation of ARMRegisterInfo::eliminateFrameIndex by Rafael Espindola · 19 years ago
  81. 357edf8 A new entry. by Evan Cheng · 19 years ago
  82. b1d26f6 Implement the getPointerRegClass method, which is required for the ptr_rc by Chris Lattner · 19 years ago
  83. 54edc84 Later models likely to have Yonah like attributes. by Evan Cheng · 19 years ago
  84. a24b761 Upgrade some load/store instructions to use the proper addressing mode stuff. by Chris Lattner · 19 years ago
  85. 66d7ebb In 64-bit mode, addr mode operands use G8RC instead of GPRC. by Chris Lattner · 19 years ago
  86. 059ca0f fix some assumptions that pointers can only be 32-bits. With this, we can by Chris Lattner · 19 years ago
  87. 956f43c Split 64-bit instructions out into a separate .td file by Chris Lattner · 19 years ago
  88. 8fa05da Force 64-bit register availability in 64-bit mode. For real. by Chris Lattner · 19 years ago
  89. af89fa6 Remove the -darwin and -aix llc options, inferring darwinism and aixism from by Chris Lattner · 19 years ago
  90. 1790d44 Don't pass target name into TargetData anymore, it is never used or needed. by Chris Lattner · 19 years ago
  91. acbc07a Remove ctor with each piece specifyable (which causes overload ambiguities), by Chris Lattner · 19 years ago
  92. 7c1fb5f Document the subtarget features better, make sure that 64-bit mode, 64-bit by Chris Lattner · 19 years ago
  93. a7a5854 Rename some subtarget features. A CPU now can *have* 64-bit instructions, by Chris Lattner · 19 years ago
  94. 94de9a8 First baby step towards ppc64 support. This adds a new -march=ppc64 backend by Chris Lattner · 19 years ago
  95. 8e173de Add a note that Nate noticed. by Chris Lattner · 19 years ago
  96. f8a01a9 1. Support standard dwarf format (was bootstrapping in Apple format.) by Jim Laskey · 19 years ago
  97. 31f7be9 Vector extract / insert index operand should have ptr type. by Evan Cheng · 19 years ago
  98. a7dc4a5 Type of extract_element index operand should be iPTR. by Evan Cheng · 19 years ago
  99. 015188f Type of vector extract / insert index operand should be iPTR. by Evan Cheng · 19 years ago
  100. fae2994 X86 call instructions can take variable number of operands. Parameters of by Evan Cheng · 19 years ago