- 3c0f9cc Check in some intermediate code that adds a skeleton for matching vsplt* by Chris Lattner · 19 years ago
- 08e25de fix typo by Chris Lattner · 19 years ago
- 556aae0 add vsplat instructions, fix sched description for vperm by Chris Lattner · 19 years ago
- f1d0b2b Custom lower arbitrary VECTOR_SHUFFLE's to VPERM. by Chris Lattner · 19 years ago
- abdff1e add the vperm instruction by Chris Lattner · 19 years ago
- b2177b9 Custom lower SCALAR_TO_VECTOR into lve*x. by Chris Lattner · 19 years ago
- 528180e add support for vector undef by Chris Lattner · 19 years ago
- a17409d minor fixes by Chris Lattner · 19 years ago
- 0a7bff0 we don't use lmw/stmw. When we want them they are easy enough to add by Chris Lattner · 19 years ago
- 79691bc Fix subfic to match subc by default instead of sub so that it is correctly by Nate Begeman · 19 years ago
- 81e8097 Remove BRTWOWAY* by Nate Begeman · 19 years ago
- be80fc8 Strangely, calls clobber call-clobbered vector regs. Whodathoughtit? by Chris Lattner · 19 years ago
- 335fd3c Add support for copying registers. still needed: spilling and reloading them by Chris Lattner · 19 years ago
- 133decd Update scheduling info for vrsave instruction by Nate Begeman · 19 years ago
- 1877ec9 For functions that use vector registers, save VRSAVE, mark used by Chris Lattner · 19 years ago
- fd97734 Mark instructions that are cracked by the PPC970 decoder as such. by Chris Lattner · 19 years ago
- 88d211f Several big changes: by Chris Lattner · 19 years ago
- bbf1c72 implement TII::insertNoop by Chris Lattner · 19 years ago
- 5126984 Compile this: by Chris Lattner · 19 years ago
- 551bf3f kill ADD_PARTS & SUB_PARTS and replace them with fancy new ADDC, ADDE, SUBC by Nate Begeman · 19 years ago
- 789fd42 Add missing patterns for andi. and andis., fixing test/Regression/CodeGen/ by Nate Begeman · 20 years ago
- cedc6f4 PHI and INLINEASM are now built-in instructions provided by Target.td by Chris Lattner · 20 years ago
- a613d26 ahem :) by Chris Lattner · 20 years ago
- 35ef913 Add bswap, rotl, and rotr nodes by Nate Begeman · 20 years ago
- 49dddb2 Remove a comment that no longer applies. by Nate Begeman · 20 years ago
- e5cf122 add ret void support back by Chris Lattner · 20 years ago
- 6da8d99 New DAG node properties SNDPInFlag, SNDPOutFlag, and SNDPOptInFlag to replace by Evan Cheng · 20 years ago
- abf6d17 Added initial support for DEBUG_LABEL allowing debug specific labels to be by Jim Laskey · 20 years ago
- 5bf6f25 Add unique id to debug location for debug label use (work in progress.) by Jim Laskey · 20 years ago
- b73628b Add support for generating v4i32 altivec code by Nate Begeman · 20 years ago
- 2b4ea79 Added field noResults to Instruction. by Evan Cheng · 20 years ago
- 171049d * Removed the use of FLAG. Now use hasFlagIn and hasFlagOut instead. by Evan Cheng · 20 years ago
- 6a3bfd9 Flip the meaning of FPContractions to reflect Requires<[]> change. by Evan Cheng · 20 years ago
- 9e4dd9d Pattern-match return. Includes gross hack! by Nate Begeman · 20 years ago
- 7fd1edd Convert load/store over to being pattern matched by Nate Begeman · 20 years ago
- f5395ce Added source file/line correspondence for dwarf (PowerPC only at this point.) by Jim Laskey · 20 years ago
- f492f99 Add a second vector type to the VRRC register class, and fix some patterns by Nate Begeman · 20 years ago
- a07da92 Use the new predicate support that Evan Cheng added to remove some code by Nate Begeman · 20 years ago
- 8c75ef9 Added predicate !NoExcessFPPrecision to FMADD, FMADDS, FMSUB, and FMSUBS. by Evan Cheng · 20 years ago
- 3fb6877 Add support for fmul node of type v4f32. by Nate Begeman · 20 years ago
- 993aeb2 Prepare support for AltiVec multiply, divide, and sqrt. by Nate Begeman · 20 years ago
- d717b19 Remove type casts that are no longer needed by Chris Lattner · 20 years ago
- 28a6b02 Add support for TargetConstantPool nodes to the dag isel emitter, and use by Nate Begeman · 20 years ago
- 0976122 Add support patterns to many load and store instructions which will by Nate Begeman · 20 years ago
- 4172b10 Use new PPC-specific nodes to represent shifts which require the 6-bit by Chris Lattner · 20 years ago
- bd05982 Add some explicit type casts so that tblgen knows the type of the shift by Chris Lattner · 20 years ago
- 937a79d Autogen matching code for ADJCALLSTACK[UP|DOWN], thanks to Evan's tblgen by Chris Lattner · 20 years ago
- 60a4ab2 Finish moving uncond br over to .td file, remove from .cpp file. by Chris Lattner · 20 years ago
- 1e48478 Define BR in the .td file now that Evan made tblgen smarter. by Chris Lattner · 20 years ago
- 7ac8e6b Represent the encoding of the SPR instructions as they actually are, so by Nate Begeman · 20 years ago
- 9b14f66 Add the remainder of the AltiVec 4 x float instructions. Further by Nate Begeman · 20 years ago
- 01595c5 Small tweaks noticed while on the plane. by Nate Begeman · 20 years ago
- e4f17a5 Some first bits of AltiVec stuff: Instruction Formats, Encodings, and by Nate Begeman · 20 years ago
- 3e7f86a disentangle call operands from branch operands a bit by Chris Lattner · 20 years ago
- 490ad08 Generate LA and ADDIS when possible. by Chris Lattner · 20 years ago
- 860e886 Add an initial hack at legalizing GlobalAddress into the appropriate nodes by Chris Lattner · 20 years ago
- bae5b3c LI could theoretically be used for the lo-part of a global address, just like by Chris Lattner · 20 years ago
- 422b0ce Patch to clean up function call pseudos and support the BLA instruction, by Nate Begeman · 20 years ago
- 6df2507 add support for branch on ordered/unordered. by Chris Lattner · 20 years ago
- 6e61ca6 autogen undef by Chris Lattner · 20 years ago
- 3075a4e Allow pseudos to have patterns, no functionality change by Chris Lattner · 20 years ago
- 9c73f09 Autogen fsel by Chris Lattner · 20 years ago
- e6115b3 Autogen a few new ppc-specific nodes by Chris Lattner · 20 years ago
- dabb829 Instead of aborting if not a case we can handle specially, break out and by Chris Lattner · 20 years ago
- ae1641c Match rotate. This does actually match the rotates in an rc5 cipher, but I by Nate Begeman · 20 years ago
- 12a9234 Add some more patterns for i64 on ppc by Nate Begeman · 20 years ago
- 5384214 Added InstrSchedClass to each of the PowerPC Instructions. by Jim Laskey · 20 years ago
- 2d5aff7 Write patterns for the various shl and srl patterns that don't involve by Nate Begeman · 20 years ago
- f6cd147 now that tblgen is smarter, use integers directly. This should help Andrew too by Chris Lattner · 20 years ago
- 8be1fa5 Convert these cases to patterns by Chris Lattner · 20 years ago
- 8d94832 Woo, it kinda works. We now generate this atrociously bad, but correct, by Nate Begeman · 20 years ago
- da32c9e Make a new reg class for 64 bit regs that aliases the 32 bit regs. This by Nate Begeman · 20 years ago
- 841d12d Fix the JIT encoding of LWA, LD, STD, and STDU. by Chris Lattner · 20 years ago
- 1d9d742 First bits of 64 bit PowerPC stuff, currently disabled. A lot of this is by Nate Begeman · 20 years ago
- e0b2e63 Add a pattern for FSQRTS by Chris Lattner · 20 years ago
- f379997 Rename PowerPC*.td -> PPC*.td by Chris Lattner · 20 years ago
- 7cb6491 Add patterns for FP round/extend by Chris Lattner · 20 years ago
- 7b1fe15 These definitions have been moved to common code. by Chris Lattner · 20 years ago
- dff06f4 add patterns for float binops and fma ops by Chris Lattner · 20 years ago
- 43f07a4 another solution to the fsel issue. Instead of having 4 variants, just force by Chris Lattner · 20 years ago
- 867940d fsel can take a different FP type for the comparison and for the result. As such by Chris Lattner · 20 years ago
- 919c032 Modify the ppc backend to use two register classes for FP: F8RC and F4RC. by Chris Lattner · 20 years ago
- 67ab118 Add a bunch of patterns for F64 FP ops, add some more integer ops by Chris Lattner · 20 years ago
- c7a37a5 tblgen autogens this pattern now by Chris Lattner · 20 years ago
- 221e53c now that tblgen is smarter, this pattern is not needed. Also, tblgen by Chris Lattner · 20 years ago
- 79d0e9f Codegen ADD X, IMM -> addis/addi if needed. This implements PowerPC/fold-li.ll by Chris Lattner · 20 years ago
- e025574 add a patter for SUBFIC by Chris Lattner · 20 years ago
- 0648ccf Mark int binops as int-only, add FP binops. Mark FADD/FMUL as commutative but by Chris Lattner · 20 years ago
- a5cac6f Mark associative nodes as associative by Chris Lattner · 20 years ago
- 645992f Nate pointed out that mulh[us] are commutative as well. Thanks! by Chris Lattner · 20 years ago
- 6bcf1b7 expose commutativity information by Chris Lattner · 20 years ago
- cfc828a add support for missed eqv tests by Chris Lattner · 20 years ago
- 91da862 learn to codegen not as NOR instead of xoris/xori by Chris Lattner · 20 years ago
- 30e21a4 minor pattern shuffling by Chris Lattner · 20 years ago
- ea874f3 Teach the dag isel generator how to construct arbitrary immediates. The by Chris Lattner · 20 years ago
- 4ac85b3 disable this for now by Chris Lattner · 20 years ago
- 43ef131 give all operands names by Chris Lattner · 20 years ago
- 4345a4a Fix some issues exposed by more testing. XORIS had the wrong operands by Chris Lattner · 20 years ago
- c36d065 Fix some bugs noticed by new checking code by Chris Lattner · 20 years ago
- 043870d Teach the code generator that rlwimi is commutable if the rotate amount by Chris Lattner · 20 years ago