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gerrit-public.fairphone.software / fp2-dev / platform / external / llvm / 3fd0018af1b692cabfa5a002bf41f1e756aa9dde / utils / TableGen / InstrInfoEmitter.cpp
  1. 1a2f988 Move various generated tables into read-only memory, fixing up const correctness along the way. by Benjamin Kramer · 13 years ago
  2. 7c78888 Move TableGen's parser and entry point into a library by Peter Collingbourne · 13 years ago
  3. c291e2f Add target hook for pseudo instruction expansion. by Jakob Stoklund Olesen · 13 years ago
  4. 83a8031 Restore hasPostISelHook tblgen flag. by Andrew Trick · 13 years ago
  5. 4815d56 ARM isel bug fix for adds/subs operands. by Andrew Trick · 13 years ago
  6. 37fefc2 Follow up to r138791. by Evan Cheng · 13 years ago
  7. 05bce0b Unconstify Inits by David Greene · 13 years ago
  8. f37dd02 [AVX] Constify Inits by David Greene · 13 years ago
  9. 20722b6 Eliminate "const" from extern const to fix breakeage since r135184 on msvc. by NAKAMURA Takumi · 13 years ago
  10. 5196c12 Add a new field to MCOperandInfo that contains information about the type of the Operand. by Benjamin Kramer · 13 years ago
  11. c60f9b7 Next round of MC refactoring. This patch factor MC table instantiations, MC by Evan Cheng · 13 years ago
  12. 1688441 Add a target-indepedent entry to MCInstrDesc to describe the encoded size of an opcode. Switch ARM over to using that rather than its own special MCInstrDesc bits. by Owen Anderson · 13 years ago
  13. d568b3f Revert r134921, 134917, 134908 and 134907. They're causing failures by Eric Christopher · 13 years ago
  14. d4a9066 [AVX] Make Inits Foldable by David Greene · 13 years ago
  15. 9421470 - Added MCSubtargetInfo to capture subtarget features and scheduling by Evan Cheng · 13 years ago
  16. 4db3cff Hide the call to InitMCInstrInfo into tblgen generated ctor. by Evan Cheng · 13 years ago
  17. 94b01f6 Add MCInstrInfo registeration machinery. by Evan Cheng · 13 years ago
  18. 22fee2d Merge XXXGenRegisterNames.inc into XXXGenRegisterInfo.inc by Evan Cheng · 13 years ago
  19. e837dea - Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo and by Evan Cheng · 13 years ago
  20. 4db3748 Remove RCBarriers from TargetInstrDesc. by Evan Cheng · 13 years ago
  21. bea6f61 Add support for alternative register names, useful for instructions whose operands are logically equivalent to existing registers, but happen to be printed specially. For example, an instruciton that prints d0[0] instead of s0. by Owen Anderson · 13 years ago
  22. ae1920b Give CodeGenRegisterClass a real sorted member set. by Jakob Stoklund Olesen · 13 years ago
  23. 0f040a2 - Add "Bitcast" target instruction property for instructions which perform by Evan Cheng · 14 years ago
  24. c4af463 Remove ARM isel hacks that fold large immediates into a pair of add, sub, and, by Evan Cheng · 14 years ago
  25. c240bb0 factor the operand list (and related fields/operations) out of by Chris Lattner · 14 years ago
  26. f523e47 Revert r114703 and r114702, removing the isConditionalMove flag from instructions. After further by Owen Anderson · 14 years ago
  27. 5716180 Add an TargetInstrDesc bit to indicate that a given instruction is a conditional move. by Owen Anderson · 14 years ago
  28. 73739d0 Add back in r109901, which adds a Compare flag to the target instructions. It's by Bill Wendling · 14 years ago
  29. 5b55ff0 Revert r109901. The implementation of <rdar://problem/7405933> (r110423) doesn't by Bill Wendling · 14 years ago
  30. 1844b1a Add a "Compare" flag to the target instruction descriptor. This will be used by Bill Wendling · 14 years ago
  31. a606d95 Start TargetRegisterClass indices at 0 instead of 1, so that by Dan Gohman · 14 years ago
  32. 622dffd How about ULL... by Eric Christopher · 14 years ago
  33. 99405df Reapply r105521, this time appending "LLU" to 64 bit by Bruno Cardoso Lopes · 14 years ago
  34. fddb766 Replace TSFlagsFields and TSFlagsShifts with a simpler TSFlags field. by Jakob Stoklund Olesen · 15 years ago
  35. 70feca4 Teach TableGen to understand X.Y notation in the TSFlagsFields strings. by Jakob Stoklund Olesen · 15 years ago
  36. e14d2e2 Finally change the instruction looking map to be a densemap from by Chris Lattner · 15 years ago
  37. 6a91b18 make inst_begin/inst_end iterate over InstructionsByEnumValue. by Chris Lattner · 15 years ago
  38. 01dcecc revert 98912 by Chris Lattner · 15 years ago
  39. a28bc68 make inst_begin/inst_end iterate over InstructionsByEnumValue. by Chris Lattner · 15 years ago
  40. f650278 change Target.getInstructionsByEnumValue to return a reference by Chris Lattner · 15 years ago
  41. a7d479c Introduce a new CodeGenInstruction::ConstraintInfo class by Chris Lattner · 15 years ago
  42. 518bb53 move target-independent opcodes out of TargetInstrInfo by Chris Lattner · 15 years ago
  43. 243a32f Remove DEBUG_DECLARE, looks like we don't need it. by Dale Johannesen · 15 years ago
  44. d203520 Add DEBUG_DECLARE. Not used yet. by Dale Johannesen · 15 years ago
  45. 87563b3 Add DEBUG_VALUE. Not used yet. by Dale Johannesen · 15 years ago
  46. 533297b Rename usesCustomDAGSchedInserter to usesCustomInserter, and update a by Dan Gohman · 15 years ago
  47. 799d697 Add instruction flags: hasExtraSrcRegAllocReq and hasExtraDefRegAllocReq. When by Evan Cheng · 15 years ago
  48. 26207e5 Introduce the TargetInstrInfo::KILL machine instruction and get rid of the by Jakob Stoklund Olesen · 15 years ago
  49. 23132b1 prune the #includes in raw_ostream.h by moving a by Chris Lattner · 15 years ago
  50. cb778a8 1. Introduce a new TargetOperandInfo::getRegClass() helper method by Chris Lattner · 15 years ago
  51. a938ac6 make ptr_rc derive from a new PointerLikeRegClass tblgen class. by Chris Lattner · 15 years ago
  52. 1a55180 Replace std::iostreams with raw_ostream in TableGen. by Daniel Dunbar · 15 years ago
  53. 88c7af0 Rename COPY_TO_SUBCLASS to COPY_TO_REGCLASS, and generalize by Dan Gohman · 16 years ago
  54. f8c7394 Add a new TargetInstrInfo MachineInstr opcode, COPY_TO_SUBCLASS. by Dan Gohman · 16 years ago
  55. 15511cf Rename isSimpleLoad to canFoldAsLoad, to better reflect its meaning. by Dan Gohman · 16 years ago
  56. b89be61 Add RCBarriers to TargetInstrDesc. It's a list of register classes the given instruction can "clobber". For example, on x86 the call instruction can modify all of the XMM and fp stack registers. by Evan Cheng · 16 years ago
  57. 4406604 Split ISD::LABEL into ISD::DBG_LABEL and ISD::EH_LABEL, eliminating by Dan Gohman · 16 years ago
  58. e4c67cd Teach the DAGISelEmitter to not compute the variable_ops operand by Dan Gohman · 16 years ago
  59. d35121a Fix a tblgen problem handling variable_ops in tblgen instruction by Dan Gohman · 16 years ago
  60. 8370d38 Add a flag to indicate that an instruction is as cheap (or cheaper) than a move by Bill Wendling · 16 years ago
  61. ee4fa19 Move instruction flag inference out of InstrInfoEmitter and into by Dan Gohman · 17 years ago
  62. c929823 Make insert_subreg a two-address instruction, vastly simplifying LowerSubregs pass. Add a new TII, subreg_to_reg, which is like insert_subreg except that it takes an immediate implicit value to insert into rather than a register. by Christopher Lamb · 17 years ago
  63. 20ccded Remove isImplicitDef TargetInstrDesc flag. by Evan Cheng · 17 years ago
  64. da47e6e Replace all target specific implicit def instructions with a target independent one: TargetInstrInfo::IMPLICIT_DEF. by Evan Cheng · 17 years ago
  65. a844bde SDIsel processes llvm.dbg.declare by recording the variable debug information descriptor and its corresponding stack frame index in MachineModuleInfo. This only works if the local variable is "homed" in the stack frame. It does not work for byval parameter, etc. by Evan Cheng · 17 years ago
  66. a22edc8 Simplify the side effect stuff a bit more and make licm/sinking by Chris Lattner · 17 years ago
  67. ba7e756 Start inferring side effect information more aggressively, and fix many bugs in the by Chris Lattner · 17 years ago
  68. 214884b if an instr lacks a pattern, assume it has side effects (unless never has s-e is true). by Chris Lattner · 17 years ago
  69. bc0b9f7 start inferring 'no side effects'. by Chris Lattner · 17 years ago
  70. 8926038 Infer mayload by Chris Lattner · 17 years ago
  71. 710e995 realize that instructions who match intrinsics that read memory read memory. by Chris Lattner · 17 years ago
  72. dcc8b4f add a mayLoad property for machine instructions, a correlary to mayStore. by Chris Lattner · 17 years ago
  73. 749c6f6 rename TargetInstrDescriptor -> TargetInstrDesc. by Chris Lattner · 17 years ago
  74. 0ff2396 Rename all the M_* flags to be namespace qualified enums, and switch by Chris Lattner · 17 years ago
  75. 8f707e1 rename hasVariableOperands() -> isVariadic(). Add some comments. by Chris Lattner · 17 years ago
  76. 4764189 Move M_* flags down in the file. Move SchedClass up in the by Chris Lattner · 17 years ago
  77. af3eb7c the name field of instructions is never set to a non-empty string, by Chris Lattner · 17 years ago
  78. 8ca5c67 Add predicates methods to TargetOperandInfo, and switch all clients by Chris Lattner · 17 years ago
  79. 834f1ce rename isLoad -> isSimpleLoad due to evan's desire to have such a predicate. by Chris Lattner · 17 years ago
  80. 2e48a70 rename isStore -> mayStore to more accurately reflect what it captures. by Chris Lattner · 17 years ago
  81. c8478d8 Change the 'isStore' inferrer to look for 'SDNPMayStore' by Chris Lattner · 17 years ago
  82. e67bde5 set the 'isstore' flag for instructions whose pattern is an by Chris Lattner · 17 years ago
  83. 2d51a4c remove some old hacky code that tried to infer whether a store by Chris Lattner · 17 years ago
  84. a529a37 rearrange some code to allow inferring instr info from the pattern of the instr, but don't do so yet. by Chris Lattner · 17 years ago
  85. 5fbe275 final cleanups. by Chris Lattner · 17 years ago
  86. ef8339b further simplifications and cleanup by Chris Lattner · 17 years ago
  87. 951740a simplify some code by Chris Lattner · 17 years ago
  88. 7b11712 split enum emission out from InstrInfoEmitter into it's own tblgen backend. by Chris Lattner · 17 years ago
  89. 2c36aff tblgen shouldn't include headers from llvm codegen. by Chris Lattner · 17 years ago
  90. 3060910 remove attributions from utils. by Chris Lattner · 17 years ago
  91. 6b1da9c Add flags to indicate that there are "never" side effects or that there "may be" by Bill Wendling · 17 years ago
  92. 3dd298f Oops. Forgot these. by Evan Cheng · 17 years ago
  93. 20ab290 Add a flag for indirect branch instructions. by Owen Anderson · 17 years ago
  94. b591082 Added TargetInstrDescriptor::numDefs - num of results. by Evan Cheng · 17 years ago
  95. 08d5207 Add target independent MachineInstr's to represent subreg insert/extract in MBB's. PR1350 by Christopher Lamb · 17 years ago
  96. 88cc092 Try committing again. Add OptionalDefOperand. Remove clobbersPred. by Evan Cheng · 17 years ago
  97. c419bd3 ImmutablePredicateOperand is no more. by Evan Cheng · 17 years ago
  98. 8012b07 Instructions with ImmutablePredicateOperand aren't really predicable since their predicates are fixed at isel time. by Evan Cheng · 17 years ago
  99. d45eddd Revert the earlier change that removed the M_REMATERIALIZABLE machine by Dan Gohman · 17 years ago
  100. 82a87a0 Replace M_REMATERIALIZIBLE and the newly-added isOtherReMaterializableLoad by Dan Gohman · 17 years ago