- af1d8ca Get rid of the EdgeMapping map. Instead, just check for BasicBlock by Dan Gohman · 15 years ago
- 891ff8f EmitDbgValue doesn't need its EdgeMapping argument. by Dan Gohman · 15 years ago
- fdb42fa Add DBG_VALUE handling for byval parameters; this by Dale Johannesen · 15 years ago
- 962021b - Move TargetLowering::EmitTargetCodeForFrameDebugValue to TargetInstrInfo and rename it to emitFrameIndexDebugValue. by Evan Cheng · 15 years ago
- 3fb150a Fix -Wcast-qual warnings. by Dan Gohman · 15 years ago
- 4ec9bd9 Scheduler assumes SDDbgValue nodes are in source order. That's true currently. But add an assertion to verify it. by Evan Cheng · 15 years ago
- 167bda4 Remove a fixme that doesn't make sense any more. by Evan Cheng · 15 years ago
- bfcb305 Change how dbg_value sdnodes are converted into machine instructions. Their placement should be determined by the relative order of incoming llvm instructions. The scheduler will now use the SDNode ordering information to determine where to insert them. A dbg_value instruction is inserted after the instruction with the last highest source order and before the instruction with the next highest source order. It will optimize the placement by inserting right after the instruction that produces the value if they have consecutive order numbers. by Evan Cheng · 15 years ago
- a8efe28 Rename SDDbgValue.h to SDNodeDbgValue.h for consistency. by Evan Cheng · 15 years ago
- bfdf7f3 Progress towards shepherding debug info through SelectionDAG. by Dale Johannesen · 15 years ago
- 736a6ea Change the scheduler from adding nodes in allnodes order by Chris Lattner · 15 years ago
- 42dae2d Enable pre-regalloc scheduling load clustering by default. by Evan Cheng · 16 years ago
- c589e03 Teach pre-regalloc scheduler to schedule loads from nearby addresses. It may improve cache locality. This is controlled by -cluster-loads for now. by Evan Cheng · 16 years ago
- 84fa822 Change errs() to dbgs(). by David Greene · 16 years ago
- b4e6a5d Changes from review: by Bill Wendling · 16 years ago
- 819309e Reapply r91392, it was only unmasking the bug, and since TOT is still broken having it reverted does no good. by Daniel Dunbar · 16 years ago
- 222518d Revert "Initial work on disabling the scheduler. This is a work in progress, and by Daniel Dunbar · 16 years ago
- 614407a Initial work on disabling the scheduler. This is a work in progress, and this by Bill Wendling · 16 years ago
- bcea859 Create a new InstrEmitter class for translating SelectionDAG nodes by Dan Gohman · 16 years ago
- 98976e4 The ScheduleDAG framework now requires an AliasAnalysis argument, though by Dan Gohman · 16 years ago
- c76909a Improve MachineMemOperand handling. by Dan Gohman · 16 years ago
- c2d98bc Remove some not-really-used variables, as warned by Duncan Sands · 16 years ago
- dc4bdcd Use the schedule itinerary operand use/def cycle information to adjust dependence edge latency for post-RA scheduling. by David Goodwin · 16 years ago
- 7104616 Add callback to allow target to adjust latency of schedule dependency edge. by David Goodwin · 16 years ago
- 825b72b Split EVT into MVT and EVT, the former representing _just_ a primitive type, while by Owen Anderson · 16 years ago
- e50ed30 Rename MVT to EVT, in preparation for splitting SimpleValueType out into its own struct type. by Owen Anderson · 16 years ago
- 1cd1d98 Move more to raw_ostream, provide support for writing MachineBasicBlock, by Daniel Dunbar · 16 years ago
- 874ae25 Revert 72707 and 72709, for the moment. by Dale Johannesen · 16 years ago
- 4150d83 Make the implicit inputs and outputs of target-independent by Dale Johannesen · 16 years ago
- 8cccf0e Don't set SUnit::hasPhysRegDefs to true unless the defs are by Dan Gohman · 16 years ago
- 3974667 Add a new bit to SUnit to record whether a node has implicit physreg by Dan Gohman · 16 years ago
- db95fa1 Simplify this code; use a while instead of an if and a do-while. by Dan Gohman · 16 years ago
- 47ac0f0 When scheduling a block in parts, keep track of the overall by Dan Gohman · 16 years ago
- 84fbac5 Move ScheduleDAGSDNodes.h to be a private header. Front-ends by Dan Gohman · 17 years ago
- e57187c CreateVirtualRegisters does trivial copy coalescing. If a node def is used by a single CopyToReg, it reuses the virtual register assigned to the CopyToReg. This won't work for SDNode that is a clone or is itself cloned. Disable this optimization for those nodes or it can end up with non-SSA machine instructions. by Evan Cheng · 17 years ago
- 79ce276 Move a few containers out of ScheduleDAGInstrs::BuildSchedGraph by Dan Gohman · 17 years ago
- c29a56d Fix PR3241: Currently EmitCopyFromReg emits a copy from the physical register to a virtual register unless it requires an expensive cross class copy. That means we are only treating "expensive to copy" register dependency as physical register dependency. by Evan Cheng · 17 years ago
- 9aacec1 CheckForPhysRegDependency should not return copy cost. It's not used. No functionality change. by Evan Cheng · 17 years ago
- c9a5b9e Rename BuildSchedUnits to BuildSchedGraph, and refactor the by Dan Gohman · 17 years ago
- e1dfc7d Avoid an unnecessary call to allnodes_size(), which is linear. by Dan Gohman · 17 years ago
- 89b64bd Double the amount of memory reserved for SUnits. This is a by Dan Gohman · 17 years ago
- 9a65d6a Remove some special-case logic in ScheduleDAGSDNodes's by Dan Gohman · 17 years ago
- 3f23744 Fix some register-alias-related bugs in the post-RA scheduler liveness by Dan Gohman · 17 years ago
- 54e4c36 Rewrite the SDep class, and simplify some of the related code. by Dan Gohman · 17 years ago
- 787782f Use ComputeLatency in the MachineInstr scheduler. by Dan Gohman · 17 years ago
- c8c2827 Implement ComputeLatency for MachineInstr ScheduleDAGs. Factor by Dan Gohman · 17 years ago
- 343f0c0 Experimental post-pass scheduling support. Post-pass scheduling by Dan Gohman · 17 years ago