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gerrit-public.fairphone.software / fp2-dev / platform / external / llvm / 49683f3c961379fbc088871a5d6304950f1f1cbc
  1. 49683f3 This patch adds a new NVPTX back-end to LLVM which supports code generation for NVIDIA PTX 3.0. This back-end will (eventually) replace the current PTX back-end, while maintaining compatibility with it. by Justin Holewinski · 12 years ago
  2. 2c7e5c7 Added missing CMN case in Thumb2SizeReduction pass so that LLVM emits 16-bits encoding of CMN instructions. by Sebastian Pop · 12 years ago
  3. 3d142e5 Adds Intel Atom scheduling latencies to X86InstrSystem.td. by Preston Gurd · 12 years ago
  4. 39af944 Pacify GCC's -Wreturn-type by Matt Beaumont-Gay · 12 years ago
  5. 90cb708 Factor the computation of input and output sets into a public interface by Chandler Carruth · 12 years ago
  6. 5095503 Rather than trying to gracefully handle input sequences with repeated by Chandler Carruth · 12 years ago
  7. 6a81f64 Fix a goof with my previous commit by completely returning when we by Chandler Carruth · 12 years ago
  8. 27742c1 Hoist a safety assert from the extraction method into the construction by Chandler Carruth · 12 years ago
  9. 99650c9 Move the CodeExtractor utility to a dedicated header file / source file, by Chandler Carruth · 12 years ago
  10. fd5abd5 Make ARM and Mips use TargetMachine::getTLSModel() by Hans Wennborg · 12 years ago
  11. 31a207a Fix some loops to match coding standards. No functional change intended. by Craig Topper · 12 years ago
  12. 6643d9c Fix up some spacing. No functional change. by Craig Topper · 12 years ago
  13. 5da8a80 Simplify broadcast lowering code. No functional change intended. by Craig Topper · 12 years ago
  14. f3640d7 Allow v16i16 and v32i8 shuffles to be rewritten as narrower shuffles. by Craig Topper · 12 years ago
  15. 98bda3d Add 'landingpad' instructions to the list of instructions to ignore. by Bill Wendling · 12 years ago
  16. 11ac1f8 Simplify shuffle narrowing code a bit. No functional change intended. by Craig Topper · 12 years ago
  17. 338607a Remove the SubRegClasses field from RegisterClass descriptions. by Jakob Stoklund Olesen · 12 years ago
  18. 7855ec6 Remove TargetRegisterClass::SuperRegClasses. by Jakob Stoklund Olesen · 12 years ago
  19. 18efed7 Pass -fcolor-diagnostics when it is supported. This makes a difference when by Rafael Espindola · 12 years ago
  20. e3ee49f Use SuperRegClassIterator for findRepresentativeClass(). by Jakob Stoklund Olesen · 12 years ago
  21. ed277f3 Initialize SparcInstrInfo before SparcTargetLowering. by Jakob Stoklund Olesen · 12 years ago
  22. 89e38f8 Add a SuperRegClassIterator class. by Jakob Stoklund Olesen · 12 years ago
  23. d5003ca A pile of long over-due refactorings here. There are some very, *very* by Chandler Carruth · 12 years ago
  24. a83a6d3 Add a FoldingSetVector datastructure which is analogous to a SetVector, by Chandler Carruth · 12 years ago
  25. ff20496 PR12729: Change 'llvm-objdump' to display the available targets. by Pete Cooper · 12 years ago
  26. 30b8866 Remove accidentally added file. by Jakob Stoklund Olesen · 12 years ago
  27. dd63a06 Use a shared implementation of getMatchingSuperRegClass(). by Jakob Stoklund Olesen · 12 years ago
  28. 1a2a19d Add TargetRegisterClass::getSuperRegIndices(). by Jakob Stoklund Olesen · 12 years ago
  29. 6a0ed18 Emit SuperRegMasks as part of the existing SubClassMask arrays. by Jakob Stoklund Olesen · 12 years ago
  30. 2d524b0 Fix issues with the ARM bl and blx thumb instructions and the J1 and J2 bits by Kevin Enderby · 12 years ago
  31. 9f7af7b Factor the logic for testing whether a basic block is viable for code by Chandler Carruth · 12 years ago
  32. cb348b9 remove calls to calloc if the allocated memory is not used (it was already being done for malloc) by Nuno Lopes · 12 years ago
  33. 26f61a1 Support for target dependent Hexagon VLIW packetizer. by Sirish Pande · 12 years ago
  34. ff9229e Add rudimentary CMake logic for detecting Graphviz. by Ted Kremenek · 12 years ago
  35. 252ef56 add support for calloc to objectsize lowering by Nuno Lopes · 12 years ago
  36. 1d61f28 Fix the type of SubClassMask. by Jakob Stoklund Olesen · 12 years ago
  37. f92be23 Compress tables for getMatchingSuperRegClass(). by Jakob Stoklund Olesen · 12 years ago
  38. 5e74696 Add the half type to the LLVM IR vim syntax highlighting. by Owen Anderson · 12 years ago
  39. b422d0b Fixed disassembler for vstm/vldm ARM VFP instructions. by Silviu Baranga · 12 years ago
  40. 309076f Don't override subreg functions in targets without subregisters. by Jakob Stoklund Olesen · 12 years ago
  41. 71d5646 Extensions of Hexagon V4 instructions. by Sirish Pande · 12 years ago
  42. a199e01 replace 'break's with 'return 0' in visitCallInst code for objectsize, since there is no need to fallback to visitCallSite. by Nuno Lopes · 12 years ago
  43. 28d95b0 Use correct variable in this example. Pointed out by waynix on IRC. by Duncan Sands · 12 years ago
  44. b607264 Use 'unsigned' instead of 'int' in a few places dealing with counts of vector elements. by Craig Topper · 12 years ago
  45. 6b28d35 Fix 256-bit vpshuflw and vpshufhw immediate encoding to handle undefs in the lower half correctly. Missed in r155982. by Craig Topper · 12 years ago
  46. d99d68b Fix two-address pass's aggressive instruction commuting heuristics. It's meant by Evan Cheng · 12 years ago
  47. f12f6df Added TargetRegisterInfo::getAllocatableClass. by Andrew Trick · 12 years ago
  48. e8cd3f2 Whitespace cleanup. by Bill Wendling · 12 years ago
  49. f2c696f [docs] Include the Kaleidescope tutorial in the Sphinx docs build. by Daniel Dunbar · 12 years ago
  50. 062c0a5 Teach DAGCombine the same multiply-by-1.0 folding trick when doing FMAs, just like it now knows for FMULs. by Owen Anderson · 12 years ago
  51. c0f0a93 by Preston Gurd · 12 years ago
  52. 79bbe85 Change the Intel Atom detection code to recognize Lincroft and Medfield. by Preston Gurd · 12 years ago
  53. 363e4b9 Teach DAG combine that multiplication by 1.0 can always be constant folded. by Owen Anderson · 12 years ago
  54. 4599613 Add tools/lld to .gitignore. by Michael J. Spencer · 12 years ago
  55. 2727930 ARM: Add missing two-operand VBIC aliases. by Jim Grosbach · 12 years ago
  56. f657da2 Move llvm-tblgen's StringMatcher into the TableGen library so it can by Douglas Gregor · 12 years ago
  57. 8ed9951 [llvm-c] Make a few function declarations proper prototypes by Anders Waldenborg · 12 years ago
  58. 95f0cf0 This patch continues the work of adding instruction latencies for X86 Atom, by Preston Gurd · 12 years ago
  59. e284985 Revert r155853 by Manman Ren · 12 years ago
  60. 37cb9ac [tsan] typo and style (thanks to Nick Lewycky) by Kostya Serebryany · 12 years ago
  61. 55e7098 The value held in the vector may be RAUW'ed by some of the canonicalization by Bill Wendling · 12 years ago
  62. 0a552d6 Disallow YIELD and other allocated nop hints in pre-ARMv6 architectures. by Richard Barton · 12 years ago
  63. a9a568a Add support for selecting AVX2 vpshuflw and vpshufhw. Add decoding support for AsmPrinter. by Craig Topper · 12 years ago
  64. 38dbb60 Update SmallVector to support move semantics if the host does. by John McCall · 12 years ago
  65. 9679f0f Fix unintentional use of operator bool. by John McCall · 12 years ago
  66. 41827f9 Fix the implementation of MachOObjectFile::isSectionZeroInit so it follows the MachO spec. by Eli Friedman · 12 years ago
  67. 39cc513 Tidy up. Naming conventions. by Jim Grosbach · 12 years ago
  68. dca40aa Remove unneeded break. by Jakub Staszak · 12 years ago
  69. ce00b44 Use dyn_cast instead of checking opcode and cast. by Jakub Staszak · 12 years ago
  70. bf14860 Remove trailing spaces. by Jakub Staszak · 12 years ago
  71. 95dd442 Strip the pointer casts off of allocas so that the selection DAG can find them. by Bill Wendling · 12 years ago
  72. 9023370 Target independent Hexagon Packetizer fix. by Sirish Pande · 12 years ago
  73. 54319e2 ARM: Add a few missing add->sub aliases w/ 'w' suffix. by Jim Grosbach · 12 years ago
  74. 94b590f ARM: allow vanilla expressions for movw/movt. by Jim Grosbach · 12 years ago
  75. 66413b6 by Preston Gurd · 12 years ago
  76. 686c018 MC: Unknown assembler directives are now hard errors. by Jim Grosbach · 12 years ago
  77. 25c7b6e MC: Remove errant EatToEndOfStatement() in asm parser. by Jim Grosbach · 12 years ago
  78. 769ea2f X86: optimization for max-like struct by Manman Ren · 12 years ago
  79. d07d06c X86: Use StackRegister instead of FrameRegister in getFrameIndexReference (to generate debug info for local variables) if stack needs realignment by Alexey Samsonov · 12 years ago
  80. 0998627 Move MipsDisassembler classes into an anonymous namespace. by Benjamin Kramer · 12 years ago
  81. 4ab6fca Regression test for PR2960. by Jay Foad · 12 years ago
  82. 030a341 Value-initialize global to avoid global construction. by Benjamin Kramer · 12 years ago
  83. c201e6e RuntimeDyld cleanup: by Eli Bendersky · 12 years ago
  84. 34df160 YAMLParser: get rid of global ctors & dtors. by Benjamin Kramer · 12 years ago
  85. 7c4ce30 Change the PassManager from a reference to a pointer. by Bill Wendling · 12 years ago
  86. c80e7d2 Allow BMI, AES, F16C, POPCNT, FMA3, and CLMUL to be detected on AMD processors. by Craig Topper · 12 years ago
  87. d98c9e9 RuntimeDyld code cleanup: by Eli Bendersky · 12 years ago
  88. e499cdf Make XOP and FMA4 require SSE4A to match GCC behavior. Use this to simplify Bulldozer feature list. by Craig Topper · 12 years ago
  89. ff72e74 Attempt to handle MRMInitReg in emitVEXOpcodePrefix. Hopefully fixes PR12711. by Craig Topper · 12 years ago
  90. f8b30f9 Removed examples of stack frame inspection which no longer work for old JIT. by Eli Bendersky · 12 years ago
  91. e106d2e Make XOP imply AVX as its needed to legalize the registers types. by Craig Topper · 12 years ago
  92. c49c6e15 Remove HasSSE2 from AES and CLMUL predicates. It's now implied by the HasAES and HasCLMUL predicates. by Craig Topper · 12 years ago
  93. da1a984 Make CLMUL and AES imply SSE2 since its needed to legalize the type. by Craig Topper · 12 years ago
  94. ed39ac5 Enable AVX and FMA4 for AMD Bulldozer processors. by Craig Topper · 12 years ago
  95. 4056a73 An instruction in a loop is not guaranteed to be executed just because the loop by Nick Lewycky · 12 years ago
  96. 973f72a Add support for llvm.arm.neon.vmull* intrinsics to InstCombine. Fixes by Lang Hames · 12 years ago
  97. 39379c5 Add some constantness. No functionality change. by Jakub Staszak · 12 years ago
  98. 16a7651 X86: optimization for -(x != 0) by Manman Ren · 12 years ago
  99. 7a3afa9 ARM: Diagnostics for out of range fixups. by Jim Grosbach · 12 years ago
  100. 887d095 Fix address calculation error from r155744. by Jakob Stoklund Olesen · 12 years ago