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gerrit-public.fairphone.software / fp2-dev / platform / external / llvm / 4d0f7c9f399774121c7eddde84d7c403b37028f2 / lib / Target / X86 / X86InstrMMX.td
  1. 4d0f7c9 remove a confused pattern that is trying to match an address by Chris Lattner · 15 years ago
  2. 8f2b4cc X86InstrInfoSSE.td declares PINSRW as having type v8i16, by Chris Lattner · 15 years ago
  3. 51898d7 by David Greene · 15 years ago
  4. 28c1d29 lower the last of the MRMInitReg instructions in MCInstLower. by Chris Lattner · 15 years ago
  5. eb38ebf Improved widening loads by adding support for wider loads if by Mon P Wang · 15 years ago
  6. 108934c Instruction fixes, added instructions, and AsmString changes in the by Sean Callanan · 15 years ago
  7. 533297b Rename usesCustomDAGSchedInserter to usesCustomInserter, and update a by Dan Gohman · 15 years ago
  8. 7417b76 Add 'isCodeGenOnly' bit to Instruction .td records. by Daniel Dunbar · 15 years ago
  9. a8c6908 Whitespace, 80-column, and isTwoAddress -> Constraints = "" changes. by Eric Christopher · 15 years ago
  10. d2aee8c Remove neverHasSideEffects on MMX_MOVD64rrv164 since it has a matching pattern. by Evan Cheng · 15 years ago
  11. 8d632c1 Use movd instead of movq by Rafael Espindola · 15 years ago
  12. 0c794b8 Fix the instruction encoding. by Rafael Espindola · 15 years ago
  13. def390a Use movq to move 64 bits in and out of mmx registers. Fixes PR4669 by Rafael Espindola · 15 years ago
  14. 3dae284 Add support for MMX VSETCC. by Eli Friedman · 15 years ago
  15. 7675040 Misc encoding fixes; reported on llvmdev. by Eli Friedman · 15 years ago
  16. 5c324d7 "The MMX_MASKMOVQ and MMX_MASKMOVQ64 instructions are labeled as MRMDestMem by Bill Wendling · 15 years ago
  17. 1041553 Get rid of some bogus patterns for X86vzmovl. Don't create VZEXT_MOVL by Eli Friedman · 15 years ago
  18. 1762c14 Get rid of a bogus pattern that interferes with optimization. by Eli Friedman · 15 years ago
  19. d58902a Evan says it's wrong; back out 72808. by Stuart Hastings · 15 years ago
  20. 77648cf Recognize another euphemism for MOVDQ2Q. by Stuart Hastings · 15 years ago
  21. 3b1259b "The instructions MMX_PSADBWrm and MMX_PSADBWrr have opcode 0b11100000 (e0), but by Bill Wendling · 15 years ago
  22. 9008ca6 2nd attempt, fixing SSE4.1 issues and implementing feedback from duncan. by Nate Begeman · 16 years ago
  23. 15684b2 Revert 69952. Causes testsuite failures on linux x86-64. by Rafael Espindola · 16 years ago
  24. b706d29 PR2957 by Nate Begeman · 16 years ago
  25. 242b38b Only v1i16 (i.e. _m64) is returned via RAX / RDX. by Evan Cheng · 16 years ago
  26. 9e5ecb8 Added support for SELECT v8i8 v4i16 for X86 (MMX) by Mon P Wang · 16 years ago
  27. 62fb4f2 Use mmx (punpckldq VR64, (mmx_v_set0)) to clear high 32-bits of a VR64 register. by Evan Cheng · 16 years ago
  28. 15511cf Rename isSimpleLoad to canFoldAsLoad, to better reflect its meaning. by Dan Gohman · 16 years ago
  29. b35ed92 Add more vector move low and zero-extend patterns. by Evan Cheng · 16 years ago
  30. 1dd0086 Make "movdq2q" and "movq2dq" dependent upon having SSE2 because they use the by Bill Wendling · 16 years ago
  31. cb3c51a Nevermind. This broke the bootstrap (?!). by Bill Wendling · 16 years ago
  32. 51e05e7 MOVQ2DQ and MOVQ2DQ use SSE2. We should conditionalize the use of these by Bill Wendling · 16 years ago
  33. 017c260 Provide a 64 bit variant of mmx.maskmovq intrinsic lowering. by Anton Korobeynikov · 16 years ago
  34. 5f6ae30 Remove dead PatLeaf; there are a number of issues around MMX movl that need to be fixed. by Nate Begeman · 16 years ago
  35. a68f901 Add v2f32 (MMX) type to X86. Support is primitive: by Dale Johannesen · 16 years ago
  36. f26ffe9 Implement vector shift up / down and insert zero with ps{rl}lq / ps{rl}ldq. by Evan Cheng · 16 years ago
  37. d880b97 Handle a few more cases of folding load i64 into xmm and zero top bits. by Evan Cheng · 16 years ago
  38. 7e2ff77 Handle vector move / load which zero the destination register top bits (i.e. movd, movq, movss (addr), movsd (addr)) with X86 specific dag combine. by Evan Cheng · 16 years ago
  39. 22b942a Add separate intrinsics for MMX / SSE shifts with i32 integer operands. This allow us to simplify the horribly complicated matching code. by Evan Cheng · 16 years ago
  40. 082948d Fix illegal MMX_MOVDQ2Qrr pattern. vector_extract result must be a scalar value. by Evan Cheng · 17 years ago
  41. 10e8642 Special handling for MMX values being passed in either GPR64 or lower 64-bits of XMM registers. by Evan Cheng · 17 years ago
  42. 80f5404 Fix MMX_MOVQ2DQrr pattern. It's illegal to do a bitconvert from a smaller type to a larger one. by Evan Cheng · 17 years ago
  43. 0416b0a Fix the encoding of the MMX movd that moves from MMX to 64-bit GPR. by Dan Gohman · 17 years ago
  44. a630f4e Add movd instructions to move from MMX registers by Dan Gohman · 17 years ago
  45. fa5a91a Undo 48570. Correctly match mmx shift instructions with an immediate operand. by Evan Cheng · 17 years ago
  46. dff1dca Add intrinsics to match mmx shift builtin's with immediate operand. by Evan Cheng · 17 years ago
  47. da47e6e Replace all target specific implicit def instructions with a target independent one: TargetInstrInfo::IMPLICIT_DEF. by Evan Cheng · 17 years ago
  48. c8e3b14 Clean up my own mess. by Evan Cheng · 17 years ago
  49. b26947e Use the correct instruction encodings for the 64-bit MMX movd. by Anders Carlsson · 17 years ago
  50. efec751 - When DAG combiner is folding a bit convert into a BUILD_VECTOR, it should check if it's essentially a SCALAR_TO_VECTOR. Avoid turning (v8i16) <10, u, u, u> to <10, 0, u, u, u, u, u, u>. Instead, simply convert it to a SCALAR_TO_VECTOR of the proper type. by Evan Cheng · 17 years ago
  51. ba7e756 Start inferring side effect information more aggressively, and fix many bugs in the by Chris Lattner · 17 years ago
  52. dd41527 remove explicit sets of 'neverHasSideEffects' that can now be by Chris Lattner · 17 years ago
  53. 834f1ce rename isLoad -> isSimpleLoad due to evan's desire to have such a predicate. by Chris Lattner · 17 years ago
  54. 4ee451d Remove attribution from file headers, per discussion on llvmdev. by Chris Lattner · 17 years ago
  55. 627c00b Add "mayHaveSideEffects" and "neverHasSideEffects" flags to some instructions. I by Bill Wendling · 17 years ago
  56. 6e141fd Implicit def instructions, e.g. X86::IMPLICIT_DEF_GR32, are always re-materializable and they should not be spilled. by Evan Cheng · 17 years ago
  57. 8a59448 Fix a long standing deficiency in the X86 backend: we would by Chris Lattner · 17 years ago
  58. 071a279 Remove (somewhat confusing) Imp<> helper, use let Defs = [], Uses = [] instead. by Evan Cheng · 17 years ago
  59. 2f39426 Mark load instructions with isLoad = 1. by Evan Cheng · 17 years ago
  60. 73a902b Mark the SSE and MMX load instructions that by Dan Gohman · 17 years ago
  61. b1576f5 Change the x86 assembly output to use tab characters to separate the by Dan Gohman · 17 years ago
  62. c64a1a9 Redo and generalize previously removed opt for pinsrw: (vextract (v4i32 bc (v4f32 s2v (f32 load ))), 0) -> (i32 load ) by Evan Cheng · 17 years ago
  63. 64d80e3 Change instruction description to split OperandList into OutOperandList and by Evan Cheng · 17 years ago
  64. 10404c4 Support generation of GR64 to MMX code in the JIT. by Bill Wendling · 17 years ago
  65. 9388842 Allow a GR64 to be moved into an MMX register via the "movd" instruction. by Bill Wendling · 17 years ago
  66. d45eddd Revert the earlier change that removed the M_REMATERIALIZABLE machine by Dan Gohman · 17 years ago
  67. 82a87a0 Replace M_REMATERIALIZIBLE and the newly-added isOtherReMaterializableLoad by Dan Gohman · 17 years ago
  68. 738a6ec implement the missing maskmovq mmx intrinsic that akor hit. by Chris Lattner · 17 years ago
  69. 69dc533 Add the final MMX instructions. Correct a few wrong patterns. by Bill Wendling · 18 years ago
  70. 71bfd11 Adding more MMX instructions. by Bill Wendling · 18 years ago
  71. 823efee Add FEMMS and ADDQ. Renamed MMX recipes to prepend the MMX_ to them. by Bill Wendling · 18 years ago
  72. 826f36f Unbreak mmx arithmetic. It was barfing trying to do v8i8 arithmetic. by Bill Wendling · 18 years ago
  73. 6dc29ec Add the "unpack low packed data" instructions. This should be the last of by Bill Wendling · 18 years ago
  74. ccc44ad Fix so that pandn is emitted instead of an xor/and combo. Add integer by Bill Wendling · 18 years ago
  75. eebc8a1 Add support for the v1i64 type. This makes better code for this: by Bill Wendling · 18 years ago
  76. b8440a0 PR1260: Add final support to get the QT example to compile. by Bill Wendling · 18 years ago
  77. 02ced83 We generate a shufflevector instruction, so we don't need the builtin intrinsic. by Bill Wendling · 18 years ago
  78. a348c56 Support added for shifts and unpacking MMX instructions. by Bill Wendling · 18 years ago
  79. 1b7a81d And now support for MMX logical operations. by Bill Wendling · 18 years ago
  80. 74027e9 Multiplication support for MMX. by Bill Wendling · 18 years ago
  81. c1fb047 Adding more arithmetic operators to MMX. This is an almost exact copy of by Bill Wendling · 18 years ago
  82. 2f88dcd Added "padd*" support for MMX. Added MMX move stuff to X86InstrInfo so that by Bill Wendling · 18 years ago
  83. c32a7f9 Remove useless pattern fragments. by Bill Wendling · 18 years ago
  84. bc9bffa Properly support v8i8 and v4i16 types. It now converts them to v2i32 for by Bill Wendling · 18 years ago
  85. a31bd27 Add LOAD/STORE support for MMX. by Bill Wendling · 18 years ago
  86. 229baff Add the emms intrinsic for MMX support. by Bill Wendling · 18 years ago
  87. 1693e48 INC / DEC instructions have shorter code size than ADD32ri8, etc. by Evan Cheng · 18 years ago
  88. 069287d X86 integer register classes naming changes. Make them consistent with FP, vector classes. by Evan Cheng · 18 years ago
  89. d2a6d54 SSE / SSE2 conversion intrinsics. by Evan Cheng · 19 years ago
  90. fcf5e21 movnt* and maskmovdqu intrinsics by Evan Cheng · 19 years ago
  91. cc4f047 Instruction encoding bug by Evan Cheng · 19 years ago
  92. 3246e06 Added CVTTPS2PI. by Evan Cheng · 19 years ago
  93. 4a7da36 Didn't mean to check this in. No MMX support yet. by Evan Cheng · 19 years ago
  94. 48090aa - Use movaps to store 128-bit vector integers. by Evan Cheng · 19 years ago
  95. 82521dd - Remove scalar to vector pseudo ops. They are just wrong. by Evan Cheng · 19 years ago
  96. 811ec1c x86 ISD::SCALAR_TO_VECTOR support. by Evan Cheng · 19 years ago
  97. ba753c6 Move a few things around. by Evan Cheng · 19 years ago
  98. 4e4c71e One more round of reorg so sabre doesn't freak out. :-) by Evan Cheng · 19 years ago
  99. ffcb95b Split instruction info into multiple files, one for each of x87, MMX, and SSE. by Evan Cheng · 19 years ago